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From: Rob Herring <robh@kernel.org>
To: Anurup M <anurupvasu@gmail.com>
Cc: mark.rutland@arm.com, will.deacon@arm.com,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com,
	zhangshaokun@hisilicon.com, tanxiaojun@huawei.com,
	xuwei5@hisilicon.com, sanil.kumar@hisilicon.com,
	john.garry@huawei.com, gabriele.paoloni@huawei.com,
	shiju.jose@huawei.com, huangdaode@hisilicon.com,
	wangkefeng.wang@huawei.com, linuxarm@huawei.com,
	dikshit.n@huawei.com, shyju.pv@huawei.com
Subject: Re: [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Date: Thu, 13 Apr 2017 14:44:51 -0500	[thread overview]
Message-ID: <20170413194451.jhi7c62iar5dqvyy@rob-hp-laptop> (raw)
In-Reply-To: <1491303333-140338-1-git-send-email-anurup.m@huawei.com>

On Tue, Apr 04, 2017 at 06:55:33AM -0400, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache and MN PMU.
> 3) Add child nodes of L3C and MN in djtag bindings example.
> 
> Signed-off-by: Anurup M <anurup.m@huawei.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
>  .../devicetree/bindings/arm/hisilicon/djtag.txt    | 29 +++++++
>  .../devicetree/bindings/arm/hisilicon/pmu.txt      | 93 ++++++++++++++++++++++
>  2 files changed, 122 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt

Acked-by: Rob Herring <robh@kernel.org>

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Anurup M <anurupvasu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org,
	will.deacon-5wv7dgnIgG8@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
	tanxiaojun-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
	sanil.kumar-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
	john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	shiju.jose-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	huangdaode-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
	wangkefeng.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	dikshit.n-hv44wF8Li93QT0dZR+AlfA@public.gmane.org,
	shyju.pv-hv44wF8Li93QT0dZR+AlfA@public.gmane.org
Subject: Re: [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Date: Thu, 13 Apr 2017 14:44:51 -0500	[thread overview]
Message-ID: <20170413194451.jhi7c62iar5dqvyy@rob-hp-laptop> (raw)
In-Reply-To: <1491303333-140338-1-git-send-email-anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>

On Tue, Apr 04, 2017 at 06:55:33AM -0400, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache and MN PMU.
> 3) Add child nodes of L3C and MN in djtag bindings example.
> 
> Signed-off-by: Anurup M <anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Shaokun Zhang <zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
>  .../devicetree/bindings/arm/hisilicon/djtag.txt    | 29 +++++++
>  .../devicetree/bindings/arm/hisilicon/pmu.txt      | 93 ++++++++++++++++++++++
>  2 files changed, 122 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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WARNING: multiple messages have this Message-ID (diff)
From: robh@kernel.org (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Date: Thu, 13 Apr 2017 14:44:51 -0500	[thread overview]
Message-ID: <20170413194451.jhi7c62iar5dqvyy@rob-hp-laptop> (raw)
In-Reply-To: <1491303333-140338-1-git-send-email-anurup.m@huawei.com>

On Tue, Apr 04, 2017 at 06:55:33AM -0400, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache and MN PMU.
> 3) Add child nodes of L3C and MN in djtag bindings example.
> 
> Signed-off-by: Anurup M <anurup.m@huawei.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
>  .../devicetree/bindings/arm/hisilicon/djtag.txt    | 29 +++++++
>  .../devicetree/bindings/arm/hisilicon/pmu.txt      | 93 ++++++++++++++++++++++
>  2 files changed, 122 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt

Acked-by: Rob Herring <robh@kernel.org>

  reply	other threads:[~2017-04-13 19:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-04 10:55 [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU Anurup M
2017-04-04 10:55 ` Anurup M
2017-04-13 19:44 ` Rob Herring [this message]
2017-04-13 19:44   ` Rob Herring
2017-04-13 19:44   ` Rob Herring

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