Various minor Display DCE120 cleanups

Various minor Display DCE120 cleanups

[Tom St Denis]

Various small tidy up patches for the dce120 display driver.  Should be
no functional changes.


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[PATCH 1/6] drm/amd/display: Tidy up dce120_timing_generator_enable_advanced_request()

[Tom St Denis]

Simplify the function by removing identical looking code blocks.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 .../display/dc/dce120/dce120_timing_generator.c    | 37 +++++++---------------
 1 file changed, 12 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 245356e72b36..ce5612fe36b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -669,36 +669,23 @@ void dce120_timing_generator_enable_advanced_request(
 				mmCRTC0_CRTC_START_LINE_CONTROL,
 				tg110->offsets.crtc);
 
-
-	if (enable) {
-		set_reg_field_value(
-			value,
-			0,
-			CRTC0_CRTC_START_LINE_CONTROL,
-			CRTC_LEGACY_REQUESTOR_EN);
-	} else {
-		set_reg_field_value(
-			value,
-			1,
-			CRTC0_CRTC_START_LINE_CONTROL,
-			CRTC_LEGACY_REQUESTOR_EN);
-	}
+	set_reg_field_value(
+		value,
+		enable ? 0 : 1,
+		CRTC0_CRTC_START_LINE_CONTROL,
+		CRTC_LEGACY_REQUESTOR_EN);
 
 	/* Program advanced line position acc.to the best case from fetching data perspective to hide MC latency
 	 * and prefilling Line Buffer in V Blank (to 10 lines as LB can store max 10 lines)
 	 */
 	if (v_sync_width_and_b_porch > 10)
-		set_reg_field_value(
-			value,
-			10,
-			CRTC0_CRTC_START_LINE_CONTROL,
-			CRTC_ADVANCED_START_LINE_POSITION);
-	else
-		set_reg_field_value(
-			value,
-			v_sync_width_and_b_porch,
-			CRTC0_CRTC_START_LINE_CONTROL,
-			CRTC_ADVANCED_START_LINE_POSITION);
+		v_sync_width_and_b_porch = 10;
+
+	set_reg_field_value(
+		value,
+		v_sync_width_and_b_porch,
+		CRTC0_CRTC_START_LINE_CONTROL,
+		CRTC_ADVANCED_START_LINE_POSITION);
 
 	dm_write_reg_soc15(tg->ctx,
 			mmCRTC0_CRTC_START_LINE_CONTROL,
-- 
2.12.0

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[PATCH 2/6] drm/amd/display: Fix indentation in dce120_tg_program_timing()

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index ce5612fe36b0..05079662265d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -733,9 +733,9 @@ void dce120_tg_program_timing(struct timing_generator *tg,
 	bool use_vbios)
 {
 	if (use_vbios)
-			dce110_timing_generator_program_timing_generator(tg, timing);
-		else
-			dce120_timing_generator_program_blanking(tg, timing);
+		dce110_timing_generator_program_timing_generator(tg, timing);
+	else
+		dce120_timing_generator_program_blanking(tg, timing);
 }
 
 bool dce120_tg_is_blanked(struct timing_generator *tg)
-- 
2.12.0

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[PATCH 3/6] drm/amd/display: Make dce120_tg_is_blanked() more legible

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 .../drm/amd/display/dc/dce120/dce120_timing_generator.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 05079662265d..017a025b527b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -746,15 +746,14 @@ bool dce120_tg_is_blanked(struct timing_generator *tg)
 			mmCRTC0_CRTC_BLANK_CONTROL,
 			tg110->offsets.crtc);
 
-	if (
-		get_reg_field_value(
-			value,
-			CRTC0_CRTC_BLANK_CONTROL,
-			CRTC_BLANK_DATA_EN) == 1	&&
-		get_reg_field_value(
-			value,
-			CRTC0_CRTC_BLANK_CONTROL,
-			CRTC_CURRENT_BLANK_STATE) == 1)
+	if (get_reg_field_value(
+		value,
+		CRTC0_CRTC_BLANK_CONTROL,
+		CRTC_BLANK_DATA_EN) == 1 &&
+	    get_reg_field_value(
+		value,
+		CRTC0_CRTC_BLANK_CONTROL,
+		CRTC_CURRENT_BLANK_STATE) == 1)
 			return true;
 
 	return false;
-- 
2.12.0

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[PATCH 4/6] drm/amd/display: Clean up indentation in dce120_tg_set_blank()

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 .../drm/amd/display/dc/dce120/dce120_timing_generator.c  | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 017a025b527b..b66dcfc3ecfb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -768,17 +768,11 @@ void dce120_tg_set_blank(struct timing_generator *tg,
 		CRTC0_CRTC_DOUBLE_BUFFER_CONTROL,
 		CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
 
-	if (enable_blanking) {
-		CRTC_REG_SET(
-			CRTC0_CRTC_BLANK_CONTROL,
-			CRTC_BLANK_DATA_EN, 1);
-
-	} else
-		dm_write_reg_soc15(
-			tg->ctx,
-			mmCRTC0_CRTC_BLANK_CONTROL,
-			tg110->offsets.crtc,
-			0);
+	if (enable_blanking)
+		CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
+	else
+		dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
+			tg110->offsets.crtc, 0);
 }
 
 bool dce120_tg_validate_timing(struct timing_generator *tg,
-- 
2.12.0

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[PATCH 5/6] drm/amd/display: Tidy up dce120_clock_source_create()

[Tom St Denis]

Also change sizeof to be automatic based on type declaration.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index b6bdd1d52922..be9266b9be7f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -444,13 +444,13 @@ struct clock_source *dce120_clock_source_create(
 	bool dp_clk_src)
 {
 	struct dce110_clk_src *clk_src =
-		dm_alloc(sizeof(struct dce110_clk_src));
+		dm_alloc(sizeof(*clk_src));
 
 	if (!clk_src)
 		return NULL;
 
 	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-			regs, &cs_shift, &cs_mask)) {
+				     regs, &cs_shift, &cs_mask)) {
 		clk_src->base.dp_clk_src = dp_clk_src;
 		return &clk_src->base;
 	}
-- 
2.12.0

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[PATCH 6/6] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 .../drm/amd/display/dc/dce120/dce120_mem_input.c   | 27 ++++++++--------------
 1 file changed, 9 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
index c0677211bd93..5a7edfd8fbf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
@@ -195,20 +195,12 @@ static bool mem_input_program_surface_flip_and_addr(
 	 * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
 	 * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
 	 */
-	DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
-			GRPH_UPDATE_LOCK, 1);
-
-	if (flip_immediate) {
-		DCP_REG_UPDATE_2(
-			DCP0_GRPH_FLIP_CONTROL,
-			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
-			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
-	} else {
-		DCP_REG_UPDATE_2(
-			DCP0_GRPH_FLIP_CONTROL,
-			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
-			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
-	}
+	DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
+
+	DCP_REG_UPDATE_2(
+		DCP0_GRPH_FLIP_CONTROL,
+		GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
+		GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ? 1 : 0);
 
 	switch (address->type) {
 	case PLN_ADDR_TYPE_GRAPHICS:
@@ -217,8 +209,8 @@ static bool mem_input_program_surface_flip_and_addr(
 		program_pri_addr(mem_input110, address->grph.addr);
 		break;
 	case PLN_ADDR_TYPE_GRPH_STEREO:
-		if (address->grph_stereo.left_addr.quad_part == 0
-			|| address->grph_stereo.right_addr.quad_part == 0)
+		if (address->grph_stereo.left_addr.quad_part == 0 ||
+		    address->grph_stereo.right_addr.quad_part == 0)
 			break;
 		program_pri_addr(mem_input110, address->grph_stereo.left_addr);
 		program_sec_addr(mem_input110, address->grph_stereo.right_addr);
@@ -234,8 +226,7 @@ static bool mem_input_program_surface_flip_and_addr(
 	if (flip_immediate)
 		mem_input->current_address = *address;
 
-	DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
-			GRPH_UPDATE_LOCK, 0);
+	DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 
 	return true;
 }
-- 
2.12.0

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RE: [PATCH 6/6] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, May 16, 2017 10:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 6/6] drm/amd/display: Tidy up
> mem_input_program_surface_flip_and_addr()
> 
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>

Patches are Acked-by: Alex Deucher <alexander.deucher@amd.com>

If Harry is ok with them, please coordinate to pull them through the dal tree.

Alex

> ---
>  .../drm/amd/display/dc/dce120/dce120_mem_input.c   | 27 ++++++++-------
> -------
>  1 file changed, 9 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> index c0677211bd93..5a7edfd8fbf7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> @@ -195,20 +195,12 @@ static bool
> mem_input_program_surface_flip_and_addr(
>  	 * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
>  	 * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
>  	 */
> -	DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
> -			GRPH_UPDATE_LOCK, 1);
> -
> -	if (flip_immediate) {
> -		DCP_REG_UPDATE_2(
> -			DCP0_GRPH_FLIP_CONTROL,
> -			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
> -			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
> -	} else {
> -		DCP_REG_UPDATE_2(
> -			DCP0_GRPH_FLIP_CONTROL,
> -			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
> -			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
> -	}
> +	DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
> +
> +	DCP_REG_UPDATE_2(
> +		DCP0_GRPH_FLIP_CONTROL,
> +		GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
> +		GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ?
> 1 : 0);
> 
>  	switch (address->type) {
>  	case PLN_ADDR_TYPE_GRAPHICS:
> @@ -217,8 +209,8 @@ static bool
> mem_input_program_surface_flip_and_addr(
>  		program_pri_addr(mem_input110, address->grph.addr);
>  		break;
>  	case PLN_ADDR_TYPE_GRPH_STEREO:
> -		if (address->grph_stereo.left_addr.quad_part == 0
> -			|| address->grph_stereo.right_addr.quad_part == 0)
> +		if (address->grph_stereo.left_addr.quad_part == 0 ||
> +		    address->grph_stereo.right_addr.quad_part == 0)
>  			break;
>  		program_pri_addr(mem_input110, address-
> >grph_stereo.left_addr);
>  		program_sec_addr(mem_input110, address-
> >grph_stereo.right_addr);
> @@ -234,8 +226,7 @@ static bool
> mem_input_program_surface_flip_and_addr(
>  	if (flip_immediate)
>  		mem_input->current_address = *address;
> 
> -	DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
> -			GRPH_UPDATE_LOCK, 0);
> +	DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
> 
>  	return true;
>  }
> --
> 2.12.0
> 
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Re: [PATCH 6/6] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()

[Harry Wentland]

On 2017-05-23 11:17 AM, Deucher, Alexander wrote:
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>> Of Tom St Denis
>> Sent: Tuesday, May 16, 2017 10:22 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: StDenis, Tom
>> Subject: [PATCH 6/6] drm/amd/display: Tidy up
>> mem_input_program_surface_flip_and_addr()
>>
>> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
> 
> Patches are Acked-by: Alex Deucher <alexander.deucher@amd.com>
> 
> If Harry is ok with them, please coordinate to pull them through the dal tree.
> 

Thanks, Alex.

Already part of the internal dal tree and on the way for amd-staging-4.9 
as part of today's set of DC patches.

Harry


> Alex
> 
>> ---
>>   .../drm/amd/display/dc/dce120/dce120_mem_input.c   | 27 ++++++++-------
>> -------
>>   1 file changed, 9 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>> b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>> index c0677211bd93..5a7edfd8fbf7 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>> @@ -195,20 +195,12 @@ static bool
>> mem_input_program_surface_flip_and_addr(
>>   	 * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
>>   	 * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
>>   	 */
>> -	DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
>> -			GRPH_UPDATE_LOCK, 1);
>> -
>> -	if (flip_immediate) {
>> -		DCP_REG_UPDATE_2(
>> -			DCP0_GRPH_FLIP_CONTROL,
>> -			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
>> -			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
>> -	} else {
>> -		DCP_REG_UPDATE_2(
>> -			DCP0_GRPH_FLIP_CONTROL,
>> -			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
>> -			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
>> -	}
>> +	DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
>> +
>> +	DCP_REG_UPDATE_2(
>> +		DCP0_GRPH_FLIP_CONTROL,
>> +		GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
>> +		GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ?
>> 1 : 0);
>>
>>   	switch (address->type) {
>>   	case PLN_ADDR_TYPE_GRAPHICS:
>> @@ -217,8 +209,8 @@ static bool
>> mem_input_program_surface_flip_and_addr(
>>   		program_pri_addr(mem_input110, address->grph.addr);
>>   		break;
>>   	case PLN_ADDR_TYPE_GRPH_STEREO:
>> -		if (address->grph_stereo.left_addr.quad_part == 0
>> -			|| address->grph_stereo.right_addr.quad_part == 0)
>> +		if (address->grph_stereo.left_addr.quad_part == 0 ||
>> +		    address->grph_stereo.right_addr.quad_part == 0)
>>   			break;
>>   		program_pri_addr(mem_input110, address-
>>> grph_stereo.left_addr);
>>   		program_sec_addr(mem_input110, address-
>>> grph_stereo.right_addr);
>> @@ -234,8 +226,7 @@ static bool
>> mem_input_program_surface_flip_and_addr(
>>   	if (flip_immediate)
>>   		mem_input->current_address = *address;
>>
>> -	DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
>> -			GRPH_UPDATE_LOCK, 0);
>> +	DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
>>
>>   	return true;
>>   }
>> --
>> 2.12.0
>>
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>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
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> 
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