[U-Boot] [PATCH 01/14] armv7: Add workaround for USB erratum A-009008

[U-Boot] [PATCH 01/14] armv7: Add workaround for USB erratum A-009008

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB High Speed (HS) EYE Height Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/Kconfig                |  2 ++
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 12 ++++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 ++++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index b61f3cd..df539e9 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -14,6 +14,8 @@ config ARCH_LS1021A
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
+	select SYS_FSL_ERRATUM_A009008
+	select SYS_FSL_ERRATUM_A009942
 
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..c54daee 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
 	return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+	val &= ~(0xF << 6);
+	out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 void s_init(void)
 {
 }
@@ -146,6 +156,8 @@ int arch_soc_init(void)
 	 */
 	out_be32(&scfg->eddrtqcfg, 0x63b20042);
 
+	/* Erratum */
+	erratum_a009008();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..f474cfd 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -172,6 +172,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG0	0x00080000
 #define SCFG_PMCINTECR_ETSECERRG1	0x00040000
 #define SCFG_CLUSTERPMCR_WFIL2EN	0x80000000
+#define SCFG_BASE                       0x01570000
+#define SCFG_USB3PRM1CR                 0x070
+#define USB_TXVREFTUNE                  0x9
+
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH] uboot: Kconfig: add ERRATUM config to Kconfig for solve compile issue.

[yinbo.zhu]

add erratum config to Kconfig and instead of config.h's config
for solve ls2080rdb compiling issue

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 24523eb..27c90fc 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,7 @@
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
 
 #define DCFG_DCSR_BASE		0X700100000ULL
+#define DCSR_BASE              0x700000000ULL
 #define DCSR_USB_PHY1                  0x4600000
 #define DCSR_USB_PHY2                  0x4610000
 #define DCSR_USB_PHY_RX_OVRD_IN_HI     0x1006
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 02/14] armv7: Add workaround for USB erratum A-009798

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB High Speed Squelch Threshold Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/Kconfig                |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index df539e9..32a48d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -16,6 +16,7 @@ config ARCH_LS1021A
 	select SYS_FSL_SEC_LE
 	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_ERRATUM_A009942
+	select SYS_FSL_ERRATUM_A009798
 
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index c54daee..2e64708 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+	out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
 	/* Erratum */
 	erratum_a009008();
+	erratum_a009798();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f474cfd..bfc92ee 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -175,6 +175,7 @@ struct ccsr_gur {
 #define SCFG_BASE                       0x01570000
 #define SCFG_USB3PRM1CR                 0x070
 #define USB_TXVREFTUNE                  0x9
+#define USB_SQRXTUNE                    0xFC7FFFFF
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 03/14] armv7: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/Kconfig                |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 16 ++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +++++++++
 3 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 32a48d5..92afe09 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -17,6 +17,7 @@ config ARCH_LS1021A
 	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
 
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 2e64708..19eb361 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+	u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+	writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_TX_OVRD_DRV_LO);
+	writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_MPLL_OVRD_IN_HI);
+	writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_LEVEL_OVRD_IN);
+	writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
 	/* Erratum */
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index bfc92ee..5f05e0d 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR                 0x070
 #define USB_TXVREFTUNE                  0x9
 #define USB_SQRXTUNE                    0xFC7FFFFF
+#define USB_PHY_BASE                    0x08510000
+#define USB_PHY_TX_OVRD_DRV_LO          0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI         0x0024
+#define USB_PHY_LEVEL_OVRD_IN           0x002a
+#define USB_PHY_TX_OVRD_IN_HI           0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL      0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL     0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL       0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL       0x0003
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 04/14] armv7: Add workaround for USB erratum A-009007

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3PHY Observing Intermittent Failure in Rx
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/Kconfig                |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 12 ++++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +++++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 92afe09..926903b 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -18,6 +18,7 @@ config ARCH_LS1021A
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
 
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 19eb361..4754907 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+	u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
 	erratum_a009008();
 	erratum_a009798();
 	erratum_a008997();
+	erratum_a009007();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 5f05e0d..fc406f7 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -181,10 +181,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI         0x0024
 #define USB_PHY_LEVEL_OVRD_IN           0x002a
 #define USB_PHY_TX_OVRD_IN_HI           0x2002
+#define USB_PHY_RX_OVRD_IN_HI           0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL      0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL     0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL       0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL       0x0003
+#define USB_PHY_RX_EQ_VAL_1             0x0000
+#define USB_PHY_RX_EQ_VAL_2             0x8000
+#define USB_PHY_RX_EQ_VAL_3             0x8004
+#define USB_PHY_RX_EQ_VAL_4             0x800C
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 05/14] armv8: Add workaround for USB erratum A-009798

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB High Speed Squelch Threshold Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  5 +++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 22 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  5 +++++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 4b87dd2..aff66fb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1012A
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
 	select SYS_FSL_ERRATUM_A010315
+	select SYS_FSL_ERRATUM_A009798
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_HAS_CCI400
@@ -18,6 +19,7 @@ config ARCH_LS1043A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A009660
+	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009929
 	select SYS_FSL_ERRATUM_A009942
@@ -44,6 +46,7 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
 	select SYS_FSL_ERRATUM_A010539
+	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SRDS_2
 	select ARCH_EARLY_INIT_R
@@ -71,6 +74,7 @@ config ARCH_LS1088A
 	select SYS_FSL_ERRATUM_A010165
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A009798
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_EC1
@@ -101,6 +105,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A008514
 	select SYS_FSL_ERRATUM_A008585
 	select SYS_FSL_ERRATUM_A009635
+	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1544eaa..8d0f1b8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -28,6 +28,25 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -200,6 +219,8 @@ void fsl_lsch3_early_init_f(void)
 #endif
 	erratum_a008514();
 	erratum_a008336();
+	erratum_a009008();
+	erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -471,6 +492,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009929();
 	erratum_a009660();
 	erratum_a010539();
+	erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5210b8c..5763586 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,6 +198,11 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_USB3PRM1CR_USB2           0x07C
+#define SCFG_USB3PRM1CR_USB3           0x088
+#define USB_TXVREFTUNE                 0x9
+#define USB_SQRXTUNE                   0xFC7FFFFF
+
 	u32     devdisr2;       /* Device disable control 2 */
 	u32     devdisr3;       /* Device disable control 3 */
 	u32     devdisr4;       /* Device disable control 4 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f5e8adb..5e458ae 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -140,6 +140,8 @@
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
+#define USB_TXVREFTUNE                 0x9
+#define USB_SQRXTUNE                   0xFC7FFFFF
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 06/14] armv8: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 29 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 42 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index aff66fb..a884ad2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1012A
 	select SYS_FSL_MMDC
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_HAS_CCI400
@@ -18,6 +19,7 @@ config ARCH_LS1043A
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009660
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009663
@@ -41,6 +43,7 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A008336
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
@@ -72,6 +75,7 @@ config ARCH_LS1088A
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A009798
@@ -106,6 +110,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A008585
 	select SYS_FSL_ERRATUM_A009635
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
@@ -121,6 +126,7 @@ config FSL_LSCH2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_BE
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 
@@ -128,6 +134,7 @@ config FSL_LSCH3
 	bool
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
+	select SYS_FSL_ERRATUM_A008997
 
 config FSL_MC_ENET
 	bool "Management Complex network"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d0f1b8..2b9eb54 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -47,6 +47,33 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -221,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a008336();
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -493,6 +521,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009660();
 	erratum_a010539();
 	erratum_a009798();
+	erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5763586..554def5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,8 +198,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_BASE                      0x01570000
+#define SCFG_USB3PRM1CR_USB1           0x070
+#define SCFG_USB3PRM2CR_USB1           0x074
 #define SCFG_USB3PRM1CR_USB2           0x07C
 #define SCFG_USB3PRM1CR_USB3           0x088
+#define SCFG_USB3PRM2CR_USB3           0x08c
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 5e458ae..c7c53b9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,9 +139,11 @@
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
+#define SCFG_USB3PRM2CR                 0x004
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
+#define USB_PCSTXSWINGFULL             0x47
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 07/14] armv8: Add workaround for USB erratum A-009007

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3PHY Observing Intermittent Failure in Rx
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 43 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 12 ++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  7 ++++
 4 files changed, 69 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a884ad2..6ba53a8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1012A
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_HAS_CCI400
@@ -27,6 +28,7 @@ config ARCH_LS1043A
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A010539
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
 	select ARCH_EARLY_INIT_R
@@ -50,6 +52,7 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A010165
 	select SYS_FSL_ERRATUM_A010539
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SRDS_2
 	select ARCH_EARLY_INIT_R
@@ -76,6 +79,7 @@ config ARCH_LS1088A
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
 	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A009798
@@ -108,6 +112,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008514
 	select SYS_FSL_ERRATUM_A008585
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_ERRATUM_A009635
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A008997
@@ -127,6 +132,7 @@ config FSL_LSCH2
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 
@@ -135,6 +141,7 @@ config FSL_LSCH3
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
 
 config FSL_MC_ENET
 	bool "Management Complex network"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2b9eb54..1597444 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -74,6 +74,47 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+	u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	usb_phy = (u32 __iomem *)USB_PHY2;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	usb_phy = (u32 __iomem *)USB_PHY3;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+	u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE;
+	writew(USB_PHY_RX_EQ_VAL_1,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_1,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -249,6 +290,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a009008();
 	erratum_a009798();
 	erratum_a008997();
+	erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -522,6 +564,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a010539();
 	erratum_a009798();
 	erratum_a008997();
+	erratum_a009007();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 554def5..2634195 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -206,6 +206,18 @@ struct ccsr_gur {
 #define SCFG_USB3PRM2CR_USB3           0x08c
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
+#define USB_PCSTXSWINGFULL             0x47
+#define USB_PHY1                       0x084F0000
+#define USB_PHY2                       0x08500000
+#define USB_PHY3                       0x08510000
+#define USB_PHY_RX_OVRD_IN_HI          0x200c
+/* TODO : make it generic */
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x8000
+#define USB_PHY_RX_EQ_VAL_3            0x8003
+
+#define USB_PHY_RX_EQ_VAL_4            0x800b
+
 
 	u32     devdisr2;       /* Device disable control 2 */
 	u32     devdisr3;       /* Device disable control 3 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index c7c53b9..79857f4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,13 @@
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
 
 #define DCFG_DCSR_BASE		0X700100000ULL
+#define DCSR_USB_PHY1                  0x4600000
+#define DCSR_USB_PHY2                  0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI     0x1006
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x0080
+#define USB_PHY_RX_EQ_VAL_3            0x0380
+#define USB_PHY_RX_EQ_VAL_4            0x0b80
 #define DCFG_DCSR_PORCR1		0x000
 
 /* Interrupt Sampling Control */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 08/14] usb: dwc3: Add helper functions to enable snooping and burst settings

[yinbo.zhu]

From: Rajat Srivastava <rajat.srivastava@nxp.com>

Adds helper functions to enable snooping and outstanding burst beat
settings.

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
 drivers/usb/dwc3/core.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h |  7 +++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 85cc96a..4ac599a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
 
 #define DWC3_ALIGN_MASK		(16 - 1)
 
+void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
+				 int breq_limit)
+{
+	struct dwc3 *dwc;
+	u32 reg;
+
+	list_for_each_entry(dwc, &dwc3_list, list) {
+		if (dwc->index != index)
+			continue;
+
+		/*
+		 * Change burst beat and outstanding pipelined
+		 * transfers requests
+		 */
+		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+		reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
+		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+
+		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
+		reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
+		dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
+		break;
+	}
+}
+
+void dwc3_core_set_snooping(int index, bool snoop)
+{
+	struct dwc3 *dwc;
+	u32 reg;
+
+	list_for_each_entry(dwc, &dwc3_list, list) {
+		if (dwc->index != index)
+			continue;
+
+		/* Enable/Disable snooping */
+		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+		if (snoop)
+			reg |= DWC3_SNOOP_ENABLE;
+		else
+			reg &= ~DWC3_SNOOP_ENABLE;
+		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+		break;
+	}
+}
+
 /**
  * dwc3_uboot_init - dwc3 core uboot initialization code
  * @dwc3_dev: struct dwc3_device containing initialization data
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 72d2fcd..455e7fa 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -593,6 +593,13 @@ struct dwc3_hwparams {
 /* HWPARAMS7 */
 #define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)
 
+/* GSBUSCFG0 */
+#define DWC3_SNOOP_ENABLE	(0x22220000)
+#define DWC3_INCR_BTYPE_MASK	(0xff)
+
+/* GSBUSCFG1 */
+#define DWC3_BREQ_LIMIT_MASK	(0xf00)
+
 struct dwc3_request {
 	struct usb_request	request;
 	struct list_head	list;
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 09/14] usb: ums: support multiple controllers using controller_index

[yinbo.zhu]

From: Rajesh Bhagat <rajesh.bhagat@nxp.com>

Adds a new field in fsg_common namely controller_index to support
multiple controllers usb gadget support.

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
---
 cmd/usb_mass_storage.c              |  2 +-
 drivers/usb/gadget/f_mass_storage.c | 11 +++++++++--
 include/usb_mass_storage.h          |  2 +-
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 86398fc..139b537 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
 	while (1) {
 		usb_gadget_handle_interrupts(controller_index);
 
-		rc = fsg_main_thread(NULL);
+		rc = fsg_main_thread(controller_index);
 		if (rc) {
 			/* Check I/O error */
 			if (rc == -EIO)
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..27ca5fe 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -362,6 +362,7 @@ struct fsg_common {
 	char inquiry_string[8 + 16 + 4 + 1];
 
 	struct kref		ref;
+	unsigned int controller_index;
 };
 
 struct fsg_config {
@@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
 			k = 0;
 		}
 
-		usb_gadget_handle_interrupts(0);
+		usb_gadget_handle_interrupts(common->controller_index);
 	}
 	common->thread_wakeup_needed = 0;
 	return rc;
@@ -2402,10 +2403,14 @@ static void handle_exception(struct fsg_common *common)
 
 /*-------------------------------------------------------------------------*/
 
-int fsg_main_thread(void *common_)
+int fsg_main_thread(unsigned int controller_index)
 {
 	int ret;
 	struct fsg_common	*common = the_fsg_common;
+
+	/* update the controller_index */
+	common->controller_index = controller_index;
+
 	/* The main loop */
 	do {
 		if (exception_in_progress(common)) {
@@ -2476,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
 
 	common->ops = NULL;
 	common->private_data = NULL;
+	common->controller_index = 0;
 
 	common->gadget = gadget;
 	common->ep0 = gadget->ep0;
@@ -2770,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
 
 	fsg_common->ops = NULL;
 	fsg_common->private_data = NULL;
+	fsg_common->controller_index = 0;
 
 	the_fsg_common = fsg_common;
 
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 8229f62..f21cc7a 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -28,6 +28,6 @@ struct ums {
 
 int fsg_init(struct ums *ums_devs, int count);
 void fsg_cleanup(void);
-int fsg_main_thread(void *);
+int fsg_main_thread(unsigned int);
 int fsg_add(struct usb_configuration *c);
 #endif /* __USB_MASS_STORAGE_H__ */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 10/14] config: ls1012aqds: Add USB EHCI support for ls1012aqds

[yinbo.zhu]

From: Rajesh Bhagat <rajesh.bhagat@nxp.com>

Add USB EHCI support for ls1012aqds platform

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
 include/configs/ls1012aqds.h                           | 2 ++
 include/usb/ehci-ci.h                                  | 2 +-
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2634195..9ac124f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
 #define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
 #define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_EHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x07600000)
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 5aaf3a7..ebc8d58 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -118,6 +118,8 @@
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 882aed4..ea3b580 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -159,7 +159,7 @@
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR	0
-#elif defined(CONFIG_LS102XA)
+#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 11/14] armv8: Add workaround for USB erratum A-009008

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB High Speed (HS) EYE Height Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 26 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 3 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6ba53a8..7619bcb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1012A
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009007
+	select SYS_FSL_ERRATUM_A009008
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_HAS_CCI400
@@ -29,6 +30,7 @@ config ARCH_LS1043A
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A010539
 	select SYS_FSL_ERRATUM_A009007
+	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
 	select ARCH_EARLY_INIT_R
@@ -53,6 +55,7 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A010539
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009007
+	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SRDS_2
 	select ARCH_EARLY_INIT_R
@@ -83,6 +86,7 @@ config ARCH_LS1088A
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A009008
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_EC1
@@ -122,6 +126,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
 	select SYS_FSL_ERRATUM_A009203
+	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_HAS_CCN504
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
@@ -133,6 +138,7 @@ config FSL_LSCH2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009007
+	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 
@@ -142,6 +148,7 @@ config FSL_LSCH3
 	select SYS_HAS_SERDES
 	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009007
+	select SYS_FSL_ERRATUM_A009008
 
 config FSL_MC_ENET
 	bool "Management Complex network"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1597444..6e536d1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -28,6 +28,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+
 static void erratum_a009798(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
@@ -288,6 +312,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a008514();
 	erratum_a008336();
 	erratum_a009008();
+	erratum_a009008();
 	erratum_a009798();
 	erratum_a008997();
 	erratum_a009007();
@@ -562,6 +587,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009929();
 	erratum_a009660();
 	erratum_a010539();
+	erratum_a009008();
 	erratum_a009798();
 	erratum_a008997();
 	erratum_a009007();
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 79857f4..24523eb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -149,6 +149,7 @@
 #define SCFG_USB3PRM2CR                 0x004
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
 #define USB_TXVREFTUNE                 0x9
+#define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
 #define USB_PCSTXSWINGFULL             0x47
 #define SCFG_QSPICLKCTLR	0x10
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 12/14] armv8/fsl-layerscape: add dwc3 gadget driver support

[yinbo.zhu]

From: Rajat Srivastava <rajat.srivastava@nxp.com>

Implements the dwc3 gadget driver support for LS1043
platform, and performs below operations:
1. Enables snooping support for DWC3 controller.
2. Enables cache coherency in LS1043 platform.

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 93 +++++++++++++++++++++-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  7 ++
 2 files changed, 99 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6e536d1..12b4278 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -25,6 +25,9 @@
 #include <fsl_validate.h>
 #endif
 #include <fsl_immap.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <linux/usb/xhci-fsl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -570,11 +573,19 @@ void fsl_lsch2_early_init_f(void)
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 	/* Make SEC reads and writes snoopable */
+#if defined(CONFIG_LS1043A)
+setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+SCFG_SNPCNFGCR_USB3WRSNP);
+#else
+/* Make SEC reads and writes snoopable */
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 		     SCFG_SNPCNFGCR_SECWRSNP |
 		     SCFG_SNPCNFGCR_SATARDSNP |
 		     SCFG_SNPCNFGCR_SATAWRSNP);
-
+#endif
 	/*
 	 * Enable snoop requests and DVM message requests for
 	 * Slave insterface S4 (A53 core cluster)
@@ -633,6 +644,86 @@ int qspi_ahb_init(void)
 }
 #endif
 
+#ifdef CONFIG_USB_DWC3
+
+#if defined(CONFIG_LS1043A)
+static struct dwc3_device dwc3_device_data0 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+static struct dwc3_device dwc3_device_data1 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 1,
+};
+
+static struct dwc3_device dwc3_device_data2 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(index);
+	return 0;
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	switch (init) {
+	case USB_INIT_DEVICE:
+		switch (index) {
+#if defined(CONFIG_LS1043A)
+		case 0:
+			dwc3_uboot_init(&dwc3_device_data0);
+			break;
+		case 1:
+			dwc3_uboot_init(&dwc3_device_data1);
+			break;
+		case 2:
+			dwc3_uboot_init(&dwc3_device_data2);
+			break;
+#endif
+		default:
+			printf("Invalid Controller Index\n");
+			return -1;
+		}
+#if defined(CONFIG_LS1043A)
+		dwc3_core_incr_burst_enable(index, 0xf, 0xf);
+		dwc3_core_set_snooping(index, true);
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	switch (init) {
+	case USB_INIT_DEVICE:
+#if defined(CONFIG_LS1043A)
+		dwc3_uboot_exit(index);
+#endif
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+#endif
+
+
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 9ac124f..5255cdd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -361,6 +361,13 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
+#define SCFG_SNPCNFGCR_USB1RDSNP       0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP       0x00100000
+#define SCFG_SNPCNFGCR_USB2RDSNP       0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP       0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP       0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP       0x00004000
+
 #define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
 
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 13/14] drivers:usb:xhci:fsl: Implement Erratum A-010151 for FSL USB3 controller

[yinbo.zhu]

From: Sriram Dash <sriram.dash@nxp.com>

Currently the controller by default enables the Receive Detect feature in P3
mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
detection in P3 mode.
Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
Detect feature is required.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 drivers/usb/host/xhci-dwc3.c | 5 +++++
 drivers/usb/host/xhci-fsl.c  | 7 +++++++
 include/linux/usb/dwc3.h     | 1 +
 3 files changed, 13 insertions(+)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 33961cd..adbd9b5 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -97,3 +97,8 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
 			GFLADJ_30MHZ(val));
 }
+
+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val)
+{
+	setbits_le32(&dwc3_reg->g_usb3pipectl[0], val);
+}
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 3a16624..e8e90fa 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -86,6 +86,13 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
 	fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
 
 	/*
+	* A-010151: USB controller to configure USB in P2 mode
+	* whenever the Receive Detect feature is required
+	*/
+	dwc3_set_rxdetect_power_mode(fsl_xhci->dwc3_reg,
+				     DWC3_GUSB3PIPECTL_DISRXDETP3);
+
+	/*
 	 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
 	 * reliably support Rx Detect in P3 mode(P3 is the default
 	 * setting). Therefore, some USB3.0 devices may not be detected
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index c1b23b2..873b4db 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -220,5 +220,6 @@ void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
 int dwc3_core_init(struct dwc3 *dwc3_reg);
 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val);
 #endif
 #endif /* __DWC3_H_ */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 14/14] uboot: Kconfig: add ERRATUM config to Kconfig for solve compile issue.

[yinbo.zhu]

add erratum config to Kconfig and instead of config.h's config
for solve ls2080rdb compiling issue

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 24523eb..27c90fc 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,7 @@
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
 
 #define DCFG_DCSR_BASE		0X700100000ULL
+#define DCSR_BASE              0x700000000ULL
 #define DCSR_USB_PHY1                  0x4600000
 #define DCSR_USB_PHY2                  0x4610000
 #define DCSR_USB_PHY_RX_OVRD_IN_HI     0x1006
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 13/14] drivers:usb:xhci:fsl: Implement Erratum A-010151 for FSL USB3 controller

[Tom Rini]

On Tue, May 16, 2017 at 08:16:33PM +0800, yinbo.zhu wrote:
> From: Sriram Dash <sriram.dash@nxp.com>
> 
> Currently the controller by default enables the Receive Detect feature in P3
> mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
> detection in P3 mode.
> Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
> Detect feature is required.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
> ---
>  drivers/usb/host/xhci-dwc3.c | 5 +++++
>  drivers/usb/host/xhci-fsl.c  | 7 +++++++
>  include/linux/usb/dwc3.h     | 1 +
>  3 files changed, 13 insertions(+)
> 
> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
> index 33961cd..adbd9b5 100644
> --- a/drivers/usb/host/xhci-dwc3.c
> +++ b/drivers/usb/host/xhci-dwc3.c
> @@ -97,3 +97,8 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
>  	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
>  			GFLADJ_30MHZ(val));
>  }
> +
> +void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val)
> +{
> +	setbits_le32(&dwc3_reg->g_usb3pipectl[0], val);
> +}
> diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
> index 3a16624..e8e90fa 100644
> --- a/drivers/usb/host/xhci-fsl.c
> +++ b/drivers/usb/host/xhci-fsl.c
> @@ -86,6 +86,13 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
>  	fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
>  
>  	/*
> +	* A-010151: USB controller to configure USB in P2 mode
> +	* whenever the Receive Detect feature is required
> +	*/
> +	dwc3_set_rxdetect_power_mode(fsl_xhci->dwc3_reg,
> +				     DWC3_GUSB3PIPECTL_DISRXDETP3);
> +
> +	/*
>  	 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
>  	 * reliably support Rx Detect in P3 mode(P3 is the default
>  	 * setting). Therefore, some USB3.0 devices may not be detected
> diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
> index c1b23b2..873b4db 100644
> --- a/include/linux/usb/dwc3.h
> +++ b/include/linux/usb/dwc3.h
> @@ -220,5 +220,6 @@ void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
>  void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
>  int dwc3_core_init(struct dwc3 *dwc3_reg);
>  void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
> +void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val);
>  #endif
>  #endif /* __DWC3_H_ */

Marek?

-- 
Tom
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[U-Boot] [PATCH 09/14] usb: ums: support multiple controllers using controller_index

[Tom Rini]

On Tue, May 16, 2017 at 08:16:29PM +0800, yinbo.zhu wrote:

> From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> 
> Adds a new field in fsg_common namely controller_index to support
> multiple controllers usb gadget support.
> 
> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
> ---
>  cmd/usb_mass_storage.c              |  2 +-
>  drivers/usb/gadget/f_mass_storage.c | 11 +++++++++--
>  include/usb_mass_storage.h          |  2 +-
>  3 files changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
> index 86398fc..139b537 100644
> --- a/cmd/usb_mass_storage.c
> +++ b/cmd/usb_mass_storage.c
> @@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
>  	while (1) {
>  		usb_gadget_handle_interrupts(controller_index);
>  
> -		rc = fsg_main_thread(NULL);
> +		rc = fsg_main_thread(controller_index);
>  		if (rc) {
>  			/* Check I/O error */
>  			if (rc == -EIO)
> diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
> index 1ecb92a..27ca5fe 100644
> --- a/drivers/usb/gadget/f_mass_storage.c
> +++ b/drivers/usb/gadget/f_mass_storage.c
> @@ -362,6 +362,7 @@ struct fsg_common {
>  	char inquiry_string[8 + 16 + 4 + 1];
>  
>  	struct kref		ref;
> +	unsigned int controller_index;
>  };
>  
>  struct fsg_config {
> @@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
>  			k = 0;
>  		}
>  
> -		usb_gadget_handle_interrupts(0);
> +		usb_gadget_handle_interrupts(common->controller_index);
>  	}
>  	common->thread_wakeup_needed = 0;
>  	return rc;
> @@ -2402,10 +2403,14 @@ static void handle_exception(struct fsg_common *common)
>  
>  /*-------------------------------------------------------------------------*/
>  
> -int fsg_main_thread(void *common_)
> +int fsg_main_thread(unsigned int controller_index)
>  {
>  	int ret;
>  	struct fsg_common	*common = the_fsg_common;
> +
> +	/* update the controller_index */
> +	common->controller_index = controller_index;
> +
>  	/* The main loop */
>  	do {
>  		if (exception_in_progress(common)) {
> @@ -2476,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
>  
>  	common->ops = NULL;
>  	common->private_data = NULL;
> +	common->controller_index = 0;
>  
>  	common->gadget = gadget;
>  	common->ep0 = gadget->ep0;
> @@ -2770,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
>  
>  	fsg_common->ops = NULL;
>  	fsg_common->private_data = NULL;
> +	fsg_common->controller_index = 0;
>  
>  	the_fsg_common = fsg_common;
>  
> diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
> index 8229f62..f21cc7a 100644
> --- a/include/usb_mass_storage.h
> +++ b/include/usb_mass_storage.h
> @@ -28,6 +28,6 @@ struct ums {
>  
>  int fsg_init(struct ums *ums_devs, int count);
>  void fsg_cleanup(void);
> -int fsg_main_thread(void *);
> +int fsg_main_thread(unsigned int);
>  int fsg_add(struct usb_configuration *c);
>  #endif /* __USB_MASS_STORAGE_H__ */

Lukasz?

-- 
Tom
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[U-Boot] [PATCH 08/14] usb: dwc3: Add helper functions to enable snooping and burst settings

[Tom Rini]

On Tue, May 16, 2017 at 08:16:28PM +0800, yinbo.zhu wrote:

> From: Rajat Srivastava <rajat.srivastava@nxp.com>
> 
> Adds helper functions to enable snooping and outstanding burst beat
> settings.
> 
> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> ---
>  drivers/usb/dwc3/core.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>  drivers/usb/dwc3/core.h |  7 +++++++
>  2 files changed, 52 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 85cc96a..4ac599a 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
>  
>  #define DWC3_ALIGN_MASK		(16 - 1)
>  
> +void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
> +				 int breq_limit)
> +{
> +	struct dwc3 *dwc;
> +	u32 reg;
> +
> +	list_for_each_entry(dwc, &dwc3_list, list) {
> +		if (dwc->index != index)
> +			continue;
> +
> +		/*
> +		 * Change burst beat and outstanding pipelined
> +		 * transfers requests
> +		 */
> +		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
> +		reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
> +		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
> +
> +		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
> +		reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
> +		dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
> +		break;
> +	}
> +}
> +
> +void dwc3_core_set_snooping(int index, bool snoop)
> +{
> +	struct dwc3 *dwc;
> +	u32 reg;
> +
> +	list_for_each_entry(dwc, &dwc3_list, list) {
> +		if (dwc->index != index)
> +			continue;
> +
> +		/* Enable/Disable snooping */
> +		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
> +		if (snoop)
> +			reg |= DWC3_SNOOP_ENABLE;
> +		else
> +			reg &= ~DWC3_SNOOP_ENABLE;
> +		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
> +		break;
> +	}
> +}
> +
>  /**
>   * dwc3_uboot_init - dwc3 core uboot initialization code
>   * @dwc3_dev: struct dwc3_device containing initialization data
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 72d2fcd..455e7fa 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -593,6 +593,13 @@ struct dwc3_hwparams {
>  /* HWPARAMS7 */
>  #define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)
>  
> +/* GSBUSCFG0 */
> +#define DWC3_SNOOP_ENABLE	(0x22220000)
> +#define DWC3_INCR_BTYPE_MASK	(0xff)
> +
> +/* GSBUSCFG1 */
> +#define DWC3_BREQ_LIMIT_MASK	(0xf00)
> +
>  struct dwc3_request {
>  	struct usb_request	request;
>  	struct list_head	list;

Marek?

-- 
Tom
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[U-Boot] [PATCH 01/14] armv7: Add workaround for USB erratum A-009008

[Tom Rini]

On Tue, May 16, 2017 at 08:16:20PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB High Speed (HS) EYE Height Adjustment
> This patch is adding the erratum for LS1021.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 02/14] armv7: Add workaround for USB erratum A-009798

[Tom Rini]

On Tue, May 16, 2017 at 08:16:22PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB High Speed Squelch Threshold Adjustment
> This patch is adding the erratum for LS1021.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 03/14] armv7: Add workaround for USB erratum A-008997

[Tom Rini]

On Tue, May 16, 2017 at 08:16:23PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
> This patch is adding the erratum for LS1021.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 04/14] armv7: Add workaround for USB erratum A-009007

[Tom Rini]

On Tue, May 16, 2017 at 08:16:24PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB3PHY Observing Intermittent Failure in Rx
> This patch is adding the erratum for LS1021.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 05/14] armv8: Add workaround for USB erratum A-009798

[Tom Rini]

On Tue, May 16, 2017 at 08:16:25PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB High Speed Squelch Threshold Adjustment
> This patch is adding the erratum for LS1043 and LS2080 SoCs.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 06/14] armv8: Add workaround for USB erratum A-008997

[Tom Rini]

On Tue, May 16, 2017 at 08:16:26PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
> This patch is adding the erratum for LS1043 and LS2080 SoCs.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 07/14] armv8: Add workaround for USB erratum A-009007

[Tom Rini]

On Tue, May 16, 2017 at 08:16:27PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB3PHY Observing Intermittent Failure in Rx
> This patch is adding the erratum for LS1043 and LS2080 SoCs.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 11/14] armv8: Add workaround for USB erratum A-009008

[Tom Rini]

On Tue, May 16, 2017 at 08:16:31PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB High Speed (HS) EYE Height Adjustment
> This patch is adding the erratum for LS1043 and LS2080 SoCs.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 12/14] armv8/fsl-layerscape: add dwc3 gadget driver support

[Tom Rini]

On Tue, May 16, 2017 at 08:16:32PM +0800, yinbo.zhu wrote:

> From: Rajat Srivastava <rajat.srivastava@nxp.com>
> 
> Implements the dwc3 gadget driver support for LS1043
> platform, and performs below operations:
> 1. Enables snooping support for DWC3 controller.
> 2. Enables cache coherency in LS1043 platform.
> 
> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
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[U-Boot] [PATCH 09/14] usb: ums: support multiple controllers using controller_index

[Lukasz Majewski]

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Hi Tom,

> On Tue, May 16, 2017 at 08:16:29PM +0800, yinbo.zhu wrote:
> 
> > From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> > 
> > Adds a new field in fsg_common namely controller_index to support
> > multiple controllers usb gadget support.
> > 
> > Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
> > Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> > Acked-by: Lukasz Majewski <l.majewski@samsung.com>

I've already acked this patch :-)

Best regards,
Łukasz

> > ---
> >  cmd/usb_mass_storage.c              |  2 +-
> >  drivers/usb/gadget/f_mass_storage.c | 11 +++++++++--
> >  include/usb_mass_storage.h          |  2 +-
> >  3 files changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
> > index 86398fc..139b537 100644
> > --- a/cmd/usb_mass_storage.c
> > +++ b/cmd/usb_mass_storage.c
> > @@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int
> > flag, while (1) {
> >  		usb_gadget_handle_interrupts(controller_index);
> >  
> > -		rc = fsg_main_thread(NULL);
> > +		rc = fsg_main_thread(controller_index);
> >  		if (rc) {
> >  			/* Check I/O error */
> >  			if (rc == -EIO)
> > diff --git a/drivers/usb/gadget/f_mass_storage.c
> > b/drivers/usb/gadget/f_mass_storage.c index 1ecb92a..27ca5fe 100644
> > --- a/drivers/usb/gadget/f_mass_storage.c
> > +++ b/drivers/usb/gadget/f_mass_storage.c
> > @@ -362,6 +362,7 @@ struct fsg_common {
> >  	char inquiry_string[8 + 16 + 4 + 1];
> >  
> >  	struct kref		ref;
> > +	unsigned int controller_index;
> >  };
> >  
> >  struct fsg_config {
> > @@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common
> > *common) k = 0;
> >  		}
> >  
> > -		usb_gadget_handle_interrupts(0);
> > +
> > usb_gadget_handle_interrupts(common->controller_index); }
> >  	common->thread_wakeup_needed = 0;
> >  	return rc;
> > @@ -2402,10 +2403,14 @@ static void handle_exception(struct
> > fsg_common *common) 
> >  /*-------------------------------------------------------------------------*/
> >  
> > -int fsg_main_thread(void *common_)
> > +int fsg_main_thread(unsigned int controller_index)
> >  {
> >  	int ret;
> >  	struct fsg_common	*common = the_fsg_common;
> > +
> > +	/* update the controller_index */
> > +	common->controller_index = controller_index;
> > +
> >  	/* The main loop */
> >  	do {
> >  		if (exception_in_progress(common)) {
> > @@ -2476,6 +2481,7 @@ static struct fsg_common
> > *fsg_common_init(struct fsg_common *common, 
> >  	common->ops = NULL;
> >  	common->private_data = NULL;
> > +	common->controller_index = 0;
> >  
> >  	common->gadget = gadget;
> >  	common->ep0 = gadget->ep0;
> > @@ -2770,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
> >  
> >  	fsg_common->ops = NULL;
> >  	fsg_common->private_data = NULL;
> > +	fsg_common->controller_index = 0;
> >  
> >  	the_fsg_common = fsg_common;
> >  
> > diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
> > index 8229f62..f21cc7a 100644
> > --- a/include/usb_mass_storage.h
> > +++ b/include/usb_mass_storage.h
> > @@ -28,6 +28,6 @@ struct ums {
> >  
> >  int fsg_init(struct ums *ums_devs, int count);
> >  void fsg_cleanup(void);
> > -int fsg_main_thread(void *);
> > +int fsg_main_thread(unsigned int);
> >  int fsg_add(struct usb_configuration *c);
> >  #endif /* __USB_MASS_STORAGE_H__ */
> 
> Lukasz?
> 




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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[U-Boot] [PATCH 09/14] usb: ums: support multiple controllers using controller_index

[Tom Rini]

On Tue, May 16, 2017 at 11:00:03PM +0200, Lukasz Majewski wrote:
> Hi Tom,
> 
> > On Tue, May 16, 2017 at 08:16:29PM +0800, yinbo.zhu wrote:
> > 
> > > From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> > > 
> > > Adds a new field in fsg_common namely controller_index to support
> > > multiple controllers usb gadget support.
> > > 
> > > Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
> > > Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> > > Acked-by: Lukasz Majewski <l.majewski@samsung.com>
> 
> I've already acked this patch :-)

D'oh, was just looking at the Cc list.

-- 
Tom
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[U-Boot] [PATCH 08/14] usb: dwc3: Add helper functions to enable snooping and burst settings

[Marek Vasut]

On 05/16/2017 09:32 PM, Tom Rini wrote:
> On Tue, May 16, 2017 at 08:16:28PM +0800, yinbo.zhu wrote:
> 
>> From: Rajat Srivastava <rajat.srivastava@nxp.com>
>>
>> Adds helper functions to enable snooping and outstanding burst beat
>> settings.
>>
>> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
>> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
>> ---
>>  drivers/usb/dwc3/core.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>>  drivers/usb/dwc3/core.h |  7 +++++++
>>  2 files changed, 52 insertions(+)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index 85cc96a..4ac599a 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
>>  
>>  #define DWC3_ALIGN_MASK		(16 - 1)
>>  
>> +void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
>> +				 int breq_limit)
>> +{
>> +	struct dwc3 *dwc;
>> +	u32 reg;
>> +
>> +	list_for_each_entry(dwc, &dwc3_list, list) {
>> +		if (dwc->index != index)
>> +			continue;
>> +
>> +		/*
>> +		 * Change burst beat and outstanding pipelined
>> +		 * transfers requests
>> +		 */
>> +		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
>> +		reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
>> +		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
>> +
>> +		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
>> +		reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
>> +		dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
>> +		break;
>> +	}
>> +}
>> +
>> +void dwc3_core_set_snooping(int index, bool snoop)
>> +{
>> +	struct dwc3 *dwc;
>> +	u32 reg;

So how do you discern which controller should have this value
increased/set and which shouldn't ? I believe that information
should come from DT ... hacking it up such that you change it
for all controllers doesn't scale.

>> +	list_for_each_entry(dwc, &dwc3_list, list) {
>> +		if (dwc->index != index)
>> +			continue;
>> +
>> +		/* Enable/Disable snooping */
>> +		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
>> +		if (snoop)
>> +			reg |= DWC3_SNOOP_ENABLE;
>> +		else
>> +			reg &= ~DWC3_SNOOP_ENABLE;
>> +		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
>> +		break;
>> +	}
>> +}
>> +
>>  /**
>>   * dwc3_uboot_init - dwc3 core uboot initialization code
>>   * @dwc3_dev: struct dwc3_device containing initialization data
>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>> index 72d2fcd..455e7fa 100644
>> --- a/drivers/usb/dwc3/core.h
>> +++ b/drivers/usb/dwc3/core.h
>> @@ -593,6 +593,13 @@ struct dwc3_hwparams {
>>  /* HWPARAMS7 */
>>  #define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)
>>  
>> +/* GSBUSCFG0 */
>> +#define DWC3_SNOOP_ENABLE	(0x22220000)
>> +#define DWC3_INCR_BTYPE_MASK	(0xff)
>> +
>> +/* GSBUSCFG1 */
>> +#define DWC3_BREQ_LIMIT_MASK	(0xf00)

Drop the parenthesis ...

>>  struct dwc3_request {
>>  	struct usb_request	request;
>>  	struct list_head	list;
> 
> Marek?
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 06/14] armv8: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 29 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 42 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index aff66fb..a884ad2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1012A
 	select SYS_FSL_MMDC
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_HAS_CCI400
@@ -18,6 +19,7 @@ config ARCH_LS1043A
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009660
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009663
@@ -41,6 +43,7 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A008336
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
@@ -72,6 +75,7 @@ config ARCH_LS1088A
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A009798
@@ -106,6 +110,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A008585
 	select SYS_FSL_ERRATUM_A009635
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
@@ -121,6 +126,7 @@ config FSL_LSCH2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_BE
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 
@@ -128,6 +134,7 @@ config FSL_LSCH3
 	bool
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
+	select SYS_FSL_ERRATUM_A008997
 
 config FSL_MC_ENET
 	bool "Management Complex network"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d0f1b8..2b9eb54 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -47,6 +47,33 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -221,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a008336();
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -493,6 +521,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009660();
 	erratum_a010539();
 	erratum_a009798();
+	erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5763586..554def5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,8 +198,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_BASE                      0x01570000
+#define SCFG_USB3PRM1CR_USB1           0x070
+#define SCFG_USB3PRM2CR_USB1           0x074
 #define SCFG_USB3PRM1CR_USB2           0x07C
 #define SCFG_USB3PRM1CR_USB3           0x088
+#define SCFG_USB3PRM2CR_USB3           0x08c
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 5e458ae..c7c53b9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,9 +139,11 @@
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
+#define SCFG_USB3PRM2CR                 0x004
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
+#define USB_PCSTXSWINGFULL             0x47
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 06/14] armv8: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 29 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 42 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index aff66fb..a884ad2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1012A
 	select SYS_FSL_MMDC
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_HAS_CCI400
@@ -18,6 +19,7 @@ config ARCH_LS1043A
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009660
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009663
@@ -41,6 +43,7 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A008336
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
@@ -72,6 +75,7 @@ config ARCH_LS1088A
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A009798
@@ -106,6 +110,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A008585
 	select SYS_FSL_ERRATUM_A009635
 	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
@@ -121,6 +126,7 @@ config FSL_LSCH2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_BE
+	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 
@@ -128,6 +134,7 @@ config FSL_LSCH3
 	bool
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
+	select SYS_FSL_ERRATUM_A008997
 
 config FSL_MC_ENET
 	bool "Management Complex network"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d0f1b8..2b9eb54 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -47,6 +47,33 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -221,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a008336();
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -493,6 +521,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009660();
 	erratum_a010539();
 	erratum_a009798();
+	erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5763586..554def5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,8 +198,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_BASE                      0x01570000
+#define SCFG_USB3PRM1CR_USB1           0x070
+#define SCFG_USB3PRM2CR_USB1           0x074
 #define SCFG_USB3PRM1CR_USB2           0x07C
 #define SCFG_USB3PRM1CR_USB3           0x088
+#define SCFG_USB3PRM2CR_USB3           0x08c
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 5e458ae..c7c53b9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,9 +139,11 @@
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
+#define SCFG_USB3PRM2CR                 0x004
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
+#define USB_PCSTXSWINGFULL             0x47
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 06/14] armv8: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 29 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 3 files changed, 35 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d0f1b8..2b9eb54 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -47,6 +47,33 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -221,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a008336();
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -493,6 +521,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009660();
 	erratum_a010539();
 	erratum_a009798();
+	erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5763586..554def5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,8 +198,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_BASE                      0x01570000
+#define SCFG_USB3PRM1CR_USB1           0x070
+#define SCFG_USB3PRM2CR_USB1           0x074
 #define SCFG_USB3PRM1CR_USB2           0x07C
 #define SCFG_USB3PRM1CR_USB3           0x088
+#define SCFG_USB3PRM2CR_USB3           0x08c
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index b5c25da..ea0226d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -133,9 +133,11 @@
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
+#define SCFG_USB3PRM2CR                 0x004
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
+#define USB_PCSTXSWINGFULL             0x47
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324