From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Kumar Gala <galak@codeaurora.org>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Gregory Clement <gregory.clement@free-electrons.com>,
linux-arm-kernel@lists.infradead.org,
Nadav Haklai <nadavh@marvell.com>,
Hanna Hawa <hannah@marvell.com>,
Yehuda Yitschak <yehuday@marvell.com>,
Antoine Tenart <antoine.tenart@free-electrons.com>
Subject: Re: [PATCH 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP
Date: Tue, 30 May 2017 16:54:54 +0200 [thread overview]
Message-ID: <20170530165454.6ca24dbc@free-electrons.com> (raw)
In-Reply-To: <2ea42715-700b-c363-eeba-db83b0f63a70@arm.com>
Hello,
On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
> > + for (i = 0; i < GICP_INT_COUNT; i++)
> > + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>
> What does this do on an edge interrupt?
I guess nothing. What the ICU does is:
* For level interrupts: when the interrupt wire is asserted, write to
SETNSR, when the interrupt wire is deasserted, write to CLRNSR
* For edge interrupts: only the interrupt assertion causes a write to
SETNSR.
> I bet this doesn't have any effect
Indeed. But do we care? Can an edge interrupt be left pending from the
firmware?
>, so you may want to use the irq_set_irqchip_state() API to clear a
> potential pending state instead (and you may want to wire it in the
> ICU driver itself as well).
I'm not sure how to use this irq_set_irqchip_state() API. I guess it
needs a virq that corresponds to the GIC SPI interrupt, and I'm not
sure how to get that.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Yehuda Yitschak <yehuday@marvell.com>,
Jason Cooper <jason@lakedaemon.net>,
Pawel Moll <pawel.moll@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Hanna Hawa <hannah@marvell.com>,
linux-kernel@vger.kernel.org, Nadav Haklai <nadavh@marvell.com>,
Rob Herring <robh+dt@kernel.org>, Andrew Lunn <andrew@lunn.ch>,
Kumar Gala <galak@codeaurora.org>,
Gregory Clement <gregory.clement@free-electrons.com>,
Thomas Gleixner <tglx@linutronix.de>,
Antoine Tenart <antoine.tenart@free-electrons.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP
Date: Tue, 30 May 2017 16:54:54 +0200 [thread overview]
Message-ID: <20170530165454.6ca24dbc@free-electrons.com> (raw)
In-Reply-To: <2ea42715-700b-c363-eeba-db83b0f63a70@arm.com>
Hello,
On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
> > + for (i = 0; i < GICP_INT_COUNT; i++)
> > + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>
> What does this do on an edge interrupt?
I guess nothing. What the ICU does is:
* For level interrupts: when the interrupt wire is asserted, write to
SETNSR, when the interrupt wire is deasserted, write to CLRNSR
* For edge interrupts: only the interrupt assertion causes a write to
SETNSR.
> I bet this doesn't have any effect
Indeed. But do we care? Can an edge interrupt be left pending from the
firmware?
>, so you may want to use the irq_set_irqchip_state() API to clear a
> potential pending state instead (and you may want to wire it in the
> ICU driver itself as well).
I'm not sure how to use this irq_set_irqchip_state() API. I guess it
needs a virq that corresponds to the GIC SPI interrupt, and I'm not
sure how to get that.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP
Date: Tue, 30 May 2017 16:54:54 +0200 [thread overview]
Message-ID: <20170530165454.6ca24dbc@free-electrons.com> (raw)
In-Reply-To: <2ea42715-700b-c363-eeba-db83b0f63a70@arm.com>
Hello,
On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
> > + for (i = 0; i < GICP_INT_COUNT; i++)
> > + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>
> What does this do on an edge interrupt?
I guess nothing. What the ICU does is:
* For level interrupts: when the interrupt wire is asserted, write to
SETNSR, when the interrupt wire is deasserted, write to CLRNSR
* For edge interrupts: only the interrupt assertion causes a write to
SETNSR.
> I bet this doesn't have any effect
Indeed. But do we care? Can an edge interrupt be left pending from the
firmware?
>, so you may want to use the irq_set_irqchip_state() API to clear a
> potential pending state instead (and you may want to wire it in the
> ICU driver itself as well).
I'm not sure how to use this irq_set_irqchip_state() API. I guess it
needs a virq that corresponds to the GIC SPI interrupt, and I'm not
sure how to get that.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
next prev parent reply other threads:[~2017-05-30 15:01 UTC|newest]
Thread overview: 107+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-30 9:16 [PATCH 0/6] Add support for the ICU unit in Marvell Armada 7K/8K Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 10:37 ` Marc Zyngier
2017-05-30 10:37 ` Marc Zyngier
2017-05-30 10:37 ` Marc Zyngier
2017-05-30 11:41 ` Thomas Petazzoni
2017-05-30 11:41 ` Thomas Petazzoni
2017-05-30 11:41 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 13:55 ` Marc Zyngier
2017-05-30 13:55 ` Marc Zyngier
2017-05-30 13:55 ` Marc Zyngier
2017-05-30 14:54 ` Thomas Petazzoni [this message]
2017-05-30 14:54 ` Thomas Petazzoni
2017-05-30 14:54 ` Thomas Petazzoni
2017-05-30 15:17 ` Marc Zyngier
2017-05-30 15:17 ` Marc Zyngier
2017-05-30 15:17 ` Marc Zyngier
2017-05-30 15:25 ` Thomas Petazzoni
2017-05-30 15:25 ` Thomas Petazzoni
2017-05-30 15:33 ` Marc Zyngier
2017-05-30 15:33 ` Marc Zyngier
2017-05-30 15:33 ` Marc Zyngier
2017-05-30 9:16 ` [PATCH 4/6] irqchip: irq-mvebu-icu: new driver for Marvell ICU Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 11:10 ` Marc Zyngier
2017-05-30 11:10 ` Marc Zyngier
2017-05-30 12:05 ` Thomas Petazzoni
2017-05-30 12:05 ` Thomas Petazzoni
2017-05-30 12:05 ` Thomas Petazzoni
2017-05-30 13:06 ` Marc Zyngier
2017-05-30 13:06 ` Marc Zyngier
2017-05-30 13:06 ` Marc Zyngier
2017-05-30 13:17 ` Thomas Petazzoni
2017-05-30 13:17 ` Thomas Petazzoni
2017-05-30 13:17 ` Thomas Petazzoni
2017-05-30 13:40 ` Marc Zyngier
2017-05-30 13:40 ` Marc Zyngier
2017-06-25 6:47 ` [EXT] " Yehuda Yitschak
2017-06-25 6:47 ` Yehuda Yitschak
2017-06-25 6:47 ` Yehuda Yitschak
2017-05-30 12:04 ` Antoine Tenart
2017-05-30 12:04 ` Antoine Tenart
2017-05-30 12:04 ` Antoine Tenart
2017-05-30 12:19 ` Russell King - ARM Linux
2017-05-30 12:19 ` Russell King - ARM Linux
2017-05-30 12:19 ` Russell King - ARM Linux
2017-05-30 12:33 ` Thomas Petazzoni
2017-05-30 12:33 ` Thomas Petazzoni
2017-05-30 12:33 ` Thomas Petazzoni
2017-05-30 12:56 ` Russell King - ARM Linux
2017-05-30 12:56 ` Russell King - ARM Linux
2017-05-30 12:56 ` Russell King - ARM Linux
2017-05-30 13:27 ` Andrew Lunn
2017-05-30 13:27 ` Andrew Lunn
2017-05-30 13:27 ` Andrew Lunn
2017-05-30 13:34 ` Thomas Petazzoni
2017-05-30 13:34 ` Thomas Petazzoni
2017-05-30 13:34 ` Thomas Petazzoni
2017-05-30 13:42 ` Russell King - ARM Linux
2017-05-30 13:42 ` Russell King - ARM Linux
2017-05-30 13:42 ` Russell King - ARM Linux
2017-05-30 14:03 ` Andrew Lunn
2017-05-30 14:03 ` Andrew Lunn
2017-05-30 14:03 ` Andrew Lunn
2017-05-30 14:36 ` Russell King - ARM Linux
2017-05-30 14:36 ` Russell King - ARM Linux
2017-05-30 14:36 ` Russell King - ARM Linux
2017-05-30 14:26 ` Thomas Petazzoni
2017-05-30 14:26 ` Thomas Petazzoni
2017-05-30 14:26 ` Thomas Petazzoni
2017-05-30 14:39 ` Russell King - ARM Linux
2017-05-30 14:39 ` Russell King - ARM Linux
2017-05-30 14:39 ` Russell King - ARM Linux
2017-05-30 14:49 ` Andrew Lunn
2017-05-30 14:49 ` Andrew Lunn
2017-05-30 14:49 ` Andrew Lunn
2017-05-30 15:08 ` Russell King - ARM Linux
2017-05-30 15:08 ` Russell King - ARM Linux
2017-05-30 13:28 ` Thomas Petazzoni
2017-05-30 13:28 ` Thomas Petazzoni
2017-05-30 13:28 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 5/6] arm64: marvell: enable ICU and GICP drivers Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 14:02 ` Marc Zyngier
2017-05-30 14:02 ` Marc Zyngier
2017-05-30 14:02 ` Marc Zyngier
2017-05-30 14:28 ` Thomas Petazzoni
2017-05-30 14:28 ` Thomas Petazzoni
2017-05-30 14:28 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU Thomas Petazzoni
2017-05-30 9:16 ` Thomas Petazzoni
2017-05-30 9:22 ` Thomas Petazzoni
2017-05-30 9:22 ` Thomas Petazzoni
2017-05-30 9:22 ` Thomas Petazzoni
2017-05-30 14:15 ` [PATCH 0/6] Add support for the ICU unit in Marvell Armada 7K/8K Marc Zyngier
2017-05-30 14:15 ` Marc Zyngier
2017-05-30 14:15 ` Marc Zyngier
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