[PATCH 0/3] use the Meson8b clock controller driver on Meson8 SoCs

[PATCH 0/3] use the Meson8b clock controller driver on Meson8 SoCs

[Martin Blumenstingl]

Based on the code from Amlogic's GPL kernel sources the clock controller
in the Meson8 (S802), Meson8b (S805) and Meson8m2 (S812) SoCs is very
similar.

a more detailed list of differences between the clock controller on each SoC
can be found in the description of the first patch.

This series adds new of_device_ids / compatibles for the Meson8 and Meson8m2
SoCs to the existing Meson8b clock controller driver (and updates the
documentation, Kconfig help and comments accordingly).
It also enables CONFIG_COMMON_CLK_MESON8B for MACH_MESON8.
Finally it adds the clock controller to meson8.dtsi and replaces the
static clk81 instance with the clk81 provided by the clock controller.

This is also the first preparation step for Meson8m2 SoC support by making
the clock controller available.
I am planning to post several follow-up series which will:
- add lots of missing devices to meson8.dtsi and meson8b.dtsi such as (but
  not limited to) PWM, USB controllers and PHYs, SAR ADC, HW random number
  generator and the SCU (Snoop Control Unit)
- add Meson8m2 SoC support
- once it's ready: the SDIO driver (allows connecting the SD card, SDIO wifi
  and eMMC flash)


Martin Blumenstingl (3):
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  arm: meson: select the clock controller for Meson8
  ARM: dts: meson8: add and use the real clock controller

 .../bindings/clock/amlogic,meson8b-clkc.txt        |  5 +++-
 arch/arm/boot/dts/meson8.dtsi                      | 32 +++++++++++-----------
 arch/arm/mach-meson/Kconfig                        |  1 +
 drivers/clk/meson/Kconfig                          |  6 ++--
 drivers/clk/meson/meson8b.c                        |  5 +++-
 5 files changed, 28 insertions(+), 21 deletions(-)

-- 
2.13.0

[PATCH 0/3] use the Meson8b clock controller driver on Meson8 SoCs

[Martin Blumenstingl]

Based on the code from Amlogic's GPL kernel sources the clock controller
in the Meson8 (S802), Meson8b (S805) and Meson8m2 (S812) SoCs is very
similar.

a more detailed list of differences between the clock controller on each SoC
can be found in the description of the first patch.

This series adds new of_device_ids / compatibles for the Meson8 and Meson8m2
SoCs to the existing Meson8b clock controller driver (and updates the
documentation, Kconfig help and comments accordingly).
It also enables CONFIG_COMMON_CLK_MESON8B for MACH_MESON8.
Finally it adds the clock controller to meson8.dtsi and replaces the
static clk81 instance with the clk81 provided by the clock controller.

This is also the first preparation step for Meson8m2 SoC support by making
the clock controller available.
I am planning to post several follow-up series which will:
- add lots of missing devices to meson8.dtsi and meson8b.dtsi such as (but
  not limited to) PWM, USB controllers and PHYs, SAR ADC, HW random number
  generator and the SCU (Snoop Control Unit)
- add Meson8m2 SoC support
- once it's ready: the SDIO driver (allows connecting the SD card, SDIO wifi
  and eMMC flash)


Martin Blumenstingl (3):
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  arm: meson: select the clock controller for Meson8
  ARM: dts: meson8: add and use the real clock controller

 .../bindings/clock/amlogic,meson8b-clkc.txt        |  5 +++-
 arch/arm/boot/dts/meson8.dtsi                      | 32 +++++++++++-----------
 arch/arm/mach-meson/Kconfig                        |  1 +
 drivers/clk/meson/Kconfig                          |  6 ++--
 drivers/clk/meson/meson8b.c                        |  5 +++-
 5 files changed, 28 insertions(+), 21 deletions(-)

-- 
2.13.0

[PATCH 0/3] use the Meson8b clock controller driver on Meson8 SoCs

[Martin Blumenstingl]

Based on the code from Amlogic's GPL kernel sources the clock controller
in the Meson8 (S802), Meson8b (S805) and Meson8m2 (S812) SoCs is very
similar.

a more detailed list of differences between the clock controller on each SoC
can be found in the description of the first patch.

This series adds new of_device_ids / compatibles for the Meson8 and Meson8m2
SoCs to the existing Meson8b clock controller driver (and updates the
documentation, Kconfig help and comments accordingly).
It also enables CONFIG_COMMON_CLK_MESON8B for MACH_MESON8.
Finally it adds the clock controller to meson8.dtsi and replaces the
static clk81 instance with the clk81 provided by the clock controller.

This is also the first preparation step for Meson8m2 SoC support by making
the clock controller available.
I am planning to post several follow-up series which will:
- add lots of missing devices to meson8.dtsi and meson8b.dtsi such as (but
  not limited to) PWM, USB controllers and PHYs, SAR ADC, HW random number
  generator and the SCU (Snoop Control Unit)
- add Meson8m2 SoC support
- once it's ready: the SDIO driver (allows connecting the SD card, SDIO wifi
  and eMMC flash)


Martin Blumenstingl (3):
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  arm: meson: select the clock controller for Meson8
  ARM: dts: meson8: add and use the real clock controller

 .../bindings/clock/amlogic,meson8b-clkc.txt        |  5 +++-
 arch/arm/boot/dts/meson8.dtsi                      | 32 +++++++++++-----------
 arch/arm/mach-meson/Kconfig                        |  1 +
 drivers/clk/meson/Kconfig                          |  6 ++--
 drivers/clk/meson/meson8b.c                        |  5 +++-
 5 files changed, 28 insertions(+), 21 deletions(-)

-- 
2.13.0

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Martin Blumenstingl]

The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++----
 drivers/clk/meson/Kconfig                                     |  6 +++---
 drivers/clk/meson/meson8b.c                                   |  5 ++++-
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 2b7b3fa588d7..606da38c0959 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -1,11 +1,14 @@
-* Amlogic Meson8b Clock and Reset Unit
+* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
 
-The Amlogic Meson8b clock controller generates and supplies clock to various
-controllers within the SoC.
+The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
+supplies clock to various controllers within the SoC.
 
 Required Properties:
 
-- compatible: should be "amlogic,meson8b-clkc"
+- compatible: must be one of:
+	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
+	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
+	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
 - reg: it must be composed by two tuples:
 	0) physical base address of the xtal register and length of memory
 	   mapped region.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 19480bcc7046..4a806203b73c 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	help
-	  Support for the clock controller on AmLogic S805 devices, aka
-	  meson8b. Say Y if you want peripherals and CPU frequency scaling to
-	  work.
+	  Support for the clock controller on AmLogic S802 (Meson8),
+	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
+	  want peripherals and CPU frequency scaling to work.
 
 config COMMON_CLK_GXBB
 	bool
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index bfd1690724de..94c55e79cdde 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1,5 +1,6 @@
 /*
- * AmLogic S805 / Meson8b Clock Controller Driver
+ * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
+ * Driver
  *
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
@@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id meson8b_clkc_match_table[] = {
+	{ .compatible = "amlogic,meson8-clkc" },
 	{ .compatible = "amlogic,meson8b-clkc" },
+	{ .compatible = "amlogic,meson8m2-clkc" },
 	{ }
 };
 
-- 
2.13.0

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Martin Blumenstingl]

The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++----
 drivers/clk/meson/Kconfig                                     |  6 +++---
 drivers/clk/meson/meson8b.c                                   |  5 ++++-
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 2b7b3fa588d7..606da38c0959 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -1,11 +1,14 @@
-* Amlogic Meson8b Clock and Reset Unit
+* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
 
-The Amlogic Meson8b clock controller generates and supplies clock to various
-controllers within the SoC.
+The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
+supplies clock to various controllers within the SoC.
 
 Required Properties:
 
-- compatible: should be "amlogic,meson8b-clkc"
+- compatible: must be one of:
+	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
+	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
+	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
 - reg: it must be composed by two tuples:
 	0) physical base address of the xtal register and length of memory
 	   mapped region.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 19480bcc7046..4a806203b73c 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	help
-	  Support for the clock controller on AmLogic S805 devices, aka
-	  meson8b. Say Y if you want peripherals and CPU frequency scaling to
-	  work.
+	  Support for the clock controller on AmLogic S802 (Meson8),
+	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
+	  want peripherals and CPU frequency scaling to work.
 
 config COMMON_CLK_GXBB
 	bool
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index bfd1690724de..94c55e79cdde 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1,5 +1,6 @@
 /*
- * AmLogic S805 / Meson8b Clock Controller Driver
+ * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
+ * Driver
  *
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
@@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id meson8b_clkc_match_table[] = {
+	{ .compatible = "amlogic,meson8-clkc" },
 	{ .compatible = "amlogic,meson8b-clkc" },
+	{ .compatible = "amlogic,meson8m2-clkc" },
 	{ }
 };
 
-- 
2.13.0

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Martin Blumenstingl]

The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++----
 drivers/clk/meson/Kconfig                                     |  6 +++---
 drivers/clk/meson/meson8b.c                                   |  5 ++++-
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 2b7b3fa588d7..606da38c0959 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -1,11 +1,14 @@
-* Amlogic Meson8b Clock and Reset Unit
+* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
 
-The Amlogic Meson8b clock controller generates and supplies clock to various
-controllers within the SoC.
+The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
+supplies clock to various controllers within the SoC.
 
 Required Properties:
 
-- compatible: should be "amlogic,meson8b-clkc"
+- compatible: must be one of:
+	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
+	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
+	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
 - reg: it must be composed by two tuples:
 	0) physical base address of the xtal register and length of memory
 	   mapped region.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 19480bcc7046..4a806203b73c 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	help
-	  Support for the clock controller on AmLogic S805 devices, aka
-	  meson8b. Say Y if you want peripherals and CPU frequency scaling to
-	  work.
+	  Support for the clock controller on AmLogic S802 (Meson8),
+	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
+	  want peripherals and CPU frequency scaling to work.
 
 config COMMON_CLK_GXBB
 	bool
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index bfd1690724de..94c55e79cdde 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1,5 +1,6 @@
 /*
- * AmLogic S805 / Meson8b Clock Controller Driver
+ * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
+ * Driver
  *
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
@@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id meson8b_clkc_match_table[] = {
+	{ .compatible = "amlogic,meson8-clkc" },
 	{ .compatible = "amlogic,meson8b-clkc" },
+	{ .compatible = "amlogic,meson8m2-clkc" },
 	{ }
 };
 
-- 
2.13.0

[PATCH 2/3] arm: meson: select the clock controller for Meson8

[Martin Blumenstingl]

Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
controller driver can also be used on Meson8 SoCs now that we have a
separate compatible for it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/mach-meson/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index b6e3acc63e14..ee30511849ca 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -21,6 +21,7 @@ config MACH_MESON8
 	bool "Amlogic Meson8 SoCs support"
 	default ARCH_MESON
 	select MESON6_TIMER
+	select COMMON_CLK_MESON8B
 
 config MACH_MESON8B
 	bool "Amlogic Meson8b SoCs support"
-- 
2.13.0

[PATCH 2/3] arm: meson: select the clock controller for Meson8

[Martin Blumenstingl]

Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
controller driver can also be used on Meson8 SoCs now that we have a
separate compatible for it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/mach-meson/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index b6e3acc63e14..ee30511849ca 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -21,6 +21,7 @@ config MACH_MESON8
 	bool "Amlogic Meson8 SoCs support"
 	default ARCH_MESON
 	select MESON6_TIMER
+	select COMMON_CLK_MESON8B
 
 config MACH_MESON8B
 	bool "Amlogic Meson8b SoCs support"
-- 
2.13.0

[PATCH 2/3] arm: meson: select the clock controller for Meson8

[Martin Blumenstingl]

Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
controller driver can also be used on Meson8 SoCs now that we have a
separate compatible for it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/mach-meson/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index b6e3acc63e14..ee30511849ca 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -21,6 +21,7 @@ config MACH_MESON8
 	bool "Amlogic Meson8 SoCs support"
 	default ARCH_MESON
 	select MESON6_TIMER
+	select COMMON_CLK_MESON8B
 
 config MACH_MESON8B
 	bool "Amlogic Meson8b SoCs support"
-- 
2.13.0

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Martin Blumenstingl]

This removes the dummy clk81 gate and replaces it with the actual clock
controller's CLKID_CLK81. This will also allow us to pass the real clock
IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6993077331c7..9b0b3ddbb17e 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -43,6 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 
@@ -82,13 +83,6 @@
 			reg = <0x203>;
 		};
 	};
-
-	clk81: clk@0 {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <141666666>;
-	};
-
 }; /* end of / */
 
 &aobus {
@@ -126,6 +120,12 @@
 };
 
 &cbus {
+	clkc: clock-controller@4000 {
+		#clock-cells = <1>;
+		compatible = "amlogic,meson8-clkc";
+		reg = <0x8000 0x4>, <0x4000 0x460>;
+	};
+
 	pinctrl_cbus: pinctrl@9880 {
 		compatible = "amlogic,meson8-cbus-pinctrl";
 		reg = <0x9880 0x10>;
@@ -172,20 +172,20 @@
 };
 
 &ethmac {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 	clock-names = "stmmaceth";
 };
 
 &i2c_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &L2 {
@@ -195,21 +195,21 @@
 };
 
 &spifc {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_C {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.0

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[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Martin Blumenstingl]

This removes the dummy clk81 gate and replaces it with the actual clock
controller's CLKID_CLK81. This will also allow us to pass the real clock
IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6993077331c7..9b0b3ddbb17e 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -43,6 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 
@@ -82,13 +83,6 @@
 			reg = <0x203>;
 		};
 	};
-
-	clk81: clk@0 {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <141666666>;
-	};
-
 }; /* end of / */
 
 &aobus {
@@ -126,6 +120,12 @@
 };
 
 &cbus {
+	clkc: clock-controller@4000 {
+		#clock-cells = <1>;
+		compatible = "amlogic,meson8-clkc";
+		reg = <0x8000 0x4>, <0x4000 0x460>;
+	};
+
 	pinctrl_cbus: pinctrl@9880 {
 		compatible = "amlogic,meson8-cbus-pinctrl";
 		reg = <0x9880 0x10>;
@@ -172,20 +172,20 @@
 };
 
 &ethmac {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 	clock-names = "stmmaceth";
 };
 
 &i2c_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &L2 {
@@ -195,21 +195,21 @@
 };
 
 &spifc {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_C {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.0

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Martin Blumenstingl]

This removes the dummy clk81 gate and replaces it with the actual clock
controller's CLKID_CLK81. This will also allow us to pass the real clock
IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6993077331c7..9b0b3ddbb17e 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -43,6 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 
@@ -82,13 +83,6 @@
 			reg = <0x203>;
 		};
 	};
-
-	clk81: clk at 0 {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <141666666>;
-	};
-
 }; /* end of / */
 
 &aobus {
@@ -126,6 +120,12 @@
 };
 
 &cbus {
+	clkc: clock-controller at 4000 {
+		#clock-cells = <1>;
+		compatible = "amlogic,meson8-clkc";
+		reg = <0x8000 0x4>, <0x4000 0x460>;
+	};
+
 	pinctrl_cbus: pinctrl at 9880 {
 		compatible = "amlogic,meson8-cbus-pinctrl";
 		reg = <0x9880 0x10>;
@@ -172,20 +172,20 @@
 };
 
 &ethmac {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 	clock-names = "stmmaceth";
 };
 
 &i2c_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &L2 {
@@ -195,21 +195,21 @@
 };
 
 &spifc {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_C {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.0

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Martin Blumenstingl]

This removes the dummy clk81 gate and replaces it with the actual clock
controller's CLKID_CLK81. This will also allow us to pass the real clock
IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6993077331c7..9b0b3ddbb17e 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -43,6 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 
@@ -82,13 +83,6 @@
 			reg = <0x203>;
 		};
 	};
-
-	clk81: clk at 0 {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <141666666>;
-	};
-
 }; /* end of / */
 
 &aobus {
@@ -126,6 +120,12 @@
 };
 
 &cbus {
+	clkc: clock-controller at 4000 {
+		#clock-cells = <1>;
+		compatible = "amlogic,meson8-clkc";
+		reg = <0x8000 0x4>, <0x4000 0x460>;
+	};
+
 	pinctrl_cbus: pinctrl at 9880 {
 		compatible = "amlogic,meson8-cbus-pinctrl";
 		reg = <0x9880 0x10>;
@@ -172,20 +172,20 @@
 };
 
 &ethmac {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 	clock-names = "stmmaceth";
 };
 
 &i2c_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &L2 {
@@ -195,21 +195,21 @@
 };
 
 &spifc {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_AO {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_A {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_B {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_C {
-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;
 };
-- 
2.13.0

Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> based on the code from the Amlogic GPL kernel sources. Add separate
> compatibles for each SoC to make sure that we can easily implement
> all the small differences for each SoC later on.
> 
> In general the Meson8 and Meson8m2 seem to be almost identical as they
> even share the same mach-meson8 directory in Amlogic's GPL kernel
> sources.
> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> because they are all using the same PLL values, 90% of the clock gates
> are the same (the actual diffstat of the mach-meson8/clock.c and
> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> all commented out code).
> The difference between the Meson8 and Meson8b clock gates seem to be:
> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>   of "PERIPHS_TOP" (on Meson8b)
> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>   kernel sources)
> None of these gates is added for now, since it's unclear whether these
> definitions are actually correct (the VCLK2_ENCT gate for example is
> defined, but only used in some commented block).
> 
> The main difference between all three SoCs seem to be the video (VPU)
> clocks. Apart from different supported clock rates (according to vpu.c
> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> (probably the same as on the Meson GX SoCs) to support glitch-free
> (clock rate) switching.
> None of these VPU clocks are not supported by our mainline meson8b
> clock driver yet though.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++---

I think you should split the binding documentation and clk changes into separate
patches.

> -
>  drivers/clk/meson/Kconfig                                     |  6 +++---
>  drivers/clk/meson/meson8b.c                                   |  5 ++++-

The change being more platform than clock related, I'd prefer if Kevin or Carlo
ack it before we apply it.

Apart from this, the change looks good to me. Nice to see people taking interest
 in these SoCs. Would you mind telling us a bit more about the board you have
used for this task and the tests you have done ? It would maybe allow other
people to help you.

Cheers
Jerome

>  3 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> index 2b7b3fa588d7..606da38c0959 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> @@ -1,11 +1,14 @@
> -* Amlogic Meson8b Clock and Reset Unit
> +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
>  
> -The Amlogic Meson8b clock controller generates and supplies clock to various
> -controllers within the SoC.
> +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
> +supplies clock to various controllers within the SoC.
>  
>  Required Properties:
>  
> -- compatible: should be "amlogic,meson8b-clkc"
> +- compatible: must be one of:
> +	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
> +	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
> +	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
>  - reg: it must be composed by two tuples:
>  	0) physical base address of the xtal register and length of memory
>  	   mapped region.
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 19480bcc7046..4a806203b73c 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
>  	bool
>  	depends on COMMON_CLK_AMLOGIC
>  	help
> -	  Support for the clock controller on AmLogic S805 devices, aka
> -	  meson8b. Say Y if you want peripherals and CPU frequency scaling to
> -	  work.
> +	  Support for the clock controller on AmLogic S802 (Meson8),
> +	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
> +	  want peripherals and CPU frequency scaling to work.
>  
>  config COMMON_CLK_GXBB
>  	bool
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index bfd1690724de..94c55e79cdde 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -1,5 +1,6 @@
>  /*
> - * AmLogic S805 / Meson8b Clock Controller Driver
> + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
> + * Driver
>   *
>   * Copyright (c) 2015 Endless Mobile, Inc.
>   * Author: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
> @@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
> *pdev)
>  }
>  
>  static const struct of_device_id meson8b_clkc_match_table[] = {
> +	{ .compatible = "amlogic,meson8-clkc" },
>  	{ .compatible = "amlogic,meson8b-clkc" },
> +	{ .compatible = "amlogic,meson8m2-clkc" },
>  	{ }
>  };
>  

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Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> based on the code from the Amlogic GPL kernel sources. Add separate
> compatibles for each SoC to make sure that we can easily implement
> all the small differences for each SoC later on.
> 
> In general the Meson8 and Meson8m2 seem to be almost identical as they
> even share the same mach-meson8 directory in Amlogic's GPL kernel
> sources.
> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> because they are all using the same PLL values, 90% of the clock gates
> are the same (the actual diffstat of the mach-meson8/clock.c and
> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> all commented out code).
> The difference between the Meson8 and Meson8b clock gates seem to be:
> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>   of "PERIPHS_TOP" (on Meson8b)
> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>   kernel sources)
> None of these gates is added for now, since it's unclear whether these
> definitions are actually correct (the VCLK2_ENCT gate for example is
> defined, but only used in some commented block).
> 
> The main difference between all three SoCs seem to be the video (VPU)
> clocks. Apart from different supported clock rates (according to vpu.c
> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> (probably the same as on the Meson GX SoCs) to support glitch-free
> (clock rate) switching.
> None of these VPU clocks are not supported by our mainline meson8b
> clock driver yet though.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++---

I think you should split the binding documentation and clk changes into separate
patches.

> -
>  drivers/clk/meson/Kconfig                                     |  6 +++---
>  drivers/clk/meson/meson8b.c                                   |  5 ++++-

The change being more platform than clock related, I'd prefer if Kevin or Carlo
ack it before we apply it.

Apart from this, the change looks good to me. Nice to see people taking interest
 in these SoCs. Would you mind telling us a bit more about the board you have
used for this task and the tests you have done ? It would maybe allow other
people to help you.

Cheers
Jerome

>  3 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> index 2b7b3fa588d7..606da38c0959 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> @@ -1,11 +1,14 @@
> -* Amlogic Meson8b Clock and Reset Unit
> +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
>  
> -The Amlogic Meson8b clock controller generates and supplies clock to various
> -controllers within the SoC.
> +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
> +supplies clock to various controllers within the SoC.
>  
>  Required Properties:
>  
> -- compatible: should be "amlogic,meson8b-clkc"
> +- compatible: must be one of:
> +	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
> +	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
> +	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
>  - reg: it must be composed by two tuples:
>  	0) physical base address of the xtal register and length of memory
>  	   mapped region.
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 19480bcc7046..4a806203b73c 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
>  	bool
>  	depends on COMMON_CLK_AMLOGIC
>  	help
> -	  Support for the clock controller on AmLogic S805 devices, aka
> -	  meson8b. Say Y if you want peripherals and CPU frequency scaling to
> -	  work.
> +	  Support for the clock controller on AmLogic S802 (Meson8),
> +	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
> +	  want peripherals and CPU frequency scaling to work.
>  
>  config COMMON_CLK_GXBB
>  	bool
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index bfd1690724de..94c55e79cdde 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -1,5 +1,6 @@
>  /*
> - * AmLogic S805 / Meson8b Clock Controller Driver
> + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
> + * Driver
>   *
>   * Copyright (c) 2015 Endless Mobile, Inc.
>   * Author: Carlo Caione <carlo@endlessm.com>
> @@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
> *pdev)
>  }
>  
>  static const struct of_device_id meson8b_clkc_match_table[] = {
> +	{ .compatible = "amlogic,meson8-clkc" },
>  	{ .compatible = "amlogic,meson8b-clkc" },
> +	{ .compatible = "amlogic,meson8m2-clkc" },
>  	{ }
>  };
>  

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> based on the code from the Amlogic GPL kernel sources. Add separate
> compatibles for each SoC to make sure that we can easily implement
> all the small differences for each SoC later on.
> 
> In general the Meson8 and Meson8m2 seem to be almost identical as they
> even share the same mach-meson8 directory in Amlogic's GPL kernel
> sources.
> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> because they are all using the same PLL values, 90% of the clock gates
> are the same (the actual diffstat of the mach-meson8/clock.c and
> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> all commented out code).
> The difference between the Meson8 and Meson8b clock gates seem to be:
> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
> ? of "PERIPHS_TOP" (on Meson8b)
> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
> ? kernel sources)
> None of these gates is added for now, since it's unclear whether these
> definitions are actually correct (the VCLK2_ENCT gate for example is
> defined, but only used in some commented block).
> 
> The main difference between all three SoCs seem to be the video (VPU)
> clocks. Apart from different supported clock rates (according to vpu.c
> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> (probably the same as on the Meson GX SoCs) to support glitch-free
> (clock rate) switching.
> None of these VPU clocks are not supported by our mainline meson8b
> clock driver yet though.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---

I think you should split the binding documentation and clk changes into separate
patches.

> -
> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---
> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-

The change being more platform than clock related, I'd prefer if Kevin or Carlo
ack it before we apply it.

Apart from this, the change looks good to me. Nice to see people taking interest
 in these SoCs. Would you mind telling us a bit more about the board you have
used for this task and the tests you have done ? It would maybe allow other
people to help you.

Cheers
Jerome

> ?3 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> index 2b7b3fa588d7..606da38c0959 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> @@ -1,11 +1,14 @@
> -* Amlogic Meson8b Clock and Reset Unit
> +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
> ?
> -The Amlogic Meson8b clock controller generates and supplies clock to various
> -controllers within the SoC.
> +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
> +supplies clock to various controllers within the SoC.
> ?
> ?Required Properties:
> ?
> -- compatible: should be "amlogic,meson8b-clkc"
> +- compatible: must be one of:
> +	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
> +	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
> +	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
> ?- reg: it must be composed by two tuples:
> ?	0) physical base address of the xtal register and length of memory
> ?	???mapped region.
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 19480bcc7046..4a806203b73c 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
> ?	bool
> ?	depends on COMMON_CLK_AMLOGIC
> ?	help
> -	??Support for the clock controller on AmLogic S805 devices, aka
> -	??meson8b. Say Y if you want peripherals and CPU frequency scaling to
> -	??work.
> +	??Support for the clock controller on AmLogic S802 (Meson8),
> +	??S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
> +	??want peripherals and CPU frequency scaling to work.
> ?
> ?config COMMON_CLK_GXBB
> ?	bool
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index bfd1690724de..94c55e79cdde 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -1,5 +1,6 @@
> ?/*
> - * AmLogic S805 / Meson8b Clock Controller Driver
> + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
> + * Driver
> ? *
> ? * Copyright (c) 2015 Endless Mobile, Inc.
> ? * Author: Carlo Caione <carlo@endlessm.com>
> @@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
> *pdev)
> ?}
> ?
> ?static const struct of_device_id meson8b_clkc_match_table[] = {
> +	{ .compatible = "amlogic,meson8-clkc" },
> ?	{ .compatible = "amlogic,meson8b-clkc" },
> +	{ .compatible = "amlogic,meson8m2-clkc" },
> ?	{ }
> ?};
> ?

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> based on the code from the Amlogic GPL kernel sources. Add separate
> compatibles for each SoC to make sure that we can easily implement
> all the small differences for each SoC later on.
> 
> In general the Meson8 and Meson8m2 seem to be almost identical as they
> even share the same mach-meson8 directory in Amlogic's GPL kernel
> sources.
> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> because they are all using the same PLL values, 90% of the clock gates
> are the same (the actual diffstat of the mach-meson8/clock.c and
> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> all commented out code).
> The difference between the Meson8 and Meson8b clock gates seem to be:
> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
> ? of "PERIPHS_TOP" (on Meson8b)
> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
> ? kernel sources)
> None of these gates is added for now, since it's unclear whether these
> definitions are actually correct (the VCLK2_ENCT gate for example is
> defined, but only used in some commented block).
> 
> The main difference between all three SoCs seem to be the video (VPU)
> clocks. Apart from different supported clock rates (according to vpu.c
> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> (probably the same as on the Meson GX SoCs) to support glitch-free
> (clock rate) switching.
> None of these VPU clocks are not supported by our mainline meson8b
> clock driver yet though.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---

I think you should split the binding documentation and clk changes into separate
patches.

> -
> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---
> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-

The change being more platform than clock related, I'd prefer if Kevin or Carlo
ack it before we apply it.

Apart from this, the change looks good to me. Nice to see people taking interest
 in these SoCs. Would you mind telling us a bit more about the board you have
used for this task and the tests you have done ? It would maybe allow other
people to help you.

Cheers
Jerome

> ?3 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> index 2b7b3fa588d7..606da38c0959 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
> @@ -1,11 +1,14 @@
> -* Amlogic Meson8b Clock and Reset Unit
> +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
> ?
> -The Amlogic Meson8b clock controller generates and supplies clock to various
> -controllers within the SoC.
> +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
> +supplies clock to various controllers within the SoC.
> ?
> ?Required Properties:
> ?
> -- compatible: should be "amlogic,meson8b-clkc"
> +- compatible: must be one of:
> +	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
> +	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
> +	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
> ?- reg: it must be composed by two tuples:
> ?	0) physical base address of the xtal register and length of memory
> ?	???mapped region.
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 19480bcc7046..4a806203b73c 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
> ?	bool
> ?	depends on COMMON_CLK_AMLOGIC
> ?	help
> -	??Support for the clock controller on AmLogic S805 devices, aka
> -	??meson8b. Say Y if you want peripherals and CPU frequency scaling to
> -	??work.
> +	??Support for the clock controller on AmLogic S802 (Meson8),
> +	??S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
> +	??want peripherals and CPU frequency scaling to work.
> ?
> ?config COMMON_CLK_GXBB
> ?	bool
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index bfd1690724de..94c55e79cdde 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -1,5 +1,6 @@
> ?/*
> - * AmLogic S805 / Meson8b Clock Controller Driver
> + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
> + * Driver
> ? *
> ? * Copyright (c) 2015 Endless Mobile, Inc.
> ? * Author: Carlo Caione <carlo@endlessm.com>
> @@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
> *pdev)
> ?}
> ?
> ?static const struct of_device_id meson8b_clkc_match_table[] = {
> +	{ .compatible = "amlogic,meson8-clkc" },
> ?	{ .compatible = "amlogic,meson8b-clkc" },
> +	{ .compatible = "amlogic,meson8m2-clkc" },
> ?	{ }
> ?};
> ?

Re: [PATCH 2/3] arm: meson: select the clock controller for Meson8

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
> controller driver can also be used on Meson8 SoCs now that we have a
> separate compatible for it.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> ---
>  arch/arm/mach-meson/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
> index b6e3acc63e14..ee30511849ca 100644
> --- a/arch/arm/mach-meson/Kconfig
> +++ b/arch/arm/mach-meson/Kconfig
> @@ -21,6 +21,7 @@ config MACH_MESON8
>  	bool "Amlogic Meson8 SoCs support"
>  	default ARCH_MESON
>  	select MESON6_TIMER
> +	select COMMON_CLK_MESON8B
>  
>  config MACH_MESON8B
>  	bool "Amlogic Meson8b SoCs support"

[PATCH 2/3] arm: meson: select the clock controller for Meson8

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
> controller driver can also be used on Meson8 SoCs now that we have a
> separate compatible for it.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> ---
> ?arch/arm/mach-meson/Kconfig | 1 +
> ?1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
> index b6e3acc63e14..ee30511849ca 100644
> --- a/arch/arm/mach-meson/Kconfig
> +++ b/arch/arm/mach-meson/Kconfig
> @@ -21,6 +21,7 @@ config MACH_MESON8
> ?	bool "Amlogic Meson8 SoCs support"
> ?	default ARCH_MESON
> ?	select MESON6_TIMER
> +	select COMMON_CLK_MESON8B
> ?
> ?config MACH_MESON8B
> ?	bool "Amlogic Meson8b SoCs support"

[PATCH 2/3] arm: meson: select the clock controller for Meson8

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
> controller driver can also be used on Meson8 SoCs now that we have a
> separate compatible for it.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> ---
> ?arch/arm/mach-meson/Kconfig | 1 +
> ?1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
> index b6e3acc63e14..ee30511849ca 100644
> --- a/arch/arm/mach-meson/Kconfig
> +++ b/arch/arm/mach-meson/Kconfig
> @@ -21,6 +21,7 @@ config MACH_MESON8
> ?	bool "Amlogic Meson8 SoCs support"
> ?	default ARCH_MESON
> ?	select MESON6_TIMER
> +	select COMMON_CLK_MESON8B
> ?
> ?config MACH_MESON8B
> ?	bool "Amlogic Meson8b SoCs support"

Re: [PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> This removes the dummy clk81 gate and replaces it with the actual clock
> controller's CLKID_CLK81. This will also allow us to pass the real clock
> IDs to all devices where the clock is controlled by clkc in the future.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

This is going in the right direction and at least align meson8 and meson8b.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

Later on, I'm wondering if some of these clock assignments should be moved to
meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar 

> ---
>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 6993077331c7..9b0b3ddbb17e 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -43,6 +43,7 @@
>   *     OTHER DEALINGS IN THE SOFTWARE.
>   */
>  
> +#include <dt-bindings/clock/meson8b-clkc.h>
>  #include <dt-bindings/gpio/meson8-gpio.h>
>  /include/ "meson.dtsi"
>  
> @@ -82,13 +83,6 @@
>  			reg = <0x203>;
>  		};
>  	};
> -
> -	clk81: clk@0 {
> -		#clock-cells = <0>;
> -		compatible = "fixed-clock";
> -		clock-frequency = <141666666>;
> -	};
> -
>  }; /* end of / */
>  
>  &aobus {
> @@ -126,6 +120,12 @@
>  };
>  
>  &cbus {
> +	clkc: clock-controller@4000 {
> +		#clock-cells = <1>;
> +		compatible = "amlogic,meson8-clkc";
> +		reg = <0x8000 0x4>, <0x4000 0x460>;
> +	};
> +
>  	pinctrl_cbus: pinctrl@9880 {
>  		compatible = "amlogic,meson8-cbus-pinctrl";
>  		reg = <0x9880 0x10>;
> @@ -172,20 +172,20 @@
>  };
>  
>  &ethmac {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  	clock-names = "stmmaceth";
>  };
>  
>  &i2c_AO {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };
>  
>  &i2c_A {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };
>  
>  &i2c_B {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };
>  
>  &L2 {
> @@ -195,21 +195,21 @@
>  };
>  
>  &spifc {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };
>  
>  &uart_AO {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };
>  
>  &uart_A {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };
>  
>  &uart_B {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };
>  
>  &uart_C {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
>  };

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> This removes the dummy clk81 gate and replaces it with the actual clock
> controller's CLKID_CLK81. This will also allow us to pass the real clock
> IDs to all devices where the clock is controlled by clkc in the future.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

This is going in the right direction and at least align meson8 and meson8b.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

Later on, I'm wondering if some of these clock assignments should be moved to
meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar 

> ---
> ?arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
> ?1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 6993077331c7..9b0b3ddbb17e 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -43,6 +43,7 @@
> ? *?????OTHER DEALINGS IN THE SOFTWARE.
> ? */
> ?
> +#include <dt-bindings/clock/meson8b-clkc.h>
> ?#include <dt-bindings/gpio/meson8-gpio.h>
> ?/include/ "meson.dtsi"
> ?
> @@ -82,13 +83,6 @@
> ?			reg = <0x203>;
> ?		};
> ?	};
> -
> -	clk81: clk at 0 {
> -		#clock-cells = <0>;
> -		compatible = "fixed-clock";
> -		clock-frequency = <141666666>;
> -	};
> -
> ?}; /* end of / */
> ?
> ?&aobus {
> @@ -126,6 +120,12 @@
> ?};
> ?
> ?&cbus {
> +	clkc: clock-controller at 4000 {
> +		#clock-cells = <1>;
> +		compatible = "amlogic,meson8-clkc";
> +		reg = <0x8000 0x4>, <0x4000 0x460>;
> +	};
> +
> ?	pinctrl_cbus: pinctrl at 9880 {
> ?		compatible = "amlogic,meson8-cbus-pinctrl";
> ?		reg = <0x9880 0x10>;
> @@ -172,20 +172,20 @@
> ?};
> ?
> ?&ethmac {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?	clock-names = "stmmaceth";
> ?};
> ?
> ?&i2c_AO {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&i2c_A {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&i2c_B {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&L2 {
> @@ -195,21 +195,21 @@
> ?};
> ?
> ?&spifc {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_AO {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_A {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_B {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_C {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Jerome Brunet]

On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> This removes the dummy clk81 gate and replaces it with the actual clock
> controller's CLKID_CLK81. This will also allow us to pass the real clock
> IDs to all devices where the clock is controlled by clkc in the future.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

This is going in the right direction and at least align meson8 and meson8b.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

Later on, I'm wondering if some of these clock assignments should be moved to
meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar 

> ---
> ?arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
> ?1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 6993077331c7..9b0b3ddbb17e 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -43,6 +43,7 @@
> ? *?????OTHER DEALINGS IN THE SOFTWARE.
> ? */
> ?
> +#include <dt-bindings/clock/meson8b-clkc.h>
> ?#include <dt-bindings/gpio/meson8-gpio.h>
> ?/include/ "meson.dtsi"
> ?
> @@ -82,13 +83,6 @@
> ?			reg = <0x203>;
> ?		};
> ?	};
> -
> -	clk81: clk at 0 {
> -		#clock-cells = <0>;
> -		compatible = "fixed-clock";
> -		clock-frequency = <141666666>;
> -	};
> -
> ?}; /* end of / */
> ?
> ?&aobus {
> @@ -126,6 +120,12 @@
> ?};
> ?
> ?&cbus {
> +	clkc: clock-controller at 4000 {
> +		#clock-cells = <1>;
> +		compatible = "amlogic,meson8-clkc";
> +		reg = <0x8000 0x4>, <0x4000 0x460>;
> +	};
> +
> ?	pinctrl_cbus: pinctrl at 9880 {
> ?		compatible = "amlogic,meson8-cbus-pinctrl";
> ?		reg = <0x9880 0x10>;
> @@ -172,20 +172,20 @@
> ?};
> ?
> ?&ethmac {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?	clock-names = "stmmaceth";
> ?};
> ?
> ?&i2c_AO {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&i2c_A {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&i2c_B {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&L2 {
> @@ -195,21 +195,21 @@
> ?};
> ?
> ?&spifc {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_AO {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_A {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_B {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};
> ?
> ?&uart_C {
> -	clocks = <&clk81>;
> +	clocks = <&clkc CLKID_CLK81>;
> ?};

Re: [PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Martin Blumenstingl]

Hi Jerome,

On Sun, Jun 4, 2017 at 10:20 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> This removes the dummy clk81 gate and replaces it with the actual clock
>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>> IDs to all devices where the clock is controlled by clkc in the future.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This is going in the right direction and at least align meson8 and meson8b.
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
that was quick, thanks!

> Later on, I'm wondering if some of these clock assignments should be moved to
> meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar
actually I think that the Meson6/MX/<however it is called> clock
controller is different (based on a quick look).
so we may end up with a similar situation that we have on
GXBB/GXL/GXM: the clock controller will stay in the corresponding
.dtsi and we have to "duplicate" the clock assignments for each SoC

however, I guess at some point we can create a .dtsi with all the bits
that are shared between Meson8 and Meson8b (during my experiments
meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of
compatibles). we can discuss whether we want to move the clock
controller to that shared/common .dtsi as well once we start
generalizing this

>> ---
>>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>>  1 file changed, 16 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>> index 6993077331c7..9b0b3ddbb17e 100644
>> --- a/arch/arm/boot/dts/meson8.dtsi
>> +++ b/arch/arm/boot/dts/meson8.dtsi
>> @@ -43,6 +43,7 @@
>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>   */
>>
>> +#include <dt-bindings/clock/meson8b-clkc.h>
>>  #include <dt-bindings/gpio/meson8-gpio.h>
>>  /include/ "meson.dtsi"
>>
>> @@ -82,13 +83,6 @@
>>                       reg = <0x203>;
>>               };
>>       };
>> -
>> -     clk81: clk@0 {
>> -             #clock-cells = <0>;
>> -             compatible = "fixed-clock";
>> -             clock-frequency = <141666666>;
>> -     };
>> -
>>  }; /* end of / */
>>
>>  &aobus {
>> @@ -126,6 +120,12 @@
>>  };
>>
>>  &cbus {
>> +     clkc: clock-controller@4000 {
>> +             #clock-cells = <1>;
>> +             compatible = "amlogic,meson8-clkc";
>> +             reg = <0x8000 0x4>, <0x4000 0x460>;
>> +     };
>> +
>>       pinctrl_cbus: pinctrl@9880 {
>>               compatible = "amlogic,meson8-cbus-pinctrl";
>>               reg = <0x9880 0x10>;
>> @@ -172,20 +172,20 @@
>>  };
>>
>>  &ethmac {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>       clock-names = "stmmaceth";
>>  };
>>
>>  &i2c_AO {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &i2c_A {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &i2c_B {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &L2 {
>> @@ -195,21 +195,21 @@
>>  };
>>
>>  &spifc {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_AO {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_A {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_B {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_C {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Martin Blumenstingl]

Hi Jerome,

On Sun, Jun 4, 2017 at 10:20 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> This removes the dummy clk81 gate and replaces it with the actual clock
>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>> IDs to all devices where the clock is controlled by clkc in the future.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This is going in the right direction and at least align meson8 and meson8b.
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
that was quick, thanks!

> Later on, I'm wondering if some of these clock assignments should be moved to
> meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar
actually I think that the Meson6/MX/<however it is called> clock
controller is different (based on a quick look).
so we may end up with a similar situation that we have on
GXBB/GXL/GXM: the clock controller will stay in the corresponding
.dtsi and we have to "duplicate" the clock assignments for each SoC

however, I guess at some point we can create a .dtsi with all the bits
that are shared between Meson8 and Meson8b (during my experiments
meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of
compatibles). we can discuss whether we want to move the clock
controller to that shared/common .dtsi as well once we start
generalizing this

>> ---
>>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>>  1 file changed, 16 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>> index 6993077331c7..9b0b3ddbb17e 100644
>> --- a/arch/arm/boot/dts/meson8.dtsi
>> +++ b/arch/arm/boot/dts/meson8.dtsi
>> @@ -43,6 +43,7 @@
>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>   */
>>
>> +#include <dt-bindings/clock/meson8b-clkc.h>
>>  #include <dt-bindings/gpio/meson8-gpio.h>
>>  /include/ "meson.dtsi"
>>
>> @@ -82,13 +83,6 @@
>>                       reg = <0x203>;
>>               };
>>       };
>> -
>> -     clk81: clk at 0 {
>> -             #clock-cells = <0>;
>> -             compatible = "fixed-clock";
>> -             clock-frequency = <141666666>;
>> -     };
>> -
>>  }; /* end of / */
>>
>>  &aobus {
>> @@ -126,6 +120,12 @@
>>  };
>>
>>  &cbus {
>> +     clkc: clock-controller at 4000 {
>> +             #clock-cells = <1>;
>> +             compatible = "amlogic,meson8-clkc";
>> +             reg = <0x8000 0x4>, <0x4000 0x460>;
>> +     };
>> +
>>       pinctrl_cbus: pinctrl at 9880 {
>>               compatible = "amlogic,meson8-cbus-pinctrl";
>>               reg = <0x9880 0x10>;
>> @@ -172,20 +172,20 @@
>>  };
>>
>>  &ethmac {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>       clock-names = "stmmaceth";
>>  };
>>
>>  &i2c_AO {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &i2c_A {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &i2c_B {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &L2 {
>> @@ -195,21 +195,21 @@
>>  };
>>
>>  &spifc {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_AO {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_A {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_B {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_C {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Martin Blumenstingl]

Hi Jerome,

On Sun, Jun 4, 2017 at 10:20 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> This removes the dummy clk81 gate and replaces it with the actual clock
>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>> IDs to all devices where the clock is controlled by clkc in the future.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This is going in the right direction and at least align meson8 and meson8b.
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
that was quick, thanks!

> Later on, I'm wondering if some of these clock assignments should be moved to
> meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar
actually I think that the Meson6/MX/<however it is called> clock
controller is different (based on a quick look).
so we may end up with a similar situation that we have on
GXBB/GXL/GXM: the clock controller will stay in the corresponding
.dtsi and we have to "duplicate" the clock assignments for each SoC

however, I guess at some point we can create a .dtsi with all the bits
that are shared between Meson8 and Meson8b (during my experiments
meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of
compatibles). we can discuss whether we want to move the clock
controller to that shared/common .dtsi as well once we start
generalizing this

>> ---
>>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>>  1 file changed, 16 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>> index 6993077331c7..9b0b3ddbb17e 100644
>> --- a/arch/arm/boot/dts/meson8.dtsi
>> +++ b/arch/arm/boot/dts/meson8.dtsi
>> @@ -43,6 +43,7 @@
>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>   */
>>
>> +#include <dt-bindings/clock/meson8b-clkc.h>
>>  #include <dt-bindings/gpio/meson8-gpio.h>
>>  /include/ "meson.dtsi"
>>
>> @@ -82,13 +83,6 @@
>>                       reg = <0x203>;
>>               };
>>       };
>> -
>> -     clk81: clk at 0 {
>> -             #clock-cells = <0>;
>> -             compatible = "fixed-clock";
>> -             clock-frequency = <141666666>;
>> -     };
>> -
>>  }; /* end of / */
>>
>>  &aobus {
>> @@ -126,6 +120,12 @@
>>  };
>>
>>  &cbus {
>> +     clkc: clock-controller at 4000 {
>> +             #clock-cells = <1>;
>> +             compatible = "amlogic,meson8-clkc";
>> +             reg = <0x8000 0x4>, <0x4000 0x460>;
>> +     };
>> +
>>       pinctrl_cbus: pinctrl at 9880 {
>>               compatible = "amlogic,meson8-cbus-pinctrl";
>>               reg = <0x9880 0x10>;
>> @@ -172,20 +172,20 @@
>>  };
>>
>>  &ethmac {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>       clock-names = "stmmaceth";
>>  };
>>
>>  &i2c_AO {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &i2c_A {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &i2c_B {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &L2 {
>> @@ -195,21 +195,21 @@
>>  };
>>
>>  &spifc {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_AO {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_A {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_B {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>>
>>  &uart_C {
>> -     clocks = <&clk81>;
>> +     clocks = <&clkc CLKID_CLK81>;
>>  };
>

Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Martin Blumenstingl]

On Sun, Jun 4, 2017 at 9:58 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
>> based on the code from the Amlogic GPL kernel sources. Add separate
>> compatibles for each SoC to make sure that we can easily implement
>> all the small differences for each SoC later on.
>>
>> In general the Meson8 and Meson8m2 seem to be almost identical as they
>> even share the same mach-meson8 directory in Amlogic's GPL kernel
>> sources.
>> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
>> because they are all using the same PLL values, 90% of the clock gates
>> are the same (the actual diffstat of the mach-meson8/clock.c and
>> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
>> all commented out code).
>> The difference between the Meson8 and Meson8b clock gates seem to be:
>> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>>   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
>> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>>   of "PERIPHS_TOP" (on Meson8b)
>> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>>   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>>   kernel sources)
>> None of these gates is added for now, since it's unclear whether these
>> definitions are actually correct (the VCLK2_ENCT gate for example is
>> defined, but only used in some commented block).
>>
>> The main difference between all three SoCs seem to be the video (VPU)
>> clocks. Apart from different supported clock rates (according to vpu.c
>> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
>> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
>> (probably the same as on the Meson GX SoCs) to support glitch-free
>> (clock rate) switching.
>> None of these VPU clocks are not supported by our mainline meson8b
>> clock driver yet though.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>>  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++---
>
> I think you should split the binding documentation and clk changes into separate
> patches.
OK, from what I know is that for "trivial" changes the driver and
dt-binding changes can go through one patch.
this patch started as a four-line patch which added two lines of
documentation and two lines of driver code.
however, with all the Kconfig/comment/etc updates I think that you are
right and it's worth splitting this into two patches (one for the
clock driver and one for the dt-binding changes)

>> -
>>  drivers/clk/meson/Kconfig                                     |  6 +++---
>>  drivers/clk/meson/meson8b.c                                   |  5 ++++-
>
> The change being more platform than clock related, I'd prefer if Kevin or Carlo
> ack it before we apply it.
yes, especially since Carlo wrote the clock driver (and has worked for
his company with Meson8b SoCs)

> Apart from this, the change looks good to me. Nice to see people taking interest
>  in these SoCs. Would you mind telling us a bit more about the board you have
> used for this task and the tests you have done ? It would maybe allow other
> people to help you.
Oleg has already asked if he could help testing: [0]
he confirmed that the clock controller (and my work-in-progress MMC
driver) works fine on his "Tronsmart MXIII Plus" (Meson8m2 aka S812).
I personally have a Akaso M8S (Meson8m2 aka S812, 2GiB RAM, Fast
Ethernet, 8GB NAND flash and a Realtek RTL8723BS SDIO wifi/bluetooth
chip)

on my own device I could even get the RTL8723BS driver to load the
firmware (I don't get any results when scanning, but I blame the
strange driver for now). this means that PWM works fine as well (so
the period and duty cycle are calculated correctly - or in other
words: it seems that the input clocks are correct and lead to a 32.768
kHz PWM clock output)

USB is working fine for me, whereas Oleg gets an error on his device
in the PHY driver ("USB ID detect failed!") -> this also seems to
happen on some GXBB boards, so it's unrelated to the gates (..I
guess).

> Cheers
> Jerome
>
>>  3 files changed, 14 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> index 2b7b3fa588d7..606da38c0959 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> @@ -1,11 +1,14 @@
>> -* Amlogic Meson8b Clock and Reset Unit
>> +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
>>
>> -The Amlogic Meson8b clock controller generates and supplies clock to various
>> -controllers within the SoC.
>> +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
>> +supplies clock to various controllers within the SoC.
>>
>>  Required Properties:
>>
>> -- compatible: should be "amlogic,meson8b-clkc"
>> +- compatible: must be one of:
>> +     - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
>> +     - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
>> +     - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
>>  - reg: it must be composed by two tuples:
>>       0) physical base address of the xtal register and length of memory
>>          mapped region.
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 19480bcc7046..4a806203b73c 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
>>       bool
>>       depends on COMMON_CLK_AMLOGIC
>>       help
>> -       Support for the clock controller on AmLogic S805 devices, aka
>> -       meson8b. Say Y if you want peripherals and CPU frequency scaling to
>> -       work.
>> +       Support for the clock controller on AmLogic S802 (Meson8),
>> +       S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
>> +       want peripherals and CPU frequency scaling to work.
>>
>>  config COMMON_CLK_GXBB
>>       bool
>> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
>> index bfd1690724de..94c55e79cdde 100644
>> --- a/drivers/clk/meson/meson8b.c
>> +++ b/drivers/clk/meson/meson8b.c
>> @@ -1,5 +1,6 @@
>>  /*
>> - * AmLogic S805 / Meson8b Clock Controller Driver
>> + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
>> + * Driver
>>   *
>>   * Copyright (c) 2015 Endless Mobile, Inc.
>>   * Author: Carlo Caione <carlo@endlessm.com>
>> @@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
>> *pdev)
>>  }
>>
>>  static const struct of_device_id meson8b_clkc_match_table[] = {
>> +     { .compatible = "amlogic,meson8-clkc" },
>>       { .compatible = "amlogic,meson8b-clkc" },
>> +     { .compatible = "amlogic,meson8m2-clkc" },
>>       { }
>>  };
>>
>

Regards,
Martin

[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-May/003601.html
[1] http://www.akaso.net/akaso-m8s-tv-box4kandroidamlogic-s812quad-core-2gb-ram-8gb-flashkodihdmiwifibluetooth-4-0-media-player/

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Martin Blumenstingl]

On Sun, Jun 4, 2017 at 9:58 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
>> based on the code from the Amlogic GPL kernel sources. Add separate
>> compatibles for each SoC to make sure that we can easily implement
>> all the small differences for each SoC later on.
>>
>> In general the Meson8 and Meson8m2 seem to be almost identical as they
>> even share the same mach-meson8 directory in Amlogic's GPL kernel
>> sources.
>> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
>> because they are all using the same PLL values, 90% of the clock gates
>> are the same (the actual diffstat of the mach-meson8/clock.c and
>> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
>> all commented out code).
>> The difference between the Meson8 and Meson8b clock gates seem to be:
>> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>>   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
>> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>>   of "PERIPHS_TOP" (on Meson8b)
>> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>>   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>>   kernel sources)
>> None of these gates is added for now, since it's unclear whether these
>> definitions are actually correct (the VCLK2_ENCT gate for example is
>> defined, but only used in some commented block).
>>
>> The main difference between all three SoCs seem to be the video (VPU)
>> clocks. Apart from different supported clock rates (according to vpu.c
>> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
>> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
>> (probably the same as on the Meson GX SoCs) to support glitch-free
>> (clock rate) switching.
>> None of these VPU clocks are not supported by our mainline meson8b
>> clock driver yet though.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>>  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++---
>
> I think you should split the binding documentation and clk changes into separate
> patches.
OK, from what I know is that for "trivial" changes the driver and
dt-binding changes can go through one patch.
this patch started as a four-line patch which added two lines of
documentation and two lines of driver code.
however, with all the Kconfig/comment/etc updates I think that you are
right and it's worth splitting this into two patches (one for the
clock driver and one for the dt-binding changes)

>> -
>>  drivers/clk/meson/Kconfig                                     |  6 +++---
>>  drivers/clk/meson/meson8b.c                                   |  5 ++++-
>
> The change being more platform than clock related, I'd prefer if Kevin or Carlo
> ack it before we apply it.
yes, especially since Carlo wrote the clock driver (and has worked for
his company with Meson8b SoCs)

> Apart from this, the change looks good to me. Nice to see people taking interest
>  in these SoCs. Would you mind telling us a bit more about the board you have
> used for this task and the tests you have done ? It would maybe allow other
> people to help you.
Oleg has already asked if he could help testing: [0]
he confirmed that the clock controller (and my work-in-progress MMC
driver) works fine on his "Tronsmart MXIII Plus" (Meson8m2 aka S812).
I personally have a Akaso M8S (Meson8m2 aka S812, 2GiB RAM, Fast
Ethernet, 8GB NAND flash and a Realtek RTL8723BS SDIO wifi/bluetooth
chip)

on my own device I could even get the RTL8723BS driver to load the
firmware (I don't get any results when scanning, but I blame the
strange driver for now). this means that PWM works fine as well (so
the period and duty cycle are calculated correctly - or in other
words: it seems that the input clocks are correct and lead to a 32.768
kHz PWM clock output)

USB is working fine for me, whereas Oleg gets an error on his device
in the PHY driver ("USB ID detect failed!") -> this also seems to
happen on some GXBB boards, so it's unrelated to the gates (..I
guess).

> Cheers
> Jerome
>
>>  3 files changed, 14 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> index 2b7b3fa588d7..606da38c0959 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> @@ -1,11 +1,14 @@
>> -* Amlogic Meson8b Clock and Reset Unit
>> +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
>>
>> -The Amlogic Meson8b clock controller generates and supplies clock to various
>> -controllers within the SoC.
>> +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
>> +supplies clock to various controllers within the SoC.
>>
>>  Required Properties:
>>
>> -- compatible: should be "amlogic,meson8b-clkc"
>> +- compatible: must be one of:
>> +     - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
>> +     - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
>> +     - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
>>  - reg: it must be composed by two tuples:
>>       0) physical base address of the xtal register and length of memory
>>          mapped region.
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 19480bcc7046..4a806203b73c 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
>>       bool
>>       depends on COMMON_CLK_AMLOGIC
>>       help
>> -       Support for the clock controller on AmLogic S805 devices, aka
>> -       meson8b. Say Y if you want peripherals and CPU frequency scaling to
>> -       work.
>> +       Support for the clock controller on AmLogic S802 (Meson8),
>> +       S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
>> +       want peripherals and CPU frequency scaling to work.
>>
>>  config COMMON_CLK_GXBB
>>       bool
>> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
>> index bfd1690724de..94c55e79cdde 100644
>> --- a/drivers/clk/meson/meson8b.c
>> +++ b/drivers/clk/meson/meson8b.c
>> @@ -1,5 +1,6 @@
>>  /*
>> - * AmLogic S805 / Meson8b Clock Controller Driver
>> + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
>> + * Driver
>>   *
>>   * Copyright (c) 2015 Endless Mobile, Inc.
>>   * Author: Carlo Caione <carlo@endlessm.com>
>> @@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
>> *pdev)
>>  }
>>
>>  static const struct of_device_id meson8b_clkc_match_table[] = {
>> +     { .compatible = "amlogic,meson8-clkc" },
>>       { .compatible = "amlogic,meson8b-clkc" },
>> +     { .compatible = "amlogic,meson8m2-clkc" },
>>       { }
>>  };
>>
>

Regards,
Martin

[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-May/003601.html
[1] http://www.akaso.net/akaso-m8s-tv-box4kandroidamlogic-s812quad-core-2gb-ram-8gb-flashkodihdmiwifibluetooth-4-0-media-player/

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Martin Blumenstingl]

On Sun, Jun 4, 2017 at 9:58 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
>> based on the code from the Amlogic GPL kernel sources. Add separate
>> compatibles for each SoC to make sure that we can easily implement
>> all the small differences for each SoC later on.
>>
>> In general the Meson8 and Meson8m2 seem to be almost identical as they
>> even share the same mach-meson8 directory in Amlogic's GPL kernel
>> sources.
>> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
>> because they are all using the same PLL values, 90% of the clock gates
>> are the same (the actual diffstat of the mach-meson8/clock.c and
>> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
>> all commented out code).
>> The difference between the Meson8 and Meson8b clock gates seem to be:
>> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>>   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
>> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>>   of "PERIPHS_TOP" (on Meson8b)
>> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>>   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>>   kernel sources)
>> None of these gates is added for now, since it's unclear whether these
>> definitions are actually correct (the VCLK2_ENCT gate for example is
>> defined, but only used in some commented block).
>>
>> The main difference between all three SoCs seem to be the video (VPU)
>> clocks. Apart from different supported clock rates (according to vpu.c
>> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
>> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
>> (probably the same as on the Meson GX SoCs) to support glitch-free
>> (clock rate) switching.
>> None of these VPU clocks are not supported by our mainline meson8b
>> clock driver yet though.
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>>  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++---
>
> I think you should split the binding documentation and clk changes into separate
> patches.
OK, from what I know is that for "trivial" changes the driver and
dt-binding changes can go through one patch.
this patch started as a four-line patch which added two lines of
documentation and two lines of driver code.
however, with all the Kconfig/comment/etc updates I think that you are
right and it's worth splitting this into two patches (one for the
clock driver and one for the dt-binding changes)

>> -
>>  drivers/clk/meson/Kconfig                                     |  6 +++---
>>  drivers/clk/meson/meson8b.c                                   |  5 ++++-
>
> The change being more platform than clock related, I'd prefer if Kevin or Carlo
> ack it before we apply it.
yes, especially since Carlo wrote the clock driver (and has worked for
his company with Meson8b SoCs)

> Apart from this, the change looks good to me. Nice to see people taking interest
>  in these SoCs. Would you mind telling us a bit more about the board you have
> used for this task and the tests you have done ? It would maybe allow other
> people to help you.
Oleg has already asked if he could help testing: [0]
he confirmed that the clock controller (and my work-in-progress MMC
driver) works fine on his "Tronsmart MXIII Plus" (Meson8m2 aka S812).
I personally have a Akaso M8S (Meson8m2 aka S812, 2GiB RAM, Fast
Ethernet, 8GB NAND flash and a Realtek RTL8723BS SDIO wifi/bluetooth
chip)

on my own device I could even get the RTL8723BS driver to load the
firmware (I don't get any results when scanning, but I blame the
strange driver for now). this means that PWM works fine as well (so
the period and duty cycle are calculated correctly - or in other
words: it seems that the input clocks are correct and lead to a 32.768
kHz PWM clock output)

USB is working fine for me, whereas Oleg gets an error on his device
in the PHY driver ("USB ID detect failed!") -> this also seems to
happen on some GXBB boards, so it's unrelated to the gates (..I
guess).

> Cheers
> Jerome
>
>>  3 files changed, 14 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> index 2b7b3fa588d7..606da38c0959 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
>> @@ -1,11 +1,14 @@
>> -* Amlogic Meson8b Clock and Reset Unit
>> +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
>>
>> -The Amlogic Meson8b clock controller generates and supplies clock to various
>> -controllers within the SoC.
>> +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
>> +supplies clock to various controllers within the SoC.
>>
>>  Required Properties:
>>
>> -- compatible: should be "amlogic,meson8b-clkc"
>> +- compatible: must be one of:
>> +     - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
>> +     - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
>> +     - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
>>  - reg: it must be composed by two tuples:
>>       0) physical base address of the xtal register and length of memory
>>          mapped region.
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 19480bcc7046..4a806203b73c 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
>>       bool
>>       depends on COMMON_CLK_AMLOGIC
>>       help
>> -       Support for the clock controller on AmLogic S805 devices, aka
>> -       meson8b. Say Y if you want peripherals and CPU frequency scaling to
>> -       work.
>> +       Support for the clock controller on AmLogic S802 (Meson8),
>> +       S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
>> +       want peripherals and CPU frequency scaling to work.
>>
>>  config COMMON_CLK_GXBB
>>       bool
>> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
>> index bfd1690724de..94c55e79cdde 100644
>> --- a/drivers/clk/meson/meson8b.c
>> +++ b/drivers/clk/meson/meson8b.c
>> @@ -1,5 +1,6 @@
>>  /*
>> - * AmLogic S805 / Meson8b Clock Controller Driver
>> + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
>> + * Driver
>>   *
>>   * Copyright (c) 2015 Endless Mobile, Inc.
>>   * Author: Carlo Caione <carlo@endlessm.com>
>> @@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
>> *pdev)
>>  }
>>
>>  static const struct of_device_id meson8b_clkc_match_table[] = {
>> +     { .compatible = "amlogic,meson8-clkc" },
>>       { .compatible = "amlogic,meson8b-clkc" },
>> +     { .compatible = "amlogic,meson8m2-clkc" },
>>       { }
>>  };
>>
>

Regards,
Martin

[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-May/003601.html
[1] http://www.akaso.net/akaso-m8s-tv-box4kandroidamlogic-s812quad-core-2gb-ram-8gb-flashkodihdmiwifibluetooth-4-0-media-player/

Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Mon, 2017-06-05 at 00:27 +0200, Martin Blumenstingl wrote:
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> 
> OK, from what I know is that for "trivial" changes the driver and
> dt-binding changes can go through one patch.
> this patch started as a four-line patch which added two lines of
> documentation and two lines of driver code.

I'm not aware of such tolerance but if you've have seen that the DT maintainers
are OK with it, feel free to point me to it.

Last time I heard about it, DT guys were using filter-branch on the kernel tree
to create a separate tree, so I was thinking that this "documentation as a
separate patch" was a hard rule ... but I may be wrong

> however, with all the Kconfig/comment/etc updates I think that you are
> right and it's worth splitting this into two patches (one for the
> clock driver and one for the dt-binding changes)

Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Mon, 2017-06-05 at 00:27 +0200, Martin Blumenstingl wrote:
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> 
> OK, from what I know is that for "trivial" changes the driver and
> dt-binding changes can go through one patch.
> this patch started as a four-line patch which added two lines of
> documentation and two lines of driver code.

I'm not aware of such tolerance but if you've have seen that the DT maintainers
are OK with it, feel free to point me to it.

Last time I heard about it, DT guys were using filter-branch on the kernel tree
to create a separate tree, so I was thinking that this "documentation as a
separate patch" was a hard rule ... but I may be wrong

> however, with all the Kconfig/comment/etc updates I think that you are
> right and it's worth splitting this into two patches (one for the
> clock driver and one for the dt-binding changes)

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Mon, 2017-06-05 at 00:27 +0200, Martin Blumenstingl wrote:
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> 
> OK, from what I know is that for "trivial" changes the driver and
> dt-binding changes can go through one patch.
> this patch started as a four-line patch which added two lines of
> documentation and two lines of driver code.

I'm not aware of such tolerance but if you've have seen that the DT maintainers
are OK with it, feel free to point me to it.

Last time I heard about it, DT guys were using filter-branch on the kernel tree
to create a separate tree, so I was thinking that this "documentation as a
separate patch" was a hard rule ... but I may be wrong

> however, with all the Kconfig/comment/etc updates I think that you are
> right and it's worth splitting this into two patches (one for the
> clock driver and one for the dt-binding changes)

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Mon, 2017-06-05 at 00:27 +0200, Martin Blumenstingl wrote:
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> 
> OK, from what I know is that for "trivial" changes the driver and
> dt-binding changes can go through one patch.
> this patch started as a four-line patch which added two lines of
> documentation and two lines of driver code.

I'm not aware of such tolerance but if you've have seen that the DT maintainers
are OK with it, feel free to point me to it.

Last time I heard about it, DT guys were using filter-branch on the kernel tree
to create a separate tree, so I was thinking that this "documentation as a
separate patch" was a hard rule ... but I may be wrong

> however, with all the Kconfig/comment/etc updates I think that you are
> right and it's worth splitting this into two patches (one for the
> clock driver and one for the dt-binding changes)

Re: [PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Neil Armstrong]

On 06/05/2017 12:13 AM, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Sun, Jun 4, 2017 at 10:20 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
>> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>>> This removes the dummy clk81 gate and replaces it with the actual clock
>>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>>> IDs to all devices where the clock is controlled by clkc in the future.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This is going in the right direction and at least align meson8 and meson8b.
>>
>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> that was quick, thanks!
> 
>> Later on, I'm wondering if some of these clock assignments should be moved to
>> meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar
> actually I think that the Meson6/MX/<however it is called> clock
> controller is different (based on a quick look).
> so we may end up with a similar situation that we have on
> GXBB/GXL/GXM: the clock controller will stay in the corresponding
> .dtsi and we have to "duplicate" the clock assignments for each SoC
> 
> however, I guess at some point we can create a .dtsi with all the bits
> that are shared between Meson8 and Meson8b (during my experiments
> meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of
> compatibles). we can discuss whether we want to move the clock
> controller to that shared/common .dtsi as well once we start
> generalizing this

Personally I think we should use the same schema as arm64 and leave the clock
definitions in the SoCs dtsi files.

Neil

> 
>>> ---
>>>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>>>  1 file changed, 16 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>>> index 6993077331c7..9b0b3ddbb17e 100644
>>> --- a/arch/arm/boot/dts/meson8.dtsi
>>> +++ b/arch/arm/boot/dts/meson8.dtsi
>>> @@ -43,6 +43,7 @@
>>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>>   */
>>>
>>> +#include <dt-bindings/clock/meson8b-clkc.h>
>>>  #include <dt-bindings/gpio/meson8-gpio.h>
>>>  /include/ "meson.dtsi"
>>>
>>> @@ -82,13 +83,6 @@
>>>                       reg = <0x203>;
>>>               };
>>>       };
>>> -
>>> -     clk81: clk@0 {
>>> -             #clock-cells = <0>;
>>> -             compatible = "fixed-clock";
>>> -             clock-frequency = <141666666>;
>>> -     };
>>> -
>>>  }; /* end of / */
>>>
>>>  &aobus {
>>> @@ -126,6 +120,12 @@
>>>  };
>>>
>>>  &cbus {
>>> +     clkc: clock-controller@4000 {
>>> +             #clock-cells = <1>;
>>> +             compatible = "amlogic,meson8-clkc";
>>> +             reg = <0x8000 0x4>, <0x4000 0x460>;
>>> +     };
>>> +
>>>       pinctrl_cbus: pinctrl@9880 {
>>>               compatible = "amlogic,meson8-cbus-pinctrl";
>>>               reg = <0x9880 0x10>;
>>> @@ -172,20 +172,20 @@
>>>  };
>>>
>>>  &ethmac {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>       clock-names = "stmmaceth";
>>>  };
>>>
>>>  &i2c_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &L2 {
>>> @@ -195,21 +195,21 @@
>>>  };
>>>
>>>  &spifc {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_C {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>

Re: [PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Neil Armstrong]

On 06/05/2017 12:13 AM, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Sun, Jun 4, 2017 at 10:20 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
>> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>>> This removes the dummy clk81 gate and replaces it with the actual clock
>>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>>> IDs to all devices where the clock is controlled by clkc in the future.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This is going in the right direction and at least align meson8 and meson8b.
>>
>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> that was quick, thanks!
> 
>> Later on, I'm wondering if some of these clock assignments should be moved to
>> meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar
> actually I think that the Meson6/MX/<however it is called> clock
> controller is different (based on a quick look).
> so we may end up with a similar situation that we have on
> GXBB/GXL/GXM: the clock controller will stay in the corresponding
> .dtsi and we have to "duplicate" the clock assignments for each SoC
> 
> however, I guess at some point we can create a .dtsi with all the bits
> that are shared between Meson8 and Meson8b (during my experiments
> meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of
> compatibles). we can discuss whether we want to move the clock
> controller to that shared/common .dtsi as well once we start
> generalizing this

Personally I think we should use the same schema as arm64 and leave the clock
definitions in the SoCs dtsi files.

Neil

> 
>>> ---
>>>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>>>  1 file changed, 16 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>>> index 6993077331c7..9b0b3ddbb17e 100644
>>> --- a/arch/arm/boot/dts/meson8.dtsi
>>> +++ b/arch/arm/boot/dts/meson8.dtsi
>>> @@ -43,6 +43,7 @@
>>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>>   */
>>>
>>> +#include <dt-bindings/clock/meson8b-clkc.h>
>>>  #include <dt-bindings/gpio/meson8-gpio.h>
>>>  /include/ "meson.dtsi"
>>>
>>> @@ -82,13 +83,6 @@
>>>                       reg = <0x203>;
>>>               };
>>>       };
>>> -
>>> -     clk81: clk@0 {
>>> -             #clock-cells = <0>;
>>> -             compatible = "fixed-clock";
>>> -             clock-frequency = <141666666>;
>>> -     };
>>> -
>>>  }; /* end of / */
>>>
>>>  &aobus {
>>> @@ -126,6 +120,12 @@
>>>  };
>>>
>>>  &cbus {
>>> +     clkc: clock-controller@4000 {
>>> +             #clock-cells = <1>;
>>> +             compatible = "amlogic,meson8-clkc";
>>> +             reg = <0x8000 0x4>, <0x4000 0x460>;
>>> +     };
>>> +
>>>       pinctrl_cbus: pinctrl@9880 {
>>>               compatible = "amlogic,meson8-cbus-pinctrl";
>>>               reg = <0x9880 0x10>;
>>> @@ -172,20 +172,20 @@
>>>  };
>>>
>>>  &ethmac {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>       clock-names = "stmmaceth";
>>>  };
>>>
>>>  &i2c_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &L2 {
>>> @@ -195,21 +195,21 @@
>>>  };
>>>
>>>  &spifc {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_C {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Neil Armstrong]

On 06/05/2017 12:13 AM, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Sun, Jun 4, 2017 at 10:20 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
>> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>>> This removes the dummy clk81 gate and replaces it with the actual clock
>>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>>> IDs to all devices where the clock is controlled by clkc in the future.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This is going in the right direction and at least align meson8 and meson8b.
>>
>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> that was quick, thanks!
> 
>> Later on, I'm wondering if some of these clock assignments should be moved to
>> meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar
> actually I think that the Meson6/MX/<however it is called> clock
> controller is different (based on a quick look).
> so we may end up with a similar situation that we have on
> GXBB/GXL/GXM: the clock controller will stay in the corresponding
> .dtsi and we have to "duplicate" the clock assignments for each SoC
> 
> however, I guess at some point we can create a .dtsi with all the bits
> that are shared between Meson8 and Meson8b (during my experiments
> meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of
> compatibles). we can discuss whether we want to move the clock
> controller to that shared/common .dtsi as well once we start
> generalizing this

Personally I think we should use the same schema as arm64 and leave the clock
definitions in the SoCs dtsi files.

Neil

> 
>>> ---
>>>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>>>  1 file changed, 16 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>>> index 6993077331c7..9b0b3ddbb17e 100644
>>> --- a/arch/arm/boot/dts/meson8.dtsi
>>> +++ b/arch/arm/boot/dts/meson8.dtsi
>>> @@ -43,6 +43,7 @@
>>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>>   */
>>>
>>> +#include <dt-bindings/clock/meson8b-clkc.h>
>>>  #include <dt-bindings/gpio/meson8-gpio.h>
>>>  /include/ "meson.dtsi"
>>>
>>> @@ -82,13 +83,6 @@
>>>                       reg = <0x203>;
>>>               };
>>>       };
>>> -
>>> -     clk81: clk at 0 {
>>> -             #clock-cells = <0>;
>>> -             compatible = "fixed-clock";
>>> -             clock-frequency = <141666666>;
>>> -     };
>>> -
>>>  }; /* end of / */
>>>
>>>  &aobus {
>>> @@ -126,6 +120,12 @@
>>>  };
>>>
>>>  &cbus {
>>> +     clkc: clock-controller at 4000 {
>>> +             #clock-cells = <1>;
>>> +             compatible = "amlogic,meson8-clkc";
>>> +             reg = <0x8000 0x4>, <0x4000 0x460>;
>>> +     };
>>> +
>>>       pinctrl_cbus: pinctrl at 9880 {
>>>               compatible = "amlogic,meson8-cbus-pinctrl";
>>>               reg = <0x9880 0x10>;
>>> @@ -172,20 +172,20 @@
>>>  };
>>>
>>>  &ethmac {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>       clock-names = "stmmaceth";
>>>  };
>>>
>>>  &i2c_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &L2 {
>>> @@ -195,21 +195,21 @@
>>>  };
>>>
>>>  &spifc {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_C {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Neil Armstrong]

On 06/05/2017 12:13 AM, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Sun, Jun 4, 2017 at 10:20 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
>> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>>> This removes the dummy clk81 gate and replaces it with the actual clock
>>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>>> IDs to all devices where the clock is controlled by clkc in the future.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This is going in the right direction and at least align meson8 and meson8b.
>>
>> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> that was quick, thanks!
> 
>> Later on, I'm wondering if some of these clock assignments should be moved to
>> meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar
> actually I think that the Meson6/MX/<however it is called> clock
> controller is different (based on a quick look).
> so we may end up with a similar situation that we have on
> GXBB/GXL/GXM: the clock controller will stay in the corresponding
> .dtsi and we have to "duplicate" the clock assignments for each SoC
> 
> however, I guess at some point we can create a .dtsi with all the bits
> that are shared between Meson8 and Meson8b (during my experiments
> meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of
> compatibles). we can discuss whether we want to move the clock
> controller to that shared/common .dtsi as well once we start
> generalizing this

Personally I think we should use the same schema as arm64 and leave the clock
definitions in the SoCs dtsi files.

Neil

> 
>>> ---
>>>  arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
>>>  1 file changed, 16 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
>>> index 6993077331c7..9b0b3ddbb17e 100644
>>> --- a/arch/arm/boot/dts/meson8.dtsi
>>> +++ b/arch/arm/boot/dts/meson8.dtsi
>>> @@ -43,6 +43,7 @@
>>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>>   */
>>>
>>> +#include <dt-bindings/clock/meson8b-clkc.h>
>>>  #include <dt-bindings/gpio/meson8-gpio.h>
>>>  /include/ "meson.dtsi"
>>>
>>> @@ -82,13 +83,6 @@
>>>                       reg = <0x203>;
>>>               };
>>>       };
>>> -
>>> -     clk81: clk at 0 {
>>> -             #clock-cells = <0>;
>>> -             compatible = "fixed-clock";
>>> -             clock-frequency = <141666666>;
>>> -     };
>>> -
>>>  }; /* end of / */
>>>
>>>  &aobus {
>>> @@ -126,6 +120,12 @@
>>>  };
>>>
>>>  &cbus {
>>> +     clkc: clock-controller at 4000 {
>>> +             #clock-cells = <1>;
>>> +             compatible = "amlogic,meson8-clkc";
>>> +             reg = <0x8000 0x4>, <0x4000 0x460>;
>>> +     };
>>> +
>>>       pinctrl_cbus: pinctrl at 9880 {
>>>               compatible = "amlogic,meson8-cbus-pinctrl";
>>>               reg = <0x9880 0x10>;
>>> @@ -172,20 +172,20 @@
>>>  };
>>>
>>>  &ethmac {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>       clock-names = "stmmaceth";
>>>  };
>>>
>>>  &i2c_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &i2c_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &L2 {
>>> @@ -195,21 +195,21 @@
>>>  };
>>>
>>>  &spifc {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_AO {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_A {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_B {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>>
>>>  &uart_C {
>>> -     clocks = <&clk81>;
>>> +     clocks = <&clkc CLKID_CLK81>;
>>>  };
>>

Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Rob Herring]

On Mon, Jun 05, 2017 at 10:23:28AM +0200, Jerome Brunet wrote:
> On Mon, 2017-06-05 at 00:27 +0200, Martin Blumenstingl wrote:
> > > I think you should split the binding documentation and clk changes into
> > > separate
> > > patches.
> > 
> > OK, from what I know is that for "trivial" changes the driver and
> > dt-binding changes can go through one patch.
> > this patch started as a four-line patch which added two lines of
> > documentation and two lines of driver code.
> 
> I'm not aware of such tolerance but if you've have seen that the DT maintainers
> are OK with it, feel free to point me to it.
> 
> Last time I heard about it, DT guys were using filter-branch on the kernel tree
> to create a separate tree, so I was thinking that this "documentation as a
> separate patch" was a hard rule ... but I may be wrong

That is one of the reasons, but there is no hard rule. It's not worth a 
respin just for that either.

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Rob Herring]

On Mon, Jun 05, 2017 at 10:23:28AM +0200, Jerome Brunet wrote:
> On Mon, 2017-06-05 at 00:27 +0200, Martin Blumenstingl wrote:
> > > I think you should split the binding documentation and clk changes into
> > > separate
> > > patches.
> > 
> > OK, from what I know is that for "trivial" changes the driver and
> > dt-binding changes can go through one patch.
> > this patch started as a four-line patch which added two lines of
> > documentation and two lines of driver code.
> 
> I'm not aware of such tolerance but if you've have seen that the DT maintainers
> are OK with it, feel free to point me to it.
> 
> Last time I heard about it, DT guys were using filter-branch on the kernel tree
> to create a separate tree, so I was thinking that this "documentation as a
> separate patch" was a hard rule ... but I may be wrong

That is one of the reasons, but there is no hard rule. It's not worth a 
respin just for that either.

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Rob Herring]

On Mon, Jun 05, 2017 at 10:23:28AM +0200, Jerome Brunet wrote:
> On Mon, 2017-06-05 at 00:27 +0200, Martin Blumenstingl wrote:
> > > I think you should split the binding documentation and clk changes into
> > > separate
> > > patches.
> > 
> > OK, from what I know is that for "trivial" changes the driver and
> > dt-binding changes can go through one patch.
> > this patch started as a four-line patch which added two lines of
> > documentation and two lines of driver code.
> 
> I'm not aware of such tolerance but if you've have seen that the DT maintainers
> are OK with it, feel free to point me to it.
> 
> Last time I heard about it, DT guys were using filter-branch on the kernel tree
> to create a separate tree, so I was thinking that this "documentation as a
> separate patch" was a hard rule ... but I may be wrong

That is one of the reasons, but there is no hard rule. It's not worth a 
respin just for that either.

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Kevin Hilman]

Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
>> based on the code from the Amlogic GPL kernel sources. Add separate
>> compatibles for each SoC to make sure that we can easily implement
>> all the small differences for each SoC later on.
>> 
>> In general the Meson8 and Meson8m2 seem to be almost identical as they
>> even share the same mach-meson8 directory in Amlogic's GPL kernel
>> sources.
>> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
>> because they are all using the same PLL values, 90% of the clock gates
>> are the same (the actual diffstat of the mach-meson8/clock.c and
>> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
>> all commented out code).
>> The difference between the Meson8 and Meson8b clock gates seem to be:
>> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>>   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
>> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>>   of "PERIPHS_TOP" (on Meson8b)
>> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>>   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>>   kernel sources)
>> None of these gates is added for now, since it's unclear whether these
>> definitions are actually correct (the VCLK2_ENCT gate for example is
>> defined, but only used in some commented block).
>> 
>> The main difference between all three SoCs seem to be the video (VPU)
>> clocks. Apart from different supported clock rates (according to vpu.c
>> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
>> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
>> (probably the same as on the Meson GX SoCs) to support glitch-free
>> (clock rate) switching.
>> None of these VPU clocks are not supported by our mainline meson8b
>> clock driver yet though.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>> ---
>>  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++---
>
> I think you should split the binding documentation and clk changes into separate
> patches.
>
>> -
>>  drivers/clk/meson/Kconfig                                     |  6 +++---
>>  drivers/clk/meson/meson8b.c                                   |  5 ++++-
>
> The change being more platform than clock related, I'd prefer if Kevin or Carlo
> ack it before we apply it.

Acked-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
>> based on the code from the Amlogic GPL kernel sources. Add separate
>> compatibles for each SoC to make sure that we can easily implement
>> all the small differences for each SoC later on.
>>=20
>> In general the Meson8 and Meson8m2 seem to be almost identical as they
>> even share the same mach-meson8 directory in Amlogic's GPL kernel
>> sources.
>> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
>> because they are all using the same PLL values, 90% of the clock gates
>> are the same (the actual diffstat of the mach-meson8/clock.c and
>> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
>> all commented out code).
>> The difference between the Meson8 and Meson8b clock gates seem to be:
>> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>> =C2=A0 CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
>> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>> =C2=A0 of "PERIPHS_TOP" (on Meson8b)
>> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>> =C2=A0 on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>> =C2=A0 kernel sources)
>> None of these gates is added for now, since it's unclear whether these
>> definitions are actually correct (the VCLK2_ENCT gate for example is
>> defined, but only used in some commented block).
>>=20
>> The main difference between all three SoCs seem to be the video (VPU)
>> clocks. Apart from different supported clock rates (according to vpu.c
>> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
>> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
>> (probably the same as on the Meson GX SoCs) to support glitch-free
>> (clock rate) switching.
>> None of these VPU clocks are not supported by our mainline meson8b
>> clock driver yet though.
>>=20
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>> =C2=A0.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0| 11 +++++++---
>
> I think you should split the binding documentation and clk changes into s=
eparate
> patches.
>
>> -
>> =C2=A0drivers/clk/meson/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A06 +++---
>> =C2=A0drivers/clk/meson/meson8b.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A05 ++++-
>
> The change being more platform than clock related, I'd prefer if Kevin or=
 Carlo
> ack it before we apply it.

Acked-by: Kevin Hilman <khilman@baylibre.com>

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
>> based on the code from the Amlogic GPL kernel sources. Add separate
>> compatibles for each SoC to make sure that we can easily implement
>> all the small differences for each SoC later on.
>> 
>> In general the Meson8 and Meson8m2 seem to be almost identical as they
>> even share the same mach-meson8 directory in Amlogic's GPL kernel
>> sources.
>> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
>> because they are all using the same PLL values, 90% of the clock gates
>> are the same (the actual diffstat of the mach-meson8/clock.c and
>> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
>> all commented out code).
>> The difference between the Meson8 and Meson8b clock gates seem to be:
>> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
>> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>> ? of "PERIPHS_TOP" (on Meson8b)
>> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>> ? kernel sources)
>> None of these gates is added for now, since it's unclear whether these
>> definitions are actually correct (the VCLK2_ENCT gate for example is
>> defined, but only used in some commented block).
>> 
>> The main difference between all three SoCs seem to be the video (VPU)
>> clocks. Apart from different supported clock rates (according to vpu.c
>> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
>> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
>> (probably the same as on the Meson GX SoCs) to support glitch-free
>> (clock rate) switching.
>> None of these VPU clocks are not supported by our mainline meson8b
>> clock driver yet though.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---
>
> I think you should split the binding documentation and clk changes into separate
> patches.
>
>> -
>> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---
>> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-
>
> The change being more platform than clock related, I'd prefer if Kevin or Carlo
> ack it before we apply it.

Acked-by: Kevin Hilman <khilman@baylibre.com>

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> The clock controller on Meson8, Meson8b and Meson8m2 is very similar
>> based on the code from the Amlogic GPL kernel sources. Add separate
>> compatibles for each SoC to make sure that we can easily implement
>> all the small differences for each SoC later on.
>> 
>> In general the Meson8 and Meson8m2 seem to be almost identical as they
>> even share the same mach-meson8 directory in Amlogic's GPL kernel
>> sources.
>> The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
>> because they are all using the same PLL values, 90% of the clock gates
>> are the same (the actual diffstat of the mach-meson8/clock.c and
>> mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
>> all commented out code).
>> The difference between the Meson8 and Meson8b clock gates seem to be:
>> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
>> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
>> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
>> ? of "PERIPHS_TOP" (on Meson8b)
>> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
>> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
>> ? kernel sources)
>> None of these gates is added for now, since it's unclear whether these
>> definitions are actually correct (the VCLK2_ENCT gate for example is
>> defined, but only used in some commented block).
>> 
>> The main difference between all three SoCs seem to be the video (VPU)
>> clocks. Apart from different supported clock rates (according to vpu.c
>> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
>> most notable difference is that Meson8m2 has a GP_PLL clock and a mux
>> (probably the same as on the Meson GX SoCs) to support glitch-free
>> (clock rate) switching.
>> None of these VPU clocks are not supported by our mainline meson8b
>> clock driver yet though.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>> ---
>> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---
>
> I think you should split the binding documentation and clk changes into separate
> patches.
>
>> -
>> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---
>> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-
>
> The change being more platform than clock related, I'd prefer if Kevin or Carlo
> ack it before we apply it.

Acked-by: Kevin Hilman <khilman@baylibre.com>

Re: [PATCH 2/3] arm: meson: select the clock controller for Meson8

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
>> controller driver can also be used on Meson8 SoCs now that we have a
>> separate compatible for it.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/soc with Jerome's ack.

Kevin

Re: [PATCH 2/3] arm: meson: select the clock controller for Meson8

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
>> controller driver can also be used on Meson8 SoCs now that we have a
>> separate compatible for it.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/soc with Jerome's ack.

Kevin

[PATCH 2/3] arm: meson: select the clock controller for Meson8

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
>> controller driver can also be used on Meson8 SoCs now that we have a
>> separate compatible for it.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/soc with Jerome's ack.

Kevin

[PATCH 2/3] arm: meson: select the clock controller for Meson8

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock
>> controller driver can also be used on Meson8 SoCs now that we have a
>> separate compatible for it.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/soc with Jerome's ack.

Kevin

Re: [PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> This removes the dummy clk81 gate and replaces it with the actual clock
>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>> IDs to all devices where the clock is controlled by clkc in the future.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This is going in the right direction and at least align meson8 and meson8b.
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/dt with Jerome's ack.

Kevin

Re: [PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> This removes the dummy clk81 gate and replaces it with the actual clock
>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>> IDs to all devices where the clock is controlled by clkc in the future.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This is going in the right direction and at least align meson8 and meson8b.
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/dt with Jerome's ack.

Kevin

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> This removes the dummy clk81 gate and replaces it with the actual clock
>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>> IDs to all devices where the clock is controlled by clkc in the future.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This is going in the right direction and at least align meson8 and meson8b.
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/dt with Jerome's ack.

Kevin

[PATCH 3/3] ARM: dts: meson8: add and use the real clock controller

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
>> This removes the dummy clk81 gate and replaces it with the actual clock
>> controller's CLKID_CLK81. This will also allow us to pass the real clock
>> IDs to all devices where the clock is controlled by clkc in the future.
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This is going in the right direction and at least align meson8 and meson8b.
>
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
>

Applied to v4.13/dt with Jerome's ack.

Kevin

Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote:
> Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:
> 
> > On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> > > The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> > > based on the code from the Amlogic GPL kernel sources. Add separate
> > > compatibles for each SoC to make sure that we can easily implement
> > > all the small differences for each SoC later on.
> > > 
> > > In general the Meson8 and Meson8m2 seem to be almost identical as they
> > > even share the same mach-meson8 directory in Amlogic's GPL kernel
> > > sources.
> > > The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> > > because they are all using the same PLL values, 90% of the clock gates
> > > are the same (the actual diffstat of the mach-meson8/clock.c and
> > > mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> > > all commented out code).
> > > The difference between the Meson8 and Meson8b clock gates seem to be:
> > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
> > >   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> > > - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
> > >   of "PERIPHS_TOP" (on Meson8b)
> > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
> > >   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
> > >   kernel sources)
> > > None of these gates is added for now, since it's unclear whether these
> > > definitions are actually correct (the VCLK2_ENCT gate for example is
> > > defined, but only used in some commented block).
> > > 
> > > The main difference between all three SoCs seem to be the video (VPU)
> > > clocks. Apart from different supported clock rates (according to vpu.c
> > > in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> > > most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> > > (probably the same as on the Meson GX SoCs) to support glitch-free
> > > (clock rate) switching.
> > > None of these VPU clocks are not supported by our mainline meson8b
> > > clock driver yet though.
> > > 
> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> > > ---
> > >  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11
> > > +++++++---
> > 
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> > 
> > > -
> > >  drivers/clk/meson/Kconfig                                     |  6 +++---
> > >  drivers/clk/meson/meson8b.c                                   |  5 ++++-
> > 
> > The change being more platform than clock related, I'd prefer if Kevin or
> > Carlo
> > ack it before we apply it.
> 
> Acked-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>

Applied to next/drivers with Kevin and Rob's Acks.

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Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote:
> Jerome Brunet <jbrunet@baylibre.com> writes:
> 
> > On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> > > The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> > > based on the code from the Amlogic GPL kernel sources. Add separate
> > > compatibles for each SoC to make sure that we can easily implement
> > > all the small differences for each SoC later on.
> > > 
> > > In general the Meson8 and Meson8m2 seem to be almost identical as they
> > > even share the same mach-meson8 directory in Amlogic's GPL kernel
> > > sources.
> > > The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> > > because they are all using the same PLL values, 90% of the clock gates
> > > are the same (the actual diffstat of the mach-meson8/clock.c and
> > > mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> > > all commented out code).
> > > The difference between the Meson8 and Meson8b clock gates seem to be:
> > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
> > >   CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> > > - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
> > >   of "PERIPHS_TOP" (on Meson8b)
> > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
> > >   on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
> > >   kernel sources)
> > > None of these gates is added for now, since it's unclear whether these
> > > definitions are actually correct (the VCLK2_ENCT gate for example is
> > > defined, but only used in some commented block).
> > > 
> > > The main difference between all three SoCs seem to be the video (VPU)
> > > clocks. Apart from different supported clock rates (according to vpu.c
> > > in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> > > most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> > > (probably the same as on the Meson GX SoCs) to support glitch-free
> > > (clock rate) switching.
> > > None of these VPU clocks are not supported by our mainline meson8b
> > > clock driver yet though.
> > > 
> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > > ---
> > >  .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11
> > > +++++++---
> > 
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> > 
> > > -
> > >  drivers/clk/meson/Kconfig                                     |  6 +++---
> > >  drivers/clk/meson/meson8b.c                                   |  5 ++++-
> > 
> > The change being more platform than clock related, I'd prefer if Kevin or
> > Carlo
> > ack it before we apply it.
> 
> Acked-by: Kevin Hilman <khilman@baylibre.com>

Applied to next/drivers with Kevin and Rob's Acks.

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote:
> Jerome Brunet <jbrunet@baylibre.com> writes:
> 
> > On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> > > The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> > > based on the code from the Amlogic GPL kernel sources. Add separate
> > > compatibles for each SoC to make sure that we can easily implement
> > > all the small differences for each SoC later on.
> > > 
> > > In general the Meson8 and Meson8m2 seem to be almost identical as they
> > > even share the same mach-meson8 directory in Amlogic's GPL kernel
> > > sources.
> > > The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> > > because they are all using the same PLL values, 90% of the clock gates
> > > are the same (the actual diffstat of the mach-meson8/clock.c and
> > > mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> > > all commented out code).
> > > The difference between the Meson8 and Meson8b clock gates seem to be:
> > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
> > > ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> > > - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
> > > ? of "PERIPHS_TOP" (on Meson8b)
> > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
> > > ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
> > > ? kernel sources)
> > > None of these gates is added for now, since it's unclear whether these
> > > definitions are actually correct (the VCLK2_ENCT gate for example is
> > > defined, but only used in some commented block).
> > > 
> > > The main difference between all three SoCs seem to be the video (VPU)
> > > clocks. Apart from different supported clock rates (according to vpu.c
> > > in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> > > most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> > > (probably the same as on the Meson GX SoCs) to support glitch-free
> > > (clock rate) switching.
> > > None of these VPU clocks are not supported by our mainline meson8b
> > > clock driver yet though.
> > > 
> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > > ---
> > > ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11
> > > +++++++---
> > 
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> > 
> > > -
> > > ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---
> > > ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-
> > 
> > The change being more platform than clock related, I'd prefer if Kevin or
> > Carlo
> > ack it before we apply it.
> 
> Acked-by: Kevin Hilman <khilman@baylibre.com>

Applied to next/drivers with Kevin and Rob's Acks.

[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

[Jerome Brunet]

On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote:
> Jerome Brunet <jbrunet@baylibre.com> writes:
> 
> > On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:
> > > The clock controller on Meson8, Meson8b and Meson8m2 is very similar
> > > based on the code from the Amlogic GPL kernel sources. Add separate
> > > compatibles for each SoC to make sure that we can easily implement
> > > all the small differences for each SoC later on.
> > > 
> > > In general the Meson8 and Meson8m2 seem to be almost identical as they
> > > even share the same mach-meson8 directory in Amlogic's GPL kernel
> > > sources.
> > > The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
> > > because they are all using the same PLL values, 90% of the clock gates
> > > are the same (the actual diffstat of the mach-meson8/clock.c and
> > > mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
> > > all commented out code).
> > > The difference between the Meson8 and Meson8b clock gates seem to be:
> > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
> > > ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
> > > - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
> > > ? of "PERIPHS_TOP" (on Meson8b)
> > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
> > > ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
> > > ? kernel sources)
> > > None of these gates is added for now, since it's unclear whether these
> > > definitions are actually correct (the VCLK2_ENCT gate for example is
> > > defined, but only used in some commented block).
> > > 
> > > The main difference between all three SoCs seem to be the video (VPU)
> > > clocks. Apart from different supported clock rates (according to vpu.c
> > > in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
> > > most notable difference is that Meson8m2 has a GP_PLL clock and a mux
> > > (probably the same as on the Meson GX SoCs) to support glitch-free
> > > (clock rate) switching.
> > > None of these VPU clocks are not supported by our mainline meson8b
> > > clock driver yet though.
> > > 
> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > > ---
> > > ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11
> > > +++++++---
> > 
> > I think you should split the binding documentation and clk changes into
> > separate
> > patches.
> > 
> > > -
> > > ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---
> > > ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-
> > 
> > The change being more platform than clock related, I'd prefer if Kevin or
> > Carlo
> > ack it before we apply it.
> 
> Acked-by: Kevin Hilman <khilman@baylibre.com>

Applied to next/drivers with Kevin and Rob's Acks.