* [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability()
2017-06-02 7:54 [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Mao Zhongyi
@ 2017-06-02 7:54 ` Mao Zhongyi
2017-06-06 15:26 ` Michael S. Tsirkin
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 2/6] pci: Add comment for pci_add_capability2() Mao Zhongyi
` (5 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-02 7:54 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel, armbru
On success, pci_add_capability2() returns a positive value. On
failure, it sets an error and return a negative value.
pci_add_capability() laboriously checks this behavior. No other
caller does. Drop the checks from pci_add_capability().
Cc: mst@redhat.com
Cc: marcel@redhat.com
Cc: armbru@redhat.com
Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/pci/pci.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 98ccc27..53566b8 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2270,12 +2270,8 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
Error *local_err = NULL;
ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
- if (local_err) {
- assert(ret < 0);
+ if (ret < 0) {
error_report_err(local_err);
- } else {
- /* success implies a positive offset in config space */
- assert(ret > 0);
}
return ret;
}
--
2.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability()
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability() Mao Zhongyi
@ 2017-06-06 15:26 ` Michael S. Tsirkin
2017-06-06 16:14 ` Markus Armbruster
0 siblings, 1 reply; 19+ messages in thread
From: Michael S. Tsirkin @ 2017-06-06 15:26 UTC (permalink / raw)
To: Mao Zhongyi; +Cc: qemu-devel, marcel, armbru
On Fri, Jun 02, 2017 at 03:54:37PM +0800, Mao Zhongyi wrote:
> On success, pci_add_capability2() returns a positive value. On
> failure, it sets an error and return a negative value.
>
> pci_add_capability() laboriously checks this behavior. No other
> caller does. Drop the checks from pci_add_capability().
>
> Cc: mst@redhat.com
> Cc: marcel@redhat.com
> Cc: armbru@redhat.com
> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
> ---
> hw/pci/pci.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index 98ccc27..53566b8 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -2270,12 +2270,8 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
> Error *local_err = NULL;
>
> ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
> - if (local_err) {
> - assert(ret < 0);
> + if (ret < 0) {
> error_report_err(local_err);
> - } else {
> - /* success implies a positive offset in config space */
> - assert(ret > 0);
> }
> return ret;
> }
I don't see why this is a good idea. You drop a bunch of
asserts, so naturally code is slightly tighter. We could gain
the same by building with NDEBUG but we don't, we rather
have more safety.
> --
> 2.9.3
>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability()
2017-06-06 15:26 ` Michael S. Tsirkin
@ 2017-06-06 16:14 ` Markus Armbruster
2017-06-06 18:06 ` Michael S. Tsirkin
0 siblings, 1 reply; 19+ messages in thread
From: Markus Armbruster @ 2017-06-06 16:14 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Mao Zhongyi, marcel, qemu-devel
"Michael S. Tsirkin" <mst@redhat.com> writes:
> On Fri, Jun 02, 2017 at 03:54:37PM +0800, Mao Zhongyi wrote:
>> On success, pci_add_capability2() returns a positive value. On
>> failure, it sets an error and return a negative value.
>>
>> pci_add_capability() laboriously checks this behavior. No other
>> caller does. Drop the checks from pci_add_capability().
>>
>> Cc: mst@redhat.com
>> Cc: marcel@redhat.com
>> Cc: armbru@redhat.com
>> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
>> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
>> ---
>> hw/pci/pci.c | 6 +-----
>> 1 file changed, 1 insertion(+), 5 deletions(-)
>>
>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
>> index 98ccc27..53566b8 100644
>> --- a/hw/pci/pci.c
>> +++ b/hw/pci/pci.c
>> @@ -2270,12 +2270,8 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
>> Error *local_err = NULL;
>>
>> ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
>> - if (local_err) {
>> - assert(ret < 0);
>> + if (ret < 0) {
>> error_report_err(local_err);
>> - } else {
>> - /* success implies a positive offset in config space */
>> - assert(ret > 0);
>> }
>> return ret;
>> }
>
>
> I don't see why this is a good idea. You drop a bunch of
> asserts, so naturally code is slightly tighter. We could gain
> the same by building with NDEBUG but we don't, we rather
> have more safety.
It's a good idea because it's what we do basically everywhere when a
function sets an error and returns a distinct error value.
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability()
2017-06-06 16:14 ` Markus Armbruster
@ 2017-06-06 18:06 ` Michael S. Tsirkin
2017-06-06 18:53 ` Markus Armbruster
0 siblings, 1 reply; 19+ messages in thread
From: Michael S. Tsirkin @ 2017-06-06 18:06 UTC (permalink / raw)
To: Markus Armbruster; +Cc: Mao Zhongyi, marcel, qemu-devel
On Tue, Jun 06, 2017 at 06:14:02PM +0200, Markus Armbruster wrote:
> "Michael S. Tsirkin" <mst@redhat.com> writes:
>
> > On Fri, Jun 02, 2017 at 03:54:37PM +0800, Mao Zhongyi wrote:
> >> On success, pci_add_capability2() returns a positive value. On
> >> failure, it sets an error and return a negative value.
> >>
> >> pci_add_capability() laboriously checks this behavior. No other
> >> caller does. Drop the checks from pci_add_capability().
> >>
> >> Cc: mst@redhat.com
> >> Cc: marcel@redhat.com
> >> Cc: armbru@redhat.com
> >> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
> >> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
> >> ---
> >> hw/pci/pci.c | 6 +-----
> >> 1 file changed, 1 insertion(+), 5 deletions(-)
> >>
> >> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> >> index 98ccc27..53566b8 100644
> >> --- a/hw/pci/pci.c
> >> +++ b/hw/pci/pci.c
> >> @@ -2270,12 +2270,8 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
> >> Error *local_err = NULL;
> >>
> >> ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
> >> - if (local_err) {
> >> - assert(ret < 0);
> >> + if (ret < 0) {
> >> error_report_err(local_err);
> >> - } else {
> >> - /* success implies a positive offset in config space */
> >> - assert(ret > 0);
> >> }
> >> return ret;
> >> }
> >
> >
> > I don't see why this is a good idea. You drop a bunch of
> > asserts, so naturally code is slightly tighter. We could gain
> > the same by building with NDEBUG but we don't, we rather
> > have more safety.
>
> It's a good idea because it's what we do basically everywhere when a
> function sets an error and returns a distinct error value.
We typically just do
if (local_err) {
error_report_err(local_err);
...
}
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability()
2017-06-06 18:06 ` Michael S. Tsirkin
@ 2017-06-06 18:53 ` Markus Armbruster
0 siblings, 0 replies; 19+ messages in thread
From: Markus Armbruster @ 2017-06-06 18:53 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: marcel, Mao Zhongyi, qemu-devel
"Michael S. Tsirkin" <mst@redhat.com> writes:
> On Tue, Jun 06, 2017 at 06:14:02PM +0200, Markus Armbruster wrote:
>> "Michael S. Tsirkin" <mst@redhat.com> writes:
>>
>> > On Fri, Jun 02, 2017 at 03:54:37PM +0800, Mao Zhongyi wrote:
>> >> On success, pci_add_capability2() returns a positive value. On
>> >> failure, it sets an error and return a negative value.
>> >>
>> >> pci_add_capability() laboriously checks this behavior. No other
>> >> caller does. Drop the checks from pci_add_capability().
>> >>
>> >> Cc: mst@redhat.com
>> >> Cc: marcel@redhat.com
>> >> Cc: armbru@redhat.com
>> >> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
>> >> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
>> >> ---
>> >> hw/pci/pci.c | 6 +-----
>> >> 1 file changed, 1 insertion(+), 5 deletions(-)
>> >>
>> >> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
>> >> index 98ccc27..53566b8 100644
>> >> --- a/hw/pci/pci.c
>> >> +++ b/hw/pci/pci.c
>> >> @@ -2270,12 +2270,8 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
>> >> Error *local_err = NULL;
>> >>
>> >> ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
>> >> - if (local_err) {
>> >> - assert(ret < 0);
>> >> + if (ret < 0) {
>> >> error_report_err(local_err);
>> >> - } else {
>> >> - /* success implies a positive offset in config space */
>> >> - assert(ret > 0);
>> >> }
>> >> return ret;
>> >> }
>> >
>> >
>> > I don't see why this is a good idea. You drop a bunch of
>> > asserts, so naturally code is slightly tighter. We could gain
>> > the same by building with NDEBUG but we don't, we rather
>> > have more safety.
>>
>> It's a good idea because it's what we do basically everywhere when a
>> function sets an error and returns a distinct error value.
>
> We typically just do
>
func(arg1, arg2, &local_err);
> if (local_err) {
> error_report_err(local_err);
> ...
> }
That one's fine.
Equally fine:
ret = func(arg1, arg2, &local_err);
if (ret < 0) {
error_report_err(local_err);
...
}
When func(...) is short, then
if (func(arg1, arg2, &local_err) < 0) {
error_report_err(local_err);
...
}
is also fine.
Whether you check the Error * variable or a distinct error return value
is purely a matter of taste (I prefer return value when possible).
Keeping matters of taste locally consistent can make sense.
What matters is keeping the error checking short and to the point.
Asserting that the callee returns the distinct error value if and only
if it sets an error is unusual precisely because it's not worth the
distraction. Mao Zhongyi's patch cleans it up here.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 2/6] pci: Add comment for pci_add_capability2()
2017-06-02 7:54 [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Mao Zhongyi
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability() Mao Zhongyi
@ 2017-06-02 7:54 ` Mao Zhongyi
2017-06-05 13:34 ` Marcel Apfelbaum
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 3/6] pci: Fix the wrong return value judgment condition Mao Zhongyi
` (4 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-02 7:54 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel, armbru
Add a comment for pci_add_capability2() to explain the return
value. This may help to make a correct return value check for
its callers.
Cc: mst@redhat.com
Cc: marcel@redhat.com
Cc: armbru@redhat.com
Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
---
hw/pci/pci.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 53566b8..9810d5f 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2276,6 +2276,10 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
return ret;
}
+/*
+ * On success, pci_add_capability2() returns a positive value.
+ * On failure, it sets an error and returns a negative value.
+ */
int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
uint8_t offset, uint8_t size,
Error **errp)
--
2.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/6] pci: Add comment for pci_add_capability2()
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 2/6] pci: Add comment for pci_add_capability2() Mao Zhongyi
@ 2017-06-05 13:34 ` Marcel Apfelbaum
2017-06-06 1:34 ` Mao Zhongyi
0 siblings, 1 reply; 19+ messages in thread
From: Marcel Apfelbaum @ 2017-06-05 13:34 UTC (permalink / raw)
To: Mao Zhongyi, qemu-devel; +Cc: mst, armbru
On 02/06/2017 10:54, Mao Zhongyi wrote:
> Add a comment for pci_add_capability2() to explain the return
> value. This may help to make a correct return value check for
> its callers.
>
> Cc: mst@redhat.com
> Cc: marcel@redhat.com
> Cc: armbru@redhat.com
> Suggested-by: Markus Armbruster <armbru@redhat.com>
> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
> ---
> hw/pci/pci.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index 53566b8..9810d5f 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -2276,6 +2276,10 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
> return ret;
> }
>
> +/*
> + * On success, pci_add_capability2() returns a positive value.
Hi,
I would specify what is the return value: the offset of the pci capability.
Thanks,
Marcel
> + * On failure, it sets an error and returns a negative value.
> + */
> int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
> uint8_t offset, uint8_t size,
> Error **errp)
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/6] pci: Add comment for pci_add_capability2()
2017-06-05 13:34 ` Marcel Apfelbaum
@ 2017-06-06 1:34 ` Mao Zhongyi
0 siblings, 0 replies; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-06 1:34 UTC (permalink / raw)
To: Marcel Apfelbaum, qemu-devel; +Cc: mst, armbru
Hi, Marcel
On 06/05/2017 09:34 PM, Marcel Apfelbaum wrote:
> On 02/06/2017 10:54, Mao Zhongyi wrote:
>> Add a comment for pci_add_capability2() to explain the return
>> value. This may help to make a correct return value check for
>> its callers.
>>
>> Cc: mst@redhat.com
>> Cc: marcel@redhat.com
>> Cc: armbru@redhat.com
>> Suggested-by: Markus Armbruster <armbru@redhat.com>
>> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
>> ---
>> hw/pci/pci.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
>> index 53566b8..9810d5f 100644
>> --- a/hw/pci/pci.c
>> +++ b/hw/pci/pci.c
>> @@ -2276,6 +2276,10 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
>> return ret;
>> }
>> +/*
>> + * On success, pci_add_capability2() returns a positive value.
>
> Hi,
> I would specify what is the return value: the offset of the pci capability.
>
> Thanks,
> Marcel
>
Thanks, I will.
Mao
>> + * On failure, it sets an error and returns a negative value.
>> + */
>> int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
>> uint8_t offset, uint8_t size,
>> Error **errp)
>>
>
>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 3/6] pci: Fix the wrong return value judgment condition
2017-06-02 7:54 [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Mao Zhongyi
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 1/6] pci: Clean up error checking in pci_add_capability() Mao Zhongyi
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 2/6] pci: Add comment for pci_add_capability2() Mao Zhongyi
@ 2017-06-02 7:54 ` Mao Zhongyi
2017-06-05 16:20 ` Marcel Apfelbaum
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 4/6] net/eepro100: Fixed code style Mao Zhongyi
` (3 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-02 7:54 UTC (permalink / raw)
To: qemu-devel; +Cc: dmitry, jasowang, alex.williamson, marcel, mst, armbru
On success, pci_add_capability2() returns a positive value. On
failure, it sets an error and return a negative value. It doesn't
always return 0. So the judgment condtion of pci_add_capability2()
is wrong if it contains the situation where return value equal to
0. Fix the error checks from its callers.
Cc: dmitry@daynix.com
Cc: jasowang@redhat.com
Cc: alex.williamson@redhat.com
Cc: marcel@redhat.com
Cc: mst@redhat.com
Cc: armbru@redhat.com
Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
---
hw/net/e1000e.c | 2 +-
hw/net/eepro100.c | 2 +-
hw/vfio/pci.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
index 6e23493..8259d67 100644
--- a/hw/net/e1000e.c
+++ b/hw/net/e1000e.c
@@ -374,7 +374,7 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
{
int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF);
- if (ret >= 0) {
+ if (ret > 0) {
pci_set_word(pdev->config + offset + PCI_PM_PMC,
PCI_PM_CAP_VER_1_1 |
pmc);
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
index 4bf71f2..da36816 100644
--- a/hw/net/eepro100.c
+++ b/hw/net/eepro100.c
@@ -571,7 +571,7 @@ static void e100_pci_reset(EEPRO100State * s)
int cfg_offset = 0xdc;
int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
cfg_offset, PCI_PM_SIZEOF);
- assert(r >= 0);
+ assert(r > 0);
pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
#if 0 /* TODO: replace dummy code for power management emulation. */
/* TODO: Power Management Control / Status. */
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 32aca77..5881968 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -1744,7 +1744,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
}
pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size);
- if (pos >= 0) {
+ if (pos > 0) {
vdev->pdev.exp.exp_cap = pos;
}
--
2.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/6] pci: Fix the wrong return value judgment condition
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 3/6] pci: Fix the wrong return value judgment condition Mao Zhongyi
@ 2017-06-05 16:20 ` Marcel Apfelbaum
2017-06-06 1:14 ` Mao Zhongyi
0 siblings, 1 reply; 19+ messages in thread
From: Marcel Apfelbaum @ 2017-06-05 16:20 UTC (permalink / raw)
To: Mao Zhongyi, qemu-devel; +Cc: dmitry, jasowang, alex.williamson, mst, armbru
On 02/06/2017 10:54, Mao Zhongyi wrote:
> On success, pci_add_capability2() returns a positive value. On
> failure, it sets an error and return a negative value. It doesn't
> always return 0. So the judgment condtion of pci_add_capability2()
> is wrong if it contains the situation where return value equal to
> 0. Fix the error checks from its callers.
>
Hi,
I would suggest changing the above to a simpler:
pci_add_capability returns a strictly positive value on success,
correct asserts.
Thanks,
Marcel
> Cc: dmitry@daynix.com
> Cc: jasowang@redhat.com
> Cc: alex.williamson@redhat.com
> Cc: marcel@redhat.com
> Cc: mst@redhat.com
> Cc: armbru@redhat.com
> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
> ---
> hw/net/e1000e.c | 2 +-
> hw/net/eepro100.c | 2 +-
> hw/vfio/pci.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
> index 6e23493..8259d67 100644
> --- a/hw/net/e1000e.c
> +++ b/hw/net/e1000e.c
> @@ -374,7 +374,7 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
> {
> int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF);
>
> - if (ret >= 0) {
> + if (ret > 0) {
> pci_set_word(pdev->config + offset + PCI_PM_PMC,
> PCI_PM_CAP_VER_1_1 |
> pmc);
> diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
> index 4bf71f2..da36816 100644
> --- a/hw/net/eepro100.c
> +++ b/hw/net/eepro100.c
> @@ -571,7 +571,7 @@ static void e100_pci_reset(EEPRO100State * s)
> int cfg_offset = 0xdc;
> int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
> cfg_offset, PCI_PM_SIZEOF);
> - assert(r >= 0);
> + assert(r > 0);
> pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
> #if 0 /* TODO: replace dummy code for power management emulation. */
> /* TODO: Power Management Control / Status. */
> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
> index 32aca77..5881968 100644
> --- a/hw/vfio/pci.c
> +++ b/hw/vfio/pci.c
> @@ -1744,7 +1744,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
> }
>
> pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size);
> - if (pos >= 0) {
> + if (pos > 0) {
> vdev->pdev.exp.exp_cap = pos;
> }
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/6] pci: Fix the wrong return value judgment condition
2017-06-05 16:20 ` Marcel Apfelbaum
@ 2017-06-06 1:14 ` Mao Zhongyi
0 siblings, 0 replies; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-06 1:14 UTC (permalink / raw)
To: Marcel Apfelbaum, qemu-devel
Cc: dmitry, jasowang, alex.williamson, mst, armbru
Hi, Marcel
On 06/06/2017 12:20 AM, Marcel Apfelbaum wrote:
> On 02/06/2017 10:54, Mao Zhongyi wrote:
>> On success, pci_add_capability2() returns a positive value. On
>> failure, it sets an error and return a negative value. It doesn't
>> always return 0. So the judgment condtion of pci_add_capability2()
>> is wrong if it contains the situation where return value equal to
>> 0. Fix the error checks from its callers.
>>
>
> Hi,
> I would suggest changing the above to a simpler:
>
> pci_add_capability returns a strictly positive value on success,
> correct asserts.
>
> Thanks,
> Marcel
OK, I see.
Thanks a lot.
Mao
>
>> Cc: dmitry@daynix.com
>> Cc: jasowang@redhat.com
>> Cc: alex.williamson@redhat.com
>> Cc: marcel@redhat.com
>> Cc: mst@redhat.com
>> Cc: armbru@redhat.com
>> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
>> ---
>> hw/net/e1000e.c | 2 +-
>> hw/net/eepro100.c | 2 +-
>> hw/vfio/pci.c | 2 +-
>> 3 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
>> index 6e23493..8259d67 100644
>> --- a/hw/net/e1000e.c
>> +++ b/hw/net/e1000e.c
>> @@ -374,7 +374,7 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
>> {
>> int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF);
>> - if (ret >= 0) {
>> + if (ret > 0) {
>> pci_set_word(pdev->config + offset + PCI_PM_PMC,
>> PCI_PM_CAP_VER_1_1 |
>> pmc);
>> diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
>> index 4bf71f2..da36816 100644
>> --- a/hw/net/eepro100.c
>> +++ b/hw/net/eepro100.c
>> @@ -571,7 +571,7 @@ static void e100_pci_reset(EEPRO100State * s)
>> int cfg_offset = 0xdc;
>> int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
>> cfg_offset, PCI_PM_SIZEOF);
>> - assert(r >= 0);
>> + assert(r > 0);
>> pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
>> #if 0 /* TODO: replace dummy code for power management emulation. */
>> /* TODO: Power Management Control / Status. */
>> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
>> index 32aca77..5881968 100644
>> --- a/hw/vfio/pci.c
>> +++ b/hw/vfio/pci.c
>> @@ -1744,7 +1744,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
>> }
>> pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size);
>> - if (pos >= 0) {
>> + if (pos > 0) {
>> vdev->pdev.exp.exp_cap = pos;
>> }
>>
>
>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 4/6] net/eepro100: Fixed code style
2017-06-02 7:54 [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Mao Zhongyi
` (2 preceding siblings ...)
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 3/6] pci: Fix the wrong return value judgment condition Mao Zhongyi
@ 2017-06-02 7:54 ` Mao Zhongyi
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 5/6] pci: Make errp the last parameter of pci_add_capability() Mao Zhongyi
` (2 subsequent siblings)
6 siblings, 0 replies; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-02 7:54 UTC (permalink / raw)
To: qemu-devel; +Cc: jasowang, armbru
It reports a code style problem(ERROR: "foo * bar" should be "foo *bar")
when running checkpatch.pl. So fix it to conform to the coding standards.
Cc: jasowang@redhat.com
Cc: armbru@redhat.com
Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
---
hw/net/eepro100.c | 62 +++++++++++++++++++++++++++----------------------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
index da36816..62e989c 100644
--- a/hw/net/eepro100.c
+++ b/hw/net/eepro100.c
@@ -405,7 +405,7 @@ enum scb_stat_ack {
stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
};
-static void disable_interrupt(EEPRO100State * s)
+static void disable_interrupt(EEPRO100State *s)
{
if (s->int_stat) {
TRACE(INT, logout("interrupt disabled\n"));
@@ -414,7 +414,7 @@ static void disable_interrupt(EEPRO100State * s)
}
}
-static void enable_interrupt(EEPRO100State * s)
+static void enable_interrupt(EEPRO100State *s)
{
if (!s->int_stat) {
TRACE(INT, logout("interrupt enabled\n"));
@@ -423,7 +423,7 @@ static void enable_interrupt(EEPRO100State * s)
}
}
-static void eepro100_acknowledge(EEPRO100State * s)
+static void eepro100_acknowledge(EEPRO100State *s)
{
s->scb_stat &= ~s->mem[SCBAck];
s->mem[SCBAck] = s->scb_stat;
@@ -432,7 +432,7 @@ static void eepro100_acknowledge(EEPRO100State * s)
}
}
-static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
+static void eepro100_interrupt(EEPRO100State *s, uint8_t status)
{
uint8_t mask = ~s->mem[SCBIntmask];
s->mem[SCBAck] |= status;
@@ -449,52 +449,52 @@ static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
}
}
-static void eepro100_cx_interrupt(EEPRO100State * s)
+static void eepro100_cx_interrupt(EEPRO100State *s)
{
/* CU completed action command. */
/* Transmit not ok (82557 only, not in emulation). */
eepro100_interrupt(s, 0x80);
}
-static void eepro100_cna_interrupt(EEPRO100State * s)
+static void eepro100_cna_interrupt(EEPRO100State *s)
{
/* CU left the active state. */
eepro100_interrupt(s, 0x20);
}
-static void eepro100_fr_interrupt(EEPRO100State * s)
+static void eepro100_fr_interrupt(EEPRO100State *s)
{
/* RU received a complete frame. */
eepro100_interrupt(s, 0x40);
}
-static void eepro100_rnr_interrupt(EEPRO100State * s)
+static void eepro100_rnr_interrupt(EEPRO100State *s)
{
/* RU is not ready. */
eepro100_interrupt(s, 0x10);
}
-static void eepro100_mdi_interrupt(EEPRO100State * s)
+static void eepro100_mdi_interrupt(EEPRO100State *s)
{
/* MDI completed read or write cycle. */
eepro100_interrupt(s, 0x08);
}
-static void eepro100_swi_interrupt(EEPRO100State * s)
+static void eepro100_swi_interrupt(EEPRO100State *s)
{
/* Software has requested an interrupt. */
eepro100_interrupt(s, 0x04);
}
#if 0
-static void eepro100_fcp_interrupt(EEPRO100State * s)
+static void eepro100_fcp_interrupt(EEPRO100State *s)
{
/* Flow control pause interrupt (82558 and later). */
eepro100_interrupt(s, 0x01);
}
#endif
-static void e100_pci_reset(EEPRO100State * s)
+static void e100_pci_reset(EEPRO100State *s)
{
E100PCIDeviceInfo *info = eepro100_get_class(s);
uint32_t device = s->device;
@@ -598,7 +598,7 @@ static void e100_pci_reset(EEPRO100State * s)
#endif /* EEPROM_SIZE > 0 */
}
-static void nic_selective_reset(EEPRO100State * s)
+static void nic_selective_reset(EEPRO100State *s)
{
size_t i;
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
@@ -669,7 +669,7 @@ static char *regname(uint32_t addr)
****************************************************************************/
#if 0
-static uint16_t eepro100_read_command(EEPRO100State * s)
+static uint16_t eepro100_read_command(EEPRO100State *s)
{
uint16_t val = 0xffff;
TRACE(OTHER, logout("val=0x%04x\n", val));
@@ -694,27 +694,27 @@ enum commands {
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
};
-static cu_state_t get_cu_state(EEPRO100State * s)
+static cu_state_t get_cu_state(EEPRO100State *s)
{
return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
}
-static void set_cu_state(EEPRO100State * s, cu_state_t state)
+static void set_cu_state(EEPRO100State *s, cu_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
}
-static ru_state_t get_ru_state(EEPRO100State * s)
+static ru_state_t get_ru_state(EEPRO100State *s)
{
return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
}
-static void set_ru_state(EEPRO100State * s, ru_state_t state)
+static void set_ru_state(EEPRO100State *s, ru_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
}
-static void dump_statistics(EEPRO100State * s)
+static void dump_statistics(EEPRO100State *s)
{
/* Dump statistical data. Most data is never changed by the emulation
* and always 0, so we first just copy the whole block and then those
@@ -962,7 +962,7 @@ static void action_command(EEPRO100State *s)
/* List is empty. Now CU is idle or suspended. */
}
-static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
+static void eepro100_cu_command(EEPRO100State *s, uint8_t val)
{
cu_state_t cu_state;
switch (val) {
@@ -1036,7 +1036,7 @@ static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
}
}
-static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
+static void eepro100_ru_command(EEPRO100State *s, uint8_t val)
{
switch (val) {
case RU_NOP:
@@ -1084,7 +1084,7 @@ static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
}
}
-static void eepro100_write_command(EEPRO100State * s, uint8_t val)
+static void eepro100_write_command(EEPRO100State *s, uint8_t val)
{
eepro100_ru_command(s, val & 0x0f);
eepro100_cu_command(s, val & 0xf0);
@@ -1106,7 +1106,7 @@ static void eepro100_write_command(EEPRO100State * s, uint8_t val)
#define EEPROM_DI 0x04
#define EEPROM_DO 0x08
-static uint16_t eepro100_read_eeprom(EEPRO100State * s)
+static uint16_t eepro100_read_eeprom(EEPRO100State *s)
{
uint16_t val = e100_read_reg2(s, SCBeeprom);
if (eeprom93xx_read(s->eeprom)) {
@@ -1170,7 +1170,7 @@ static const char *reg2name(uint8_t reg)
}
#endif /* DEBUG_EEPRO100 */
-static uint32_t eepro100_read_mdi(EEPRO100State * s)
+static uint32_t eepro100_read_mdi(EEPRO100State *s)
{
uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
@@ -1302,7 +1302,7 @@ typedef struct {
uint32_t st_result; /* Self Test Results */
} eepro100_selftest_t;
-static uint32_t eepro100_read_port(EEPRO100State * s)
+static uint32_t eepro100_read_port(EEPRO100State *s)
{
return 0;
}
@@ -1340,7 +1340,7 @@ static void eepro100_write_port(EEPRO100State *s)
*
****************************************************************************/
-static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
+static uint8_t eepro100_read1(EEPRO100State *s, uint32_t addr)
{
uint8_t val = 0;
if (addr <= sizeof(s->mem) - sizeof(val)) {
@@ -1393,7 +1393,7 @@ static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
return val;
}
-static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
+static uint16_t eepro100_read2(EEPRO100State *s, uint32_t addr)
{
uint16_t val = 0;
if (addr <= sizeof(s->mem) - sizeof(val)) {
@@ -1421,7 +1421,7 @@ static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
return val;
}
-static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
+static uint32_t eepro100_read4(EEPRO100State *s, uint32_t addr)
{
uint32_t val = 0;
if (addr <= sizeof(s->mem) - sizeof(val)) {
@@ -1453,7 +1453,7 @@ static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
return val;
}
-static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
+static void eepro100_write1(EEPRO100State *s, uint32_t addr, uint8_t val)
{
/* SCBStatus is readonly. */
if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
@@ -1519,7 +1519,7 @@ static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
}
}
-static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
+static void eepro100_write2(EEPRO100State *s, uint32_t addr, uint16_t val)
{
/* SCBStatus is readonly. */
if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
@@ -1565,7 +1565,7 @@ static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
}
}
-static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
+static void eepro100_write4(EEPRO100State *s, uint32_t addr, uint32_t val)
{
if (addr <= sizeof(s->mem) - sizeof(val)) {
e100_write_reg4(s, addr, val);
--
2.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PATCH v2 5/6] pci: Make errp the last parameter of pci_add_capability()
2017-06-02 7:54 [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Mao Zhongyi
` (3 preceding siblings ...)
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 4/6] net/eepro100: Fixed code style Mao Zhongyi
@ 2017-06-02 7:54 ` Mao Zhongyi
2017-06-02 17:45 ` Eduardo Habkost
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 6/6] pci: Convert to realize Mao Zhongyi
2017-06-06 15:23 ` [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Michael S. Tsirkin
6 siblings, 1 reply; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-02 7:54 UTC (permalink / raw)
To: qemu-devel
Cc: mst, pbonzini, rth, ehabkost, dmitry, jasowang, marcel,
alex.williamson, armbru
Add Error argument for pci_add_capability() to leverage the errp
to pass info on errors. This way is helpful for its callers to
make a better error handling when moving to 'realize'.
Cc: mst@redhat.com
Cc: pbonzini@redhat.com
Cc: rth@twiddle.net
Cc: ehabkost@redhat.com
Cc: dmitry@daynix.com
Cc: jasowang@redhat.com
Cc: marcel@redhat.com
Cc: alex.williamson@redhat.com
Cc: armbru@redhat.com
Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
---
hw/i386/amd_iommu.c | 24 +++++++++++++++++-------
hw/net/e1000e.c | 7 ++++++-
hw/net/eepro100.c | 17 ++++++++++++-----
hw/pci-bridge/i82801b11.c | 1 +
hw/pci/pci.c | 10 ++++------
hw/pci/pci_bridge.c | 7 ++++++-
hw/pci/pcie.c | 10 ++++++++--
hw/pci/shpc.c | 5 ++++-
hw/pci/slotid_cap.c | 7 ++++++-
hw/vfio/pci.c | 3 ++-
hw/virtio/virtio-pci.c | 19 ++++++++++++++-----
include/hw/pci/pci.h | 3 ++-
12 files changed, 82 insertions(+), 31 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 7b6d4ea..d93ffc2 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -1158,13 +1158,23 @@ static void amdvi_realize(DeviceState *dev, Error **err)
x86_iommu->type = TYPE_AMD;
qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus);
object_property_set_bool(OBJECT(&s->pci), true, "realized", err);
- s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,
- AMDVI_CAPAB_SIZE);
- assert(s->capab_offset > 0);
- ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE);
- assert(ret > 0);
- ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE);
- assert(ret > 0);
+ ret = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,
+ AMDVI_CAPAB_SIZE, err);
+ if (ret < 0) {
+ return;
+ }
+ s->capab_offset = ret;
+
+ ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0,
+ AMDVI_CAPAB_REG_SIZE, err);
+ if (ret < 0) {
+ return;
+ }
+ ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0,
+ AMDVI_CAPAB_REG_SIZE, err);
+ if (ret < 0) {
+ return;
+ }
/* set up MMIO */
memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",
diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
index 8259d67..41430766 100644
--- a/hw/net/e1000e.c
+++ b/hw/net/e1000e.c
@@ -47,6 +47,7 @@
#include "e1000e_core.h"
#include "trace.h"
+#include "qapi/error.h"
#define TYPE_E1000E "e1000e"
#define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
@@ -372,7 +373,9 @@ e1000e_gen_dsn(uint8_t *mac)
static int
e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
{
- int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF);
+ Error *local_err = NULL;
+ int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
+ PCI_PM_SIZEOF, &local_err);
if (ret > 0) {
pci_set_word(pdev->config + offset + PCI_PM_PMC,
@@ -386,6 +389,8 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
PCI_PM_CTRL_PME_STATUS);
+ } else {
+ error_report_err(local_err);
}
return ret;
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
index 62e989c..f24046a 100644
--- a/hw/net/eepro100.c
+++ b/hw/net/eepro100.c
@@ -494,7 +494,7 @@ static void eepro100_fcp_interrupt(EEPRO100State *s)
}
#endif
-static void e100_pci_reset(EEPRO100State *s)
+static void e100_pci_reset(EEPRO100State *s, Error **errp)
{
E100PCIDeviceInfo *info = eepro100_get_class(s);
uint32_t device = s->device;
@@ -570,9 +570,13 @@ static void e100_pci_reset(EEPRO100State *s)
/* Power Management Capabilities */
int cfg_offset = 0xdc;
int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
- cfg_offset, PCI_PM_SIZEOF);
- assert(r > 0);
- pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
+ cfg_offset, PCI_PM_SIZEOF,
+ errp);
+ if (r > 0) {
+ pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
+ } else {
+ return;
+ }
#if 0 /* TODO: replace dummy code for power management emulation. */
/* TODO: Power Management Control / Status. */
pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
@@ -1863,7 +1867,10 @@ static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
s->device = info->device;
- e100_pci_reset(s);
+ e100_pci_reset(s, errp);
+ if (errp && *errp) {
+ return;
+ }
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
* i82559 and later support 64 or 256 word EEPROM. */
diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
index 2404e7e..2c065c3 100644
--- a/hw/pci-bridge/i82801b11.c
+++ b/hw/pci-bridge/i82801b11.c
@@ -44,6 +44,7 @@
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/i386/ich9.h"
+#include "qapi/error.h"
/*****************************************************************************/
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 9810d5f..1cfeeba 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2264,15 +2264,13 @@ static void pci_del_option_rom(PCIDevice *pdev)
* in pci config space
*/
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
- uint8_t offset, uint8_t size)
+ uint8_t offset, uint8_t size,
+ Error **errp)
{
int ret;
- Error *local_err = NULL;
- ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
- if (ret < 0) {
- error_report_err(local_err);
- }
+ ret = pci_add_capability2(pdev, cap_id, offset, size, errp);
+
return ret;
}
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 5118ef4..bb0f3a3 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -33,6 +33,7 @@
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "qemu/range.h"
+#include "qapi/error.h"
/* PCI bridge subsystem vendor ID helper functions */
#define PCI_SSVID_SIZEOF 8
@@ -43,8 +44,12 @@ int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
uint16_t svid, uint16_t ssid)
{
int pos;
- pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF);
+ Error *local_err = NULL;
+
+ pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
+ PCI_SSVID_SIZEOF, &local_err);
if (pos < 0) {
+ error_report_err(local_err);
return pos;
}
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 18e634f..f187512 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -91,11 +91,14 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
/* PCIe cap v2 init */
int pos;
uint8_t *exp_cap;
+ Error *local_err = NULL;
assert(pci_is_express(dev));
- pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF);
+ pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
+ PCI_EXP_VER2_SIZEOF, &local_err);
if (pos < 0) {
+ error_report_err(local_err);
return pos;
}
dev->exp.exp_cap = pos;
@@ -123,11 +126,14 @@ int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
{
/* PCIe cap v1 init */
int pos;
+ Error *local_err = NULL;
assert(pci_is_express(dev));
- pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF);
+ pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
+ PCI_EXP_VER1_SIZEOF, &local_err);
if (pos < 0) {
+ error_report_err(local_err);
return pos;
}
dev->exp.exp_cap = pos;
diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c
index 42fafac..d72d5e4 100644
--- a/hw/pci/shpc.c
+++ b/hw/pci/shpc.c
@@ -450,9 +450,12 @@ static int shpc_cap_add_config(PCIDevice *d)
{
uint8_t *config;
int config_offset;
+ Error *local_err = NULL;
config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
- 0, SHPC_CAP_LENGTH);
+ 0, SHPC_CAP_LENGTH,
+ &local_err);
if (config_offset < 0) {
+ error_report_err(local_err);
return config_offset;
}
config = d->config + config_offset;
diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c
index aec1e91..bdca205 100644
--- a/hw/pci/slotid_cap.c
+++ b/hw/pci/slotid_cap.c
@@ -2,6 +2,7 @@
#include "hw/pci/slotid_cap.h"
#include "hw/pci/pci.h"
#include "qemu/error-report.h"
+#include "qapi/error.h"
#define SLOTID_CAP_LENGTH 4
#define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS)
@@ -11,6 +12,8 @@ int slotid_cap_init(PCIDevice *d, int nslots,
unsigned offset)
{
int cap;
+ Error *local_err = NULL;
+
if (!chassis) {
error_report("Bridge chassis not specified. Each bridge is required "
"to be assigned a unique chassis id > 0.");
@@ -21,8 +24,10 @@ int slotid_cap_init(PCIDevice *d, int nslots,
return -EINVAL;
}
- cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LENGTH);
+ cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset,
+ SLOTID_CAP_LENGTH, &local_err);
if (cap < 0) {
+ error_report_err(local_err);
return cap;
}
/* We make each chassis unique, this way each bridge is First in Chassis */
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 5881968..85cfe38 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -1743,7 +1743,8 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
}
- pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size);
+ pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size,
+ errp);
if (pos > 0) {
vdev->pdev.exp.exp_cap = pos;
}
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index f9b7244..cca5276 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1161,9 +1161,14 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
{
PCIDevice *dev = &proxy->pci_dev;
int offset;
+ Error *local_err = NULL;
- offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len);
- assert(offset > 0);
+ offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0,
+ cap->cap_len, &local_err);
+ if (offset < 0) {
+ error_report_err(local_err);
+ abort();
+ }
assert(cap->cap_len >= sizeof *cap);
memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
@@ -1810,9 +1815,13 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
pos = pcie_endpoint_cap_init(pci_dev, 0);
assert(pos > 0);
- pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF);
- assert(pos > 0);
- pci_dev->exp.pm_cap = pos;
+ pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,
+ PCI_PM_SIZEOF, errp);
+ if (pos > 0) {
+ pci_dev->exp.pm_cap = pos;
+ } else {
+ return;
+ }
/*
* Indicates that this function complies with revision 1.2 of the
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index a37a2d5..fe52aa8 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -356,7 +356,8 @@ void pci_unregister_vga(PCIDevice *pci_dev);
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
- uint8_t offset, uint8_t size);
+ uint8_t offset, uint8_t size,
+ Error **errp);
int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
uint8_t offset, uint8_t size,
Error **errp);
--
2.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 5/6] pci: Make errp the last parameter of pci_add_capability()
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 5/6] pci: Make errp the last parameter of pci_add_capability() Mao Zhongyi
@ 2017-06-02 17:45 ` Eduardo Habkost
2017-06-05 3:06 ` Mao Zhongyi
0 siblings, 1 reply; 19+ messages in thread
From: Eduardo Habkost @ 2017-06-02 17:45 UTC (permalink / raw)
To: Mao Zhongyi
Cc: qemu-devel, mst, pbonzini, rth, dmitry, jasowang, marcel,
alex.williamson, armbru
On Fri, Jun 02, 2017 at 03:54:41PM +0800, Mao Zhongyi wrote:
> Add Error argument for pci_add_capability() to leverage the errp
> to pass info on errors. This way is helpful for its callers to
> make a better error handling when moving to 'realize'.
>
> Cc: mst@redhat.com
> Cc: pbonzini@redhat.com
> Cc: rth@twiddle.net
> Cc: ehabkost@redhat.com
> Cc: dmitry@daynix.com
> Cc: jasowang@redhat.com
> Cc: marcel@redhat.com
> Cc: alex.williamson@redhat.com
> Cc: armbru@redhat.com
> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
[...]
> diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
> index 62e989c..f24046a 100644
> --- a/hw/net/eepro100.c
> +++ b/hw/net/eepro100.c
> @@ -494,7 +494,7 @@ static void eepro100_fcp_interrupt(EEPRO100State *s)
> }
> #endif
>
> -static void e100_pci_reset(EEPRO100State *s)
> +static void e100_pci_reset(EEPRO100State *s, Error **errp)
> {
> E100PCIDeviceInfo *info = eepro100_get_class(s);
> uint32_t device = s->device;
> @@ -570,9 +570,13 @@ static void e100_pci_reset(EEPRO100State *s)
> /* Power Management Capabilities */
> int cfg_offset = 0xdc;
> int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
> - cfg_offset, PCI_PM_SIZEOF);
> - assert(r > 0);
> - pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
> + cfg_offset, PCI_PM_SIZEOF,
> + errp);
> + if (r > 0) {
> + pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
> + } else {
> + return;
> + }
> #if 0 /* TODO: replace dummy code for power management emulation. */
> /* TODO: Power Management Control / Status. */
> pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
> @@ -1863,7 +1867,10 @@ static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
>
> s->device = info->device;
>
> - e100_pci_reset(s);
> + e100_pci_reset(s, errp);
> + if (errp && *errp) {
> + return;
> + }
This doesn't look right. The behavior of the function shouldn't
be different depending on the value of errp.
If you need to check for e100_pci_reset() errors inside
e100_nic_realize(), you'll need a local Error* variable and an
error_propagate() call. See the "Receive an error and pass it on
to the caller" example at include/qapi/error.h.
>
> /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
> * i82559 and later support 64 or 256 word EEPROM. */
--
Eduardo
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 5/6] pci: Make errp the last parameter of pci_add_capability()
2017-06-02 17:45 ` Eduardo Habkost
@ 2017-06-05 3:06 ` Mao Zhongyi
0 siblings, 0 replies; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-05 3:06 UTC (permalink / raw)
To: Eduardo Habkost
Cc: qemu-devel, mst, pbonzini, rth, dmitry, jasowang, marcel,
alex.williamson, armbru
Hi, Eduardo
On 06/03/2017 01:45 AM, Eduardo Habkost wrote:
> On Fri, Jun 02, 2017 at 03:54:41PM +0800, Mao Zhongyi wrote:
>> Add Error argument for pci_add_capability() to leverage the errp
>> to pass info on errors. This way is helpful for its callers to
>> make a better error handling when moving to 'realize'.
>>
>> Cc: mst@redhat.com
>> Cc: pbonzini@redhat.com
>> Cc: rth@twiddle.net
>> Cc: ehabkost@redhat.com
>> Cc: dmitry@daynix.com
>> Cc: jasowang@redhat.com
>> Cc: marcel@redhat.com
>> Cc: alex.williamson@redhat.com
>> Cc: armbru@redhat.com
>> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
> [...]
>> diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
>> index 62e989c..f24046a 100644
>> --- a/hw/net/eepro100.c
>> +++ b/hw/net/eepro100.c
>> @@ -494,7 +494,7 @@ static void eepro100_fcp_interrupt(EEPRO100State *s)
>> }
>> #endif
>>
>> -static void e100_pci_reset(EEPRO100State *s)
>> +static void e100_pci_reset(EEPRO100State *s, Error **errp)
>> {
>> E100PCIDeviceInfo *info = eepro100_get_class(s);
>> uint32_t device = s->device;
>> @@ -570,9 +570,13 @@ static void e100_pci_reset(EEPRO100State *s)
>> /* Power Management Capabilities */
>> int cfg_offset = 0xdc;
>> int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
>> - cfg_offset, PCI_PM_SIZEOF);
>> - assert(r > 0);
>> - pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
>> + cfg_offset, PCI_PM_SIZEOF,
>> + errp);
>> + if (r > 0) {
>> + pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
>> + } else {
>> + return;
>> + }
>> #if 0 /* TODO: replace dummy code for power management emulation. */
>> /* TODO: Power Management Control / Status. */
>> pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
>> @@ -1863,7 +1867,10 @@ static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
>>
>> s->device = info->device;
>>
>> - e100_pci_reset(s);
>> + e100_pci_reset(s, errp);
>> + if (errp && *errp) {
>> + return;
>> + }
>
> This doesn't look right. The behavior of the function shouldn't
> be different depending on the value of errp.
>
> If you need to check for e100_pci_reset() errors inside
> e100_nic_realize(), you'll need a local Error* variable and an
> error_propagate() call. See the "Receive an error and pass it on
> to the caller" example at include/qapi/error.h.
Thanks for your detailed explanation. I already know how to do it, will
fix it in the next version.
Mao
>>
>> /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
>> * i82559 and later support 64 or 256 word EEPROM. */
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v2 6/6] pci: Convert to realize
2017-06-02 7:54 [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Mao Zhongyi
` (4 preceding siblings ...)
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 5/6] pci: Make errp the last parameter of pci_add_capability() Mao Zhongyi
@ 2017-06-02 7:54 ` Mao Zhongyi
2017-06-06 15:23 ` [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Michael S. Tsirkin
6 siblings, 0 replies; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-02 7:54 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel, armbru
The pci-birdge device i82801b11 and io3130_upstream/downstream
still implements the old PCIDeviceClass .init() through *_init()
instead of the new .realize(). All devices need to be converted
to .realize(). So convert it and rename it to *_realize().
Cc: mst@redhat.com
Cc: marcel@redhat.com
Cc: armbru@redhat.com
Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
---
hw/pci-bridge/i82801b11.c | 11 +++++------
hw/pci-bridge/pcie_root_port.c | 15 ++++++---------
hw/pci-bridge/xio3130_downstream.c | 20 +++++++++-----------
hw/pci-bridge/xio3130_upstream.c | 20 +++++++++-----------
hw/pci/pci_bridge.c | 7 +++----
hw/pci/pcie.c | 11 ++++++-----
include/hw/pci/pci_bridge.h | 3 ++-
include/hw/pci/pcie.h | 3 ++-
8 files changed, 42 insertions(+), 48 deletions(-)
diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
index 2c065c3..2c1b747 100644
--- a/hw/pci-bridge/i82801b11.c
+++ b/hw/pci-bridge/i82801b11.c
@@ -59,24 +59,23 @@ typedef struct I82801b11Bridge {
/*< public >*/
} I82801b11Bridge;
-static int i82801b11_bridge_initfn(PCIDevice *d)
+static void i82801b11_bridge_realize(PCIDevice *d, Error **errp)
{
int rc;
pci_bridge_initfn(d, TYPE_PCI_BUS);
rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,
- I82801ba_SSVID_SVID, I82801ba_SSVID_SSID);
+ I82801ba_SSVID_SVID, I82801ba_SSVID_SSID,
+ errp);
if (rc < 0) {
goto err_bridge;
}
pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB);
- return 0;
+ return;
err_bridge:
pci_bridge_exitfn(d);
-
- return rc;
}
static const VMStateDescription i82801b11_bridge_dev_vmstate = {
@@ -96,7 +95,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;
k->revision = ICH9_D2P_A2_REVISION;
- k->init = i82801b11_bridge_initfn;
+ k->realize = i82801b11_bridge_realize;
k->config_write = pci_bridge_write_config;
dc->vmsd = &i82801b11_bridge_dev_vmstate;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
index cf36318..00f0b1f 100644
--- a/hw/pci-bridge/pcie_root_port.c
+++ b/hw/pci-bridge/pcie_root_port.c
@@ -59,29 +59,27 @@ static void rp_realize(PCIDevice *d, Error **errp)
PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
int rc;
- Error *local_err = NULL;
pci_config_set_interrupt_pin(d->config, 1);
pci_bridge_initfn(d, TYPE_PCIE_BUS);
pcie_port_init_reg(d);
- rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc->ssid);
+ rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id,
+ rpc->ssid, errp);
if (rc < 0) {
- error_setg(errp, "Can't init SSV ID, error %d", rc);
goto err_bridge;
}
if (rpc->interrupts_init) {
- rc = rpc->interrupts_init(d, &local_err);
+ rc = rpc->interrupts_init(d, errp);
if (rc < 0) {
- error_propagate(errp, local_err);
goto err_bridge;
}
}
- rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->port);
+ rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT,
+ p->port, errp);
if (rc < 0) {
- error_setg(errp, "Can't add Root Port capability, error %d", rc);
goto err_int;
}
@@ -98,9 +96,8 @@ static void rp_realize(PCIDevice *d, Error **errp)
}
rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset,
- PCI_ERR_SIZEOF, &local_err);
+ PCI_ERR_SIZEOF, errp);
if (rc < 0) {
- error_propagate(errp, local_err);
goto err;
}
pcie_aer_root_init(d);
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index cfe8a36..e706f36 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -56,33 +56,33 @@ static void xio3130_downstream_reset(DeviceState *qdev)
pci_bridge_reset(qdev);
}
-static int xio3130_downstream_initfn(PCIDevice *d)
+static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
{
PCIEPort *p = PCIE_PORT(d);
PCIESlot *s = PCIE_SLOT(d);
int rc;
- Error *err = NULL;
pci_bridge_initfn(d, TYPE_PCIE_BUS);
pcie_port_init_reg(d);
rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
- XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);
+ XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
+ errp);
if (rc < 0) {
assert(rc == -ENOTSUP);
- error_report_err(err);
goto err_bridge;
}
rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
- XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
+ XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
+ errp);
if (rc < 0) {
goto err_bridge;
}
rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
- p->port);
+ p->port, errp);
if (rc < 0) {
goto err_msi;
}
@@ -98,13 +98,12 @@ static int xio3130_downstream_initfn(PCIDevice *d)
}
rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
- PCI_ERR_SIZEOF, &err);
+ PCI_ERR_SIZEOF, errp);
if (rc < 0) {
- error_report_err(err);
goto err;
}
- return 0;
+ return;
err:
pcie_chassis_del_slot(s);
@@ -114,7 +113,6 @@ err_msi:
msi_uninit(d);
err_bridge:
pci_bridge_exitfn(d);
- return rc;
}
static void xio3130_downstream_exitfn(PCIDevice *d)
@@ -181,7 +179,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
k->is_express = 1;
k->is_bridge = 1;
k->config_write = xio3130_downstream_write_config;
- k->init = xio3130_downstream_initfn;
+ k->realize = xio3130_downstream_realize;
k->exit = xio3130_downstream_exitfn;
k->vendor_id = PCI_VENDOR_ID_TI;
k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index 401c784..a052224 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -53,32 +53,32 @@ static void xio3130_upstream_reset(DeviceState *qdev)
pcie_cap_deverr_reset(d);
}
-static int xio3130_upstream_initfn(PCIDevice *d)
+static void xio3130_upstream_realize(PCIDevice *d, Error **errp)
{
PCIEPort *p = PCIE_PORT(d);
int rc;
- Error *err = NULL;
pci_bridge_initfn(d, TYPE_PCIE_BUS);
pcie_port_init_reg(d);
rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
- XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);
+ XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
+ errp);
if (rc < 0) {
assert(rc == -ENOTSUP);
- error_report_err(err);
goto err_bridge;
}
rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
- XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
+ XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
+ errp);
if (rc < 0) {
goto err_bridge;
}
rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
- p->port);
+ p->port, errp);
if (rc < 0) {
goto err_msi;
}
@@ -86,13 +86,12 @@ static int xio3130_upstream_initfn(PCIDevice *d)
pcie_cap_deverr_init(d);
rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
- PCI_ERR_SIZEOF, &err);
+ PCI_ERR_SIZEOF, errp);
if (rc < 0) {
- error_report_err(err);
goto err;
}
- return 0;
+ return;
err:
pcie_cap_exit(d);
@@ -100,7 +99,6 @@ err_msi:
msi_uninit(d);
err_bridge:
pci_bridge_exitfn(d);
- return rc;
}
static void xio3130_upstream_exitfn(PCIDevice *d)
@@ -153,7 +151,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
k->is_express = 1;
k->is_bridge = 1;
k->config_write = xio3130_upstream_write_config;
- k->init = xio3130_upstream_initfn;
+ k->realize = xio3130_upstream_realize;
k->exit = xio3130_upstream_exitfn;
k->vendor_id = PCI_VENDOR_ID_TI;
k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index bb0f3a3..720119b 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -41,15 +41,14 @@
#define PCI_SSVID_SSID 6
int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
- uint16_t svid, uint16_t ssid)
+ uint16_t svid, uint16_t ssid,
+ Error **errp)
{
int pos;
- Error *local_err = NULL;
pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
- PCI_SSVID_SIZEOF, &local_err);
+ PCI_SSVID_SIZEOF, errp);
if (pos < 0) {
- error_report_err(local_err);
return pos;
}
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index f187512..05d091a 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -86,19 +86,19 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
}
-int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
+int pcie_cap_init(PCIDevice *dev, uint8_t offset,
+ uint8_t type, uint8_t port,
+ Error **errp)
{
/* PCIe cap v2 init */
int pos;
uint8_t *exp_cap;
- Error *local_err = NULL;
assert(pci_is_express(dev));
pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
- PCI_EXP_VER2_SIZEOF, &local_err);
+ PCI_EXP_VER2_SIZEOF, errp);
if (pos < 0) {
- error_report_err(local_err);
return pos;
}
dev->exp.exp_cap = pos;
@@ -147,6 +147,7 @@ static int
pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
{
uint8_t type = PCI_EXP_TYPE_ENDPOINT;
+ Error *local_err = NULL;
/*
* Windows guests will report Code 10, device cannot start, if
@@ -159,7 +160,7 @@ pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
return (cap_size == PCI_EXP_VER1_SIZEOF)
? pcie_cap_v1_init(dev, offset, type, 0)
- : pcie_cap_init(dev, offset, type, 0);
+ : pcie_cap_init(dev, offset, type, 0, &local_err);
}
int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
index d5891cd..ff7cbaa 100644
--- a/include/hw/pci/pci_bridge.h
+++ b/include/hw/pci/pci_bridge.h
@@ -33,7 +33,8 @@
#define PCI_BRIDGE_DEV_PROP_SHPC "shpc"
int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
- uint16_t svid, uint16_t ssid);
+ uint16_t svid, uint16_t ssid,
+ Error **errp);
PCIDevice *pci_bridge_get_device(PCIBus *bus);
PCIBus *pci_bridge_get_sec_bus(PCIBridge *br);
diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
index 3d8f24b..b71e369 100644
--- a/include/hw/pci/pcie.h
+++ b/include/hw/pci/pcie.h
@@ -84,7 +84,8 @@ struct PCIExpressDevice {
#define COMPAT_PROP_PCP "power_controller_present"
/* PCI express capability helper functions */
-int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port);
+int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type,
+ uint8_t port, Error **errp);
int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset,
uint8_t type, uint8_t port);
int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset);
--
2.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup
2017-06-02 7:54 [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Mao Zhongyi
` (5 preceding siblings ...)
2017-06-02 7:54 ` [Qemu-devel] [PATCH v2 6/6] pci: Convert to realize Mao Zhongyi
@ 2017-06-06 15:23 ` Michael S. Tsirkin
2017-06-07 2:51 ` Mao Zhongyi
6 siblings, 1 reply; 19+ messages in thread
From: Michael S. Tsirkin @ 2017-06-06 15:23 UTC (permalink / raw)
To: Mao Zhongyi; +Cc: qemu-devel
Notes:
- Please write a cover letter explaining what this patchset is about
- Please add notes about how did you test it
- Pls copy everyone on the cover letter too.
- Please run a spell checker on comments and commit log
Thanks!
On Fri, Jun 02, 2017 at 03:54:36PM +0800, Mao Zhongyi wrote:
> v2:
> * patch1: subject and commit message was rewrited by markus.
> * patch2: comment was added to pci_add_capability2().
> * patch3: a new patch that fix the wrong return value judgment condition.
> * patch4: a new patch that fix code style problems.
> * patch5: add an errp argument for pci_add_capability to pass
> error for its callers.
> * patch6: convert part of pci-bridge device to realize.
>
> v1:
> * patch1: fix unreasonable return value check
> Mao Zhongyi (6):
> pci: Clean up error checking in pci_add_capability()
> pci: Add comment for pci_add_capability2()
> pci: Fix the wrong return value judgment condition
> net/eepro100: Fixed code style
> pci: Make errp the last parameter of pci_add_capability()
> pci: Convert to realize
>
> hw/i386/amd_iommu.c | 24 ++++++++----
> hw/net/e1000e.c | 9 ++++-
> hw/net/eepro100.c | 77 +++++++++++++++++++++-----------------
> hw/pci-bridge/i82801b11.c | 12 +++---
> hw/pci-bridge/pcie_root_port.c | 15 +++-----
> hw/pci-bridge/xio3130_downstream.c | 20 +++++-----
> hw/pci-bridge/xio3130_upstream.c | 20 +++++-----
> hw/pci/pci.c | 18 ++++-----
> hw/pci/pci_bridge.c | 8 +++-
> hw/pci/pcie.c | 15 ++++++--
> hw/pci/shpc.c | 5 ++-
> hw/pci/slotid_cap.c | 7 +++-
> hw/vfio/pci.c | 5 ++-
> hw/virtio/virtio-pci.c | 19 +++++++---
> include/hw/pci/pci.h | 3 +-
> include/hw/pci/pci_bridge.h | 3 +-
> include/hw/pci/pcie.h | 3 +-
> 17 files changed, 154 insertions(+), 109 deletions(-)
>
> --
> 2.9.3
>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup
2017-06-06 15:23 ` [Qemu-devel] [PATCH v2 0/6] Convert to realize and cleanup Michael S. Tsirkin
@ 2017-06-07 2:51 ` Mao Zhongyi
0 siblings, 0 replies; 19+ messages in thread
From: Mao Zhongyi @ 2017-06-07 2:51 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel
Hi, Michael
On 06/06/2017 11:23 PM, Michael S. Tsirkin wrote:
> Notes:
> - Please write a cover letter explaining what this patchset is about
> - Please add notes about how did you test it
> - Pls copy everyone on the cover letter too.
> - Please run a spell checker on comments and commit log
>
> Thanks!
OK, I see.
Thanks for your kind reminder.
Mao
>
> On Fri, Jun 02, 2017 at 03:54:36PM +0800, Mao Zhongyi wrote:
>> v2:
>> * patch1: subject and commit message was rewrited by markus.
>> * patch2: comment was added to pci_add_capability2().
>> * patch3: a new patch that fix the wrong return value judgment condition.
>> * patch4: a new patch that fix code style problems.
>> * patch5: add an errp argument for pci_add_capability to pass
>> error for its callers.
>> * patch6: convert part of pci-bridge device to realize.
>>
>> v1:
>> * patch1: fix unreasonable return value check
>> Mao Zhongyi (6):
>> pci: Clean up error checking in pci_add_capability()
>> pci: Add comment for pci_add_capability2()
>> pci: Fix the wrong return value judgment condition
>> net/eepro100: Fixed code style
>> pci: Make errp the last parameter of pci_add_capability()
>> pci: Convert to realize
>>
>> hw/i386/amd_iommu.c | 24 ++++++++----
>> hw/net/e1000e.c | 9 ++++-
>> hw/net/eepro100.c | 77 +++++++++++++++++++++-----------------
>> hw/pci-bridge/i82801b11.c | 12 +++---
>> hw/pci-bridge/pcie_root_port.c | 15 +++-----
>> hw/pci-bridge/xio3130_downstream.c | 20 +++++-----
>> hw/pci-bridge/xio3130_upstream.c | 20 +++++-----
>> hw/pci/pci.c | 18 ++++-----
>> hw/pci/pci_bridge.c | 8 +++-
>> hw/pci/pcie.c | 15 ++++++--
>> hw/pci/shpc.c | 5 ++-
>> hw/pci/slotid_cap.c | 7 +++-
>> hw/vfio/pci.c | 5 ++-
>> hw/virtio/virtio-pci.c | 19 +++++++---
>> include/hw/pci/pci.h | 3 +-
>> include/hw/pci/pci_bridge.h | 3 +-
>> include/hw/pci/pcie.h | 3 +-
>> 17 files changed, 154 insertions(+), 109 deletions(-)
>>
>> --
>> 2.9.3
>>
>>
>>
>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread