From: "Jérémy Lefaure" <jeremy.lefaure@lse.epita.fr> To: Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org> Cc: "Jérémy Lefaure" <jeremy.lefaure@lse.epita.fr>, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] edac, i5000, i5400: fix definition of nrecmemb register Date: Mon, 12 Jun 2017 13:47:58 -0400 [thread overview] Message-ID: <20170612174759.7649-1-jeremy.lefaure@lse.epita.fr> (raw) In i5000 and i5400 edac drivers, the register nrecmemb is defined as a 16 bits value which result in wrong shifts in the code: CHECK drivers/edac/i5000_edac.c drivers/edac/i5000_edac.c:485:15: warning: right shift by bigger than source value drivers/edac/i5000_edac.c:580:23: warning: right shift by bigger than source value CC drivers/edac/i5000_edac.o CHECK drivers/edac/i5400_edac.c drivers/edac/i5400_edac.c:391:36: warning: right shift by bigger than source value drivers/edac/i5400_edac.c:401:37: warning: right shift by bigger than source value CC drivers/edac/i5400_edac.o In the datasheets ([1], section 3.9.22.20 and [2], section 3.9.22.21), this register is a 32 bits register. A u32 value for the register fixes the wrong shifts warnings and matches the datasheet. This patch also fixes the mask to access to the CAS bits [16 to 28] in the i5000 edac driver. [1]: https://www.intel.com/content/dam/doc/datasheet/5000p-5000v-5000z-chipset-memory-controller-hub-datasheet.pdf [2]: https://www.intel.se/content/dam/doc/datasheet/5400-chipset-memory-controller-hub-datasheet.pdf Signed-off-by: Jérémy Lefaure <jeremy.lefaure@lse.epita.fr> --- I have found this error thanks to the sparse tool. Please note that this patch hasn't been tested on real hardware. drivers/edac/i5000_edac.c | 6 +++--- drivers/edac/i5400_edac.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c index f683919981b0..c79016ade51e 100644 --- a/drivers/edac/i5000_edac.c +++ b/drivers/edac/i5000_edac.c @@ -227,7 +227,7 @@ #define NREC_RDWR(x) (((x)>>11) & 1) #define NREC_RANK(x) (((x)>>8) & 0x7) #define NRECMEMB 0xC0 -#define NREC_CAS(x) (((x)>>16) & 0xFFFFFF) +#define NREC_CAS(x) (((x)>>16) & 0x1FFF) #define NREC_RAS(x) ((x) & 0x7FFF) #define NRECFGLOG 0xC4 #define NREEECFBDA 0xC8 @@ -371,7 +371,7 @@ struct i5000_error_info { /* These registers are input ONLY if there was a * Non-Recoverable Error */ u16 nrecmema; /* Non-Recoverable Mem log A */ - u16 nrecmemb; /* Non-Recoverable Mem log B */ + u32 nrecmemb; /* Non-Recoverable Mem log B */ }; @@ -407,7 +407,7 @@ static void i5000_get_error_info(struct mem_ctl_info *mci, NERR_FAT_FBD, &info->nerr_fat_fbd); pci_read_config_word(pvt->branchmap_werrors, NRECMEMA, &info->nrecmema); - pci_read_config_word(pvt->branchmap_werrors, + pci_read_config_dword(pvt->branchmap_werrors, NRECMEMB, &info->nrecmemb); /* Clear the error bits, by writing them back */ diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c index 37a9ba71da44..cd889edc8516 100644 --- a/drivers/edac/i5400_edac.c +++ b/drivers/edac/i5400_edac.c @@ -368,7 +368,7 @@ struct i5400_error_info { /* These registers are input ONLY if there was a Non-Rec Error */ u16 nrecmema; /* Non-Recoverable Mem log A */ - u16 nrecmemb; /* Non-Recoverable Mem log B */ + u32 nrecmemb; /* Non-Recoverable Mem log B */ }; @@ -458,7 +458,7 @@ static void i5400_get_error_info(struct mem_ctl_info *mci, NERR_FAT_FBD, &info->nerr_fat_fbd); pci_read_config_word(pvt->branchmap_werrors, NRECMEMA, &info->nrecmema); - pci_read_config_word(pvt->branchmap_werrors, + pci_read_config_dword(pvt->branchmap_werrors, NRECMEMB, &info->nrecmemb); /* Clear the error bits, by writing them back */ -- 2.13.1
WARNING: multiple messages have this Message-ID (diff)
From: "Jérémy Lefaure" <jeremy.lefaure@lse.epita.fr> To: Borislav Petkov <bp@alien8.de>, Mauro Carvalho Chehab <mchehab@kernel.org> Cc: "Jérémy Lefaure" <jeremy.lefaure@lse.epita.fr>, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: edac, i5000, i5400: fix definition of nrecmemb register Date: Mon, 12 Jun 2017 13:47:58 -0400 [thread overview] Message-ID: <20170612174759.7649-1-jeremy.lefaure@lse.epita.fr> (raw) In i5000 and i5400 edac drivers, the register nrecmemb is defined as a 16 bits value which result in wrong shifts in the code: CHECK drivers/edac/i5000_edac.c drivers/edac/i5000_edac.c:485:15: warning: right shift by bigger than source value drivers/edac/i5000_edac.c:580:23: warning: right shift by bigger than source value CC drivers/edac/i5000_edac.o CHECK drivers/edac/i5400_edac.c drivers/edac/i5400_edac.c:391:36: warning: right shift by bigger than source value drivers/edac/i5400_edac.c:401:37: warning: right shift by bigger than source value CC drivers/edac/i5400_edac.o In the datasheets ([1], section 3.9.22.20 and [2], section 3.9.22.21), this register is a 32 bits register. A u32 value for the register fixes the wrong shifts warnings and matches the datasheet. This patch also fixes the mask to access to the CAS bits [16 to 28] in the i5000 edac driver. [1]: https://www.intel.com/content/dam/doc/datasheet/5000p-5000v-5000z-chipset-memory-controller-hub-datasheet.pdf [2]: https://www.intel.se/content/dam/doc/datasheet/5400-chipset-memory-controller-hub-datasheet.pdf Signed-off-by: Jérémy Lefaure <jeremy.lefaure@lse.epita.fr> --- I have found this error thanks to the sparse tool. Please note that this patch hasn't been tested on real hardware. drivers/edac/i5000_edac.c | 6 +++--- drivers/edac/i5400_edac.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c index f683919981b0..c79016ade51e 100644 --- a/drivers/edac/i5000_edac.c +++ b/drivers/edac/i5000_edac.c @@ -227,7 +227,7 @@ #define NREC_RDWR(x) (((x)>>11) & 1) #define NREC_RANK(x) (((x)>>8) & 0x7) #define NRECMEMB 0xC0 -#define NREC_CAS(x) (((x)>>16) & 0xFFFFFF) +#define NREC_CAS(x) (((x)>>16) & 0x1FFF) #define NREC_RAS(x) ((x) & 0x7FFF) #define NRECFGLOG 0xC4 #define NREEECFBDA 0xC8 @@ -371,7 +371,7 @@ struct i5000_error_info { /* These registers are input ONLY if there was a * Non-Recoverable Error */ u16 nrecmema; /* Non-Recoverable Mem log A */ - u16 nrecmemb; /* Non-Recoverable Mem log B */ + u32 nrecmemb; /* Non-Recoverable Mem log B */ }; @@ -407,7 +407,7 @@ static void i5000_get_error_info(struct mem_ctl_info *mci, NERR_FAT_FBD, &info->nerr_fat_fbd); pci_read_config_word(pvt->branchmap_werrors, NRECMEMA, &info->nrecmema); - pci_read_config_word(pvt->branchmap_werrors, + pci_read_config_dword(pvt->branchmap_werrors, NRECMEMB, &info->nrecmemb); /* Clear the error bits, by writing them back */ diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c index 37a9ba71da44..cd889edc8516 100644 --- a/drivers/edac/i5400_edac.c +++ b/drivers/edac/i5400_edac.c @@ -368,7 +368,7 @@ struct i5400_error_info { /* These registers are input ONLY if there was a Non-Rec Error */ u16 nrecmema; /* Non-Recoverable Mem log A */ - u16 nrecmemb; /* Non-Recoverable Mem log B */ + u32 nrecmemb; /* Non-Recoverable Mem log B */ }; @@ -458,7 +458,7 @@ static void i5400_get_error_info(struct mem_ctl_info *mci, NERR_FAT_FBD, &info->nerr_fat_fbd); pci_read_config_word(pvt->branchmap_werrors, NRECMEMA, &info->nrecmema); - pci_read_config_word(pvt->branchmap_werrors, + pci_read_config_dword(pvt->branchmap_werrors, NRECMEMB, &info->nrecmemb); /* Clear the error bits, by writing them back */
next reply other threads:[~2017-06-12 17:49 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-12 17:47 Jérémy Lefaure [this message] 2017-06-12 17:47 ` edac, i5000, i5400: fix definition of nrecmemb register Jérémy Lefaure 2017-06-28 16:08 ` [PATCH] " Borislav Petkov 2017-06-28 16:08 ` Borislav Petkov 2017-06-29 0:54 ` [PATCH] " Jérémy Lefaure 2017-06-29 0:54 ` Jérémy Lefaure 2017-06-29 0:57 ` [PATCH v2] " Jérémy Lefaure 2017-06-29 0:57 ` [v2] " Jérémy Lefaure 2017-06-29 8:36 ` [PATCH v2] " Borislav Petkov 2017-06-29 8:36 ` [v2] " Borislav Petkov
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