[PATCH 0/2] Handle unsupported configuration with IF-ID

[PATCH 0/2] Handle unsupported configuration with IF-ID

[Mahesh Kumar]

Gen9+ Interlace fetch mode doesn't support few plane configurations & pipe scaling.
 - Y-tile
 - 90/270 rotation
 - pipe/plane scaling
 - 420 planar formats

Mahesh Kumar (2):
  drm/i915/skl+: Check for supported plane configuration in Interlace
    mode
  drm/i915/skl+: Pipe scaling not supported in IF-ID Interlace mode

 drivers/gpu/drm/i915/intel_atomic.c  |  8 ++++++++
 drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

-- 
2.13.0

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[PATCH 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode

[Mahesh Kumar]

In Gen9 platform Interlaced fetch mode doesn't support following plane
configuration:
 - Y/Yf tiling
 - 90/270 rotation
 - Scaling
 - YUV420 hybrid planar source pixel formats.

This patch adds check to fail the flip if any of the above configuration
is requested.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4e03ca6c946f..1f2394a0c07d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11022,6 +11022,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 	bool is_crtc_enabled = crtc_state->active;
 	bool turn_off, turn_on, visible, was_visible;
 	struct drm_framebuffer *fb = plane_state->fb;
+	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 	int ret;
 
 	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
@@ -11108,6 +11109,41 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 	    !needs_scaling(old_plane_state))
 		pipe_config->disable_lp_wm = true;
 
+	/*
+	 * Y-tiling is not supported in IF-ID Interlace mode in
+	 * GEN9 and above.
+	 * Scaling is not supported with Interlaced fetch mode.
+	 * YUV420 hybrid planar source pixel formats are not supported with
+	 * Interlaced fetch mode.
+	 */
+	if (visible && INTEL_GEN(dev_priv) >= 9 &&
+				mode->flags & DRM_MODE_FLAG_INTERLACE) {
+		struct drm_format_name_buf format_name;
+
+		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
+			DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
+			return -EINVAL;
+		}
+
+		if (needs_scaling(to_intel_plane_state(plane_state))) {
+			DRM_DEBUG_KMS("Scaling not supported in IF-ID mode\n");
+			return -EINVAL;
+		}
+
+		switch (fb->format->format) {
+		case DRM_FORMAT_NV12:
+		case DRM_FORMAT_YUV420:
+		case DRM_FORMAT_YVU420:
+			DRM_DEBUG_KMS("Unsupported pixel format %s for IF-ID\n",
+				      drm_get_format_name(fb->format->format,
+				      &format_name));
+			return -EINVAL;
+		default:
+			break;
+		}
+	}
+
 	return 0;
 }
 
-- 
2.13.0

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Re: [PATCH 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode

[Ville Syrjälä]

On Thu, Jun 29, 2017 at 02:27:39PM +0530, Mahesh Kumar wrote:
> In Gen9 platform Interlaced fetch mode doesn't support following plane
> configuration:
>  - Y/Yf tiling
>  - 90/270 rotation
>  - Scaling
>  - YUV420 hybrid planar source pixel formats.
> 
> This patch adds check to fail the flip if any of the above configuration
> is requested.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4e03ca6c946f..1f2394a0c07d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11022,6 +11022,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,

calc_changes seems like the wrong place for this. 
intel_plane_atomic_check_with_state() seems better.

>  	bool is_crtc_enabled = crtc_state->active;
>  	bool turn_off, turn_on, visible, was_visible;
>  	struct drm_framebuffer *fb = plane_state->fb;
> +	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;

Please call it "adjusted_mode".

>  	int ret;
>  
>  	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
> @@ -11108,6 +11109,41 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
>  	    !needs_scaling(old_plane_state))
>  		pipe_config->disable_lp_wm = true;
>  
> +	/*
> +	 * Y-tiling is not supported in IF-ID Interlace mode in
> +	 * GEN9 and above.
> +	 * Scaling is not supported with Interlaced fetch mode.
> +	 * YUV420 hybrid planar source pixel formats are not supported with
> +	 * Interlaced fetch mode.
> +	 */
> +	if (visible && INTEL_GEN(dev_priv) >= 9 &&

I think here we probably want state->fb instead of visible.
Hmm. I guess it'll have to check for crtc_state->enable as well
to make sure the adjusted_mode is valid.

In fact it looks to me like we could perhaps combine these with
the already existing rotation vs. format/modifier checks in
intel_plane_atomic_check_with_state()

> +				mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +		struct drm_format_name_buf format_name;
> +
> +		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> +		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
> +			DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> +			return -EINVAL;
> +		}
> +
> +		if (needs_scaling(to_intel_plane_state(plane_state))) {
> +			DRM_DEBUG_KMS("Scaling not supported in IF-ID mode\n");
> +			return -EINVAL;
> +		}
> +
> +		switch (fb->format->format) {
> +		case DRM_FORMAT_NV12:
> +		case DRM_FORMAT_YUV420:
> +		case DRM_FORMAT_YVU420:

We don't support those formats. NV12 we'll hopefully get some
time soon, so we could keep that.

> +			DRM_DEBUG_KMS("Unsupported pixel format %s for IF-ID\n",
> +				      drm_get_format_name(fb->format->format,
> +				      &format_name));
> +			return -EINVAL;
> +		default:
> +			break;
> +		}
> +	}
> +
>  	return 0;
>  }
>  
> -- 
> 2.13.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode

[Mahesh Kumar]

Hi,


On Thursday 29 June 2017 07:36 PM, Ville Syrjälä wrote:
> On Thu, Jun 29, 2017 at 02:27:39PM +0530, Mahesh Kumar wrote:
>> In Gen9 platform Interlaced fetch mode doesn't support following plane
>> configuration:
>>   - Y/Yf tiling
>>   - 90/270 rotation
>>   - Scaling
>>   - YUV420 hybrid planar source pixel formats.
>>
>> This patch adds check to fail the flip if any of the above configuration
>> is requested.
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 4e03ca6c946f..1f2394a0c07d 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -11022,6 +11022,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> calc_changes seems like the wrong place for this.
> intel_plane_atomic_check_with_state() seems better.
ok, will move it to intel_plane_atomic_check_with_state()
>
>>   	bool is_crtc_enabled = crtc_state->active;
>>   	bool turn_off, turn_on, visible, was_visible;
>>   	struct drm_framebuffer *fb = plane_state->fb;
>> +	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> Please call it "adjusted_mode".
ok :)
>
>>   	int ret;
>>   
>>   	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
>> @@ -11108,6 +11109,41 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
>>   	    !needs_scaling(old_plane_state))
>>   		pipe_config->disable_lp_wm = true;
>>   
>> +	/*
>> +	 * Y-tiling is not supported in IF-ID Interlace mode in
>> +	 * GEN9 and above.
>> +	 * Scaling is not supported with Interlaced fetch mode.
>> +	 * YUV420 hybrid planar source pixel formats are not supported with
>> +	 * Interlaced fetch mode.
>> +	 */
>> +	if (visible && INTEL_GEN(dev_priv) >= 9 &&
> I think here we probably want state->fb instead of visible.
> Hmm. I guess it'll have to check for crtc_state->enable as well
> to make sure the adjusted_mode is valid.
>
> In fact it looks to me like we could perhaps combine these with
> the already existing rotation vs. format/modifier checks in
> intel_plane_atomic_check_with_state()
ok
thanks for review

-Mahesh
>
>> +				mode->flags & DRM_MODE_FLAG_INTERLACE) {
>> +		struct drm_format_name_buf format_name;
>> +
>> +		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>> +		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
>> +			DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (needs_scaling(to_intel_plane_state(plane_state))) {
>> +			DRM_DEBUG_KMS("Scaling not supported in IF-ID mode\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		switch (fb->format->format) {
>> +		case DRM_FORMAT_NV12:
>> +		case DRM_FORMAT_YUV420:
>> +		case DRM_FORMAT_YVU420:
> We don't support those formats. NV12 we'll hopefully get some
> time soon, so we could keep that.
>
>> +			DRM_DEBUG_KMS("Unsupported pixel format %s for IF-ID\n",
>> +				      drm_get_format_name(fb->format->format,
>> +				      &format_name));
>> +			return -EINVAL;
>> +		default:
>> +			break;
>> +		}
>> +	}
>> +
>>   	return 0;
>>   }
>>   
>> -- 
>> 2.13.0

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[PATCH 2/2] drm/i915/skl+: Pipe scaling not supported in IF-ID Interlace mode

[Mahesh Kumar]

GEN9+ Interlace fetch mode doesn't support pipe scaling,
This patch adds check to fail the flip if pipe scaling is requested in
Interlace fetch mode.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e635e4ce..a1206d4f9a23 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -224,6 +224,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
 	struct drm_atomic_state *drm_state = crtc_state->base.state;
+	const struct drm_display_mode *mode = &crtc_state->base.adjusted_mode;
 	int num_scalers_need;
 	int i, j;
 
@@ -248,6 +249,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 		return -EINVAL;
 	}
 
+	/* Scaling/fitting not supported in IF-ID mode in GEN9+ */
+	if (INTEL_GEN(dev_priv) >=9 && mode->flags & DRM_MODE_FLAG_INTERLACE &&
+			scaler_state->scaler_users & (1 << SKL_CRTC_INDEX)) {
+		DRM_DEBUG_KMS("Pipe Scaling not supported with IF-ID mode\n");
+		return -EINVAL;
+	}
+
 	/* walkthrough scaler_users bits and start assigning scalers */
 	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 		int *scaler_id;
-- 
2.13.0

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Re: [PATCH 2/2] drm/i915/skl+: Pipe scaling not supported in IF-ID Interlace mode

[Ville Syrjälä]

On Thu, Jun 29, 2017 at 02:27:40PM +0530, Mahesh Kumar wrote:
> GEN9+ Interlace fetch mode doesn't support pipe scaling,
> This patch adds check to fail the flip if pipe scaling is requested in
> Interlace fetch mode.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 36d4e635e4ce..a1206d4f9a23 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -224,6 +224,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  	struct intel_crtc_scaler_state *scaler_state =
>  		&crtc_state->scaler_state;
>  	struct drm_atomic_state *drm_state = crtc_state->base.state;
> +	const struct drm_display_mode *mode = &crtc_state->base.adjusted_mode;

"adjusted_mode"

>  	int num_scalers_need;
>  	int i, j;
>  
> @@ -248,6 +249,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  		return -EINVAL;
>  	}
>  
> +	/* Scaling/fitting not supported in IF-ID mode in GEN9+ */
> +	if (INTEL_GEN(dev_priv) >=9 && mode->flags & DRM_MODE_FLAG_INTERLACE &&
> +			scaler_state->scaler_users & (1 << SKL_CRTC_INDEX)) {
> +		DRM_DEBUG_KMS("Pipe Scaling not supported with IF-ID mode\n");
> +		return -EINVAL;
> +	}

Hmm. I think if you put this into skl_update_scaler() then it'll catch
both pipe and plane scalers for you automagically.

> +
>  	/* walkthrough scaler_users bits and start assigning scalers */
>  	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
>  		int *scaler_id;
> -- 
> 2.13.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 2/2] drm/i915/skl+: Pipe scaling not supported in IF-ID Interlace mode

[Mahesh Kumar]

Hi,


On Thursday 29 June 2017 07:46 PM, Ville Syrjälä wrote:
> On Thu, Jun 29, 2017 at 02:27:40PM +0530, Mahesh Kumar wrote:
>> GEN9+ Interlace fetch mode doesn't support pipe scaling,
>> This patch adds check to fail the flip if pipe scaling is requested in
>> Interlace fetch mode.
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
>> index 36d4e635e4ce..a1206d4f9a23 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic.c
>> @@ -224,6 +224,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>   	struct intel_crtc_scaler_state *scaler_state =
>>   		&crtc_state->scaler_state;
>>   	struct drm_atomic_state *drm_state = crtc_state->base.state;
>> +	const struct drm_display_mode *mode = &crtc_state->base.adjusted_mode;
> "adjusted_mode"
ok
>
>>   	int num_scalers_need;
>>   	int i, j;
>>   
>> @@ -248,6 +249,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>   		return -EINVAL;
>>   	}
>>   
>> +	/* Scaling/fitting not supported in IF-ID mode in GEN9+ */
>> +	if (INTEL_GEN(dev_priv) >=9 && mode->flags & DRM_MODE_FLAG_INTERLACE &&
>> +			scaler_state->scaler_users & (1 << SKL_CRTC_INDEX)) {
>> +		DRM_DEBUG_KMS("Pipe Scaling not supported with IF-ID mode\n");
>> +		return -EINVAL;
>> +	}
> Hmm. I think if you put this into skl_update_scaler() then it'll catch
> both pipe and plane scalers for you automagically.
will update.
-Mahesh
>
>> +
>>   	/* walkthrough scaler_users bits and start assigning scalers */
>>   	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
>>   		int *scaler_id;
>> -- 
>> 2.13.0

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✓ Fi.CI.BAT: success for Handle unsupported configuration with IF-ID

[Patchwork]

== Series Details ==

Series: Handle unsupported configuration with IF-ID
URL   : https://patchwork.freedesktop.org/series/26546/
State : success

== Summary ==

Series 26546v1 Handle unsupported configuration with IF-ID
https://patchwork.freedesktop.org/api/1.0/series/26546/revisions/1/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                fail       -> PASS       (fi-snb-2600) fdo#100007
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-pnv-d510) fdo#101597 +1

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:443s
fi-bdw-gvtdvm    total:279  pass:257  dwarn:8   dfail:0   fail:0   skip:14  time:428s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:357s
fi-bsw-n3050     total:279  pass:242  dwarn:1   dfail:0   fail:0   skip:36  time:541s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:502s
fi-byt-j1900     total:279  pass:253  dwarn:2   dfail:0   fail:0   skip:24  time:496s
fi-byt-n2820     total:279  pass:249  dwarn:2   dfail:0   fail:0   skip:28  time:485s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:593s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:433s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:413s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:420s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:488s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:473s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:469s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:581s
fi-kbl-r         total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  time:580s
fi-pnv-d510      total:279  pass:221  dwarn:3   dfail:0   fail:0   skip:55  time:555s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:458s
fi-skl-6700hq    total:279  pass:223  dwarn:1   dfail:0   fail:30  skip:24  time:341s
fi-skl-6700k     total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  time:474s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:484s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:437s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:542s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:400s

85a692e2c6a7cf93082044d776e838cb9e9b2146 drm-tip: 2017y-06m-28d-14h-24m-59s UTC integration manifest
f8f52e2 drm/i915/skl+: Pipe scaling not supported in IF-ID Interlace mode
4a2b354 drm/i915/skl+: Check for supported plane configuration in Interlace mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5066/
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