[PATCH] drm/i915: enable WaDisableDopClkGating for SKL GT4

[PATCH] drm/i915: enable WaDisableDopClkGating for SKL GT4

[Praveen Paneri]

This WA is required when decopled frequencies for slice
and unslice are enabled. This disables DOP clock gating
for SKL GT4.

Cc: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 48785ef..6dee3b6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
+
+	if (IS_SKL_GT4(dev_priv)) {
+		/* WaDisableDopClockGating */
+		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
+			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	}
 }
 
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915: enable WaDisableDopClkGating for SKL GT4

[Patchwork]

== Series Details ==

Series: drm/i915: enable WaDisableDopClkGating for SKL GT4
URL   : https://patchwork.freedesktop.org/series/28068/
State : success

== Summary ==

Series 28068v1 drm/i915: enable WaDisableDopClkGating for SKL GT4
https://patchwork.freedesktop.org/api/1.0/series/28068/revisions/1/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                fail       -> PASS       (fi-snb-2600) fdo#100007
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-pnv-d510) fdo#101597 +1
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (fi-byt-j1900) fdo#101705

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u     total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  time:442s
fi-bdw-gvtdvm    total:280  pass:266  dwarn:0   dfail:0   fail:0   skip:14  time:431s
fi-blb-e6850     total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  time:359s
fi-bsw-n3050     total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  time:547s
fi-bxt-j4205     total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  time:517s
fi-byt-j1900     total:280  pass:256  dwarn:0   dfail:0   fail:0   skip:24  time:496s
fi-byt-n2820     total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  time:496s
fi-glk-2a        total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  time:601s
fi-hsw-4770      total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  time:444s
fi-hsw-4770r     total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  time:427s
fi-ilk-650       total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  time:416s
fi-ivb-3520m     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:504s
fi-ivb-3770      total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:477s
fi-kbl-7500u     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:471s
fi-kbl-7560u     total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:586s
fi-kbl-r         total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:583s
fi-pnv-d510      total:280  pass:222  dwarn:3   dfail:0   fail:0   skip:55  time:568s
fi-skl-6260u     total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:462s
fi-skl-6700hq    total:280  pass:263  dwarn:0   dfail:0   fail:0   skip:17  time:583s
fi-skl-6700k     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:472s
fi-skl-6770hq    total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:477s
fi-skl-gvtdvm    total:280  pass:267  dwarn:0   dfail:0   fail:0   skip:13  time:440s
fi-skl-x1585l    total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  time:468s
fi-snb-2520m     total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  time:550s
fi-snb-2600      total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  time:407s

8760573807154dd40cdcd873cc87aa0c347e9742 drm-tip: 2017y-07m-29d-00h-50m-50s UTC integration manifest
6cdf80a34d1b drm/i915: enable WaDisableDopClkGating for SKL GT4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5297/
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Re: [PATCH] drm/i915: enable WaDisableDopClkGating for SKL GT4

[David Weinehall]

On Sat, Jul 29, 2017 at 10:29:00AM +0530, Praveen Paneri wrote:
> This WA is required when decopled frequencies for slice
> and unslice are enabled. This disables DOP clock gating
> for SKL GT4.
> 
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>

Tested to fix hangs on GT4; I would suggest applying this fix
for all GEN 9 platforms though, not just SKL GT4e, even if that
platform is the only one where we've been able to trigger the
issue so far.

Anyway, the fix works and is correct, so:

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 48785ef..6dee3b6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>  	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_DISABLE_DUMMY0);
> +
> +	if (IS_SKL_GT4(dev_priv)) {
> +		/* WaDisableDopClockGating */
> +		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
> +			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> +	}
>  }
>  
>  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
> 
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[PATCH] drm/i915: enable WaDisableDopClkGating for gen9

[Praveen Paneri]

This WA is required when decoupled frequencies for slice and unslice
are enabled. This disables DOP clock gating for gen9.

v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
    the hang issue is originally reported) to avoid rare hangs (David)

Cc: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3fc42aa..e369d77 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
+
+	if (IS_GEN9(dev_priv)) {
+		/* WaDisableDopClockGating */
+		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
+			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	}
 }
 
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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✗ Fi.CI.BAT: warning for drm/i915: enable WaDisableDopClkGating for SKL GT4 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: enable WaDisableDopClkGating for SKL GT4 (rev2)
URL   : https://patchwork.freedesktop.org/series/28068/
State : warning

== Summary ==

Series 28068v2 drm/i915: enable WaDisableDopClkGating for SKL GT4
https://patchwork.freedesktop.org/api/1.0/series/28068/revisions/2/mbox/

Test kms_busy:
        Subgroup basic-flip-default-a:
                pass       -> DMESG-WARN (fi-skl-6700hq) fdo#101144
        Subgroup basic-flip-default-b:
                pass       -> FAIL       (fi-skl-6700hq) fdo#101518 +31
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                pass       -> SKIP       (fi-skl-6700hq)
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> SKIP       (fi-skl-6700hq) fdo#99739
        Subgroup basic-plain-flip:
                pass       -> SKIP       (fi-skl-6700hq)
Test kms_frontbuffer_tracking:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-6700hq)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-pnv-d510) fdo#101597
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                pass       -> SKIP       (fi-skl-6700hq)
        Subgroup basic-rte:
                pass       -> SKIP       (fi-skl-6700hq)

fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#101518 https://bugs.freedesktop.org/show_bug.cgi?id=101518
fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u     total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  time:446s
fi-bdw-gvtdvm    total:280  pass:266  dwarn:0   dfail:0   fail:0   skip:14  time:430s
fi-blb-e6850     total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  time:352s
fi-bsw-n3050     total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  time:530s
fi-bxt-j4205     total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  time:513s
fi-byt-n2820     total:280  pass:251  dwarn:1   dfail:0   fail:0   skip:28  time:499s
fi-glk-2a        total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  time:605s
fi-hsw-4770      total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  time:439s
fi-hsw-4770r     total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  time:418s
fi-ilk-650       total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  time:418s
fi-ivb-3520m     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:502s
fi-ivb-3770      total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:481s
fi-kbl-7500u     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:468s
fi-kbl-7560u     total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:572s
fi-kbl-r         total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:585s
fi-pnv-d510      total:280  pass:223  dwarn:2   dfail:0   fail:0   skip:55  time:573s
fi-skl-6260u     total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:459s
fi-skl-6700hq    total:280  pass:224  dwarn:1   dfail:0   fail:30  skip:24  time:320s
fi-skl-6700k     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:468s
fi-skl-6770hq    total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:471s
fi-skl-gvtdvm    total:280  pass:267  dwarn:0   dfail:0   fail:0   skip:13  time:437s
fi-skl-x1585l    total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  time:480s
fi-snb-2520m     total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  time:551s
fi-snb-2600      total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  time:403s

fcb630a80579faf6d12ee62cb49bd7a4acff41e6 drm-tip: 2017y-08m-01d-17h-14m-57s UTC integration manifest
a37eed7cdd7b drm/i915: enable WaDisableDopClkGating for gen9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5313/
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Re: [PATCH] drm/i915: enable WaDisableDopClkGating for gen9

[Rodrigo Vivi]

On Wed, Aug 2, 2017 at 10:34 AM, Praveen Paneri
<praveen.paneri@intel.com> wrote:
> This WA is required when decoupled frequencies for slice and unslice
> are enabled. This disables DOP clock gating for gen9.
>
> v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
>     the hang issue is originally reported) to avoid rare hangs (David)
>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3fc42aa..e369d77 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>                    ILK_DPFC_DISABLE_DUMMY0);
> +
> +       if (IS_GEN9(dev_priv)) {

I believe we should go with IS_SKYLAKE(dev_priv)

Bspec only list this Wa for:
BDW: ALL
CHV: UNTIL A7

WaDatabase only list this to:
SKL: SIWA_FOREVER
BDW: SIWA_FOREVER
CHV: SIWA_CHV_UNTIL_A7
SNB: SIWA_UNTIL_GT_MOBILE_D0

> +               /* WaDisableDopClockGating */
> +               I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
> +                          & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> +       }
>  }
>
>  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH] drm/i915: enable WaDisableDopClkGating for gen9

[David Weinehall]

On Wed, Aug 02, 2017 at 12:24:33PM -0700, Rodrigo Vivi wrote:
> On Wed, Aug 2, 2017 at 10:34 AM, Praveen Paneri
> <praveen.paneri@intel.com> wrote:
> > This WA is required when decoupled frequencies for slice and unslice
> > are enabled. This disables DOP clock gating for gen9.
> >
> > v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
> >     the hang issue is originally reported) to avoid rare hangs (David)
> >
> > Cc: David Weinehall <david.weinehall@linux.intel.com>
> > Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3fc42aa..e369d77 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> >         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
> >         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >                    ILK_DPFC_DISABLE_DUMMY0);
> > +
> > +       if (IS_GEN9(dev_priv)) {
> 
> I believe we should go with IS_SKYLAKE(dev_priv)

Based on the info below that sounds sensible, yes. Good find.

> Bspec only list this Wa for:
> BDW: ALL
> CHV: UNTIL A7
> 
> WaDatabase only list this to:
> SKL: SIWA_FOREVER
> BDW: SIWA_FOREVER
> CHV: SIWA_CHV_UNTIL_A7
> SNB: SIWA_UNTIL_GT_MOBILE_D0

Do we currently apply the fix on SNB?

I must say that the list of platforms seem a bit arbitrary though; it
seems weird that an issue on Sandybridge would disappear on Ivybridge
and Haswell, then resurface again on Broadwell...

Then again, it happens far too often in software land, so it might very
well be that it happens in hardware land too.


Kind regards, David
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[PATCH v3] drm/i915: enable WaDisableDopClkGating for skl

[Praveen Paneri]

This WA is required when decoupled frequencies for slice and unslice
are enabled. This disables DOP clock gating for skl.

v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
    the hang issue is originally reported) to avoid rare hangs (David)
v3: as per WaDatabase, enable it only for SKL (Rodrigo)

Cc: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3fc42aa..1c6bc08 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -60,7 +60,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 misccpctl;
 
-	if (IS_SKL_GT4(dev_priv))
+	if (IS_SKYLAKE(dev_priv))
 	{
 		/* WaTempDisableDOPClkGating: */
 		misccpctl = I915_READ(GEN7_MISCCPCTL);
@@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
+
+	if (IS_GEN9(dev_priv)) {
+		/* WaDisableDopClockGating */
+		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
+			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	}
 }
 
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH v3] drm/i915: enable WaDisableDopClkGating for skl

[Praveen Paneri]

Just realized that I have sent out a wrong patch. Plz ignore this.
Gonna send the correct one in some time.

Thanks,
Praveen
Thanks,
Praveen


On Thu, Aug 3, 2017 at 7:21 PM, Praveen Paneri <praveen.paneri@intel.com> wrote:
> This WA is required when decoupled frequencies for slice and unslice
> are enabled. This disables DOP clock gating for skl.
>
> v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
>     the hang issue is originally reported) to avoid rare hangs (David)
> v3: as per WaDatabase, enable it only for SKL (Rodrigo)
>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3fc42aa..1c6bc08 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -60,7 +60,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>         u32 misccpctl;
>
> -       if (IS_SKL_GT4(dev_priv))
> +       if (IS_SKYLAKE(dev_priv))
>         {
>                 /* WaTempDisableDOPClkGating: */
>                 misccpctl = I915_READ(GEN7_MISCCPCTL);
> @@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>                    ILK_DPFC_DISABLE_DUMMY0);
> +
> +       if (IS_GEN9(dev_priv)) {
> +               /* WaDisableDopClockGating */
> +               I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
> +                          & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> +       }
>  }
>
>  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> --
> 1.9.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH] drm/i915: enable WaDisableDopClkGating for gen9

[Rodrigo Vivi]

On Thu, Aug 3, 2017 at 4:13 AM, David Weinehall
<david.weinehall@linux.intel.com> wrote:
> On Wed, Aug 02, 2017 at 12:24:33PM -0700, Rodrigo Vivi wrote:
>> On Wed, Aug 2, 2017 at 10:34 AM, Praveen Paneri
>> <praveen.paneri@intel.com> wrote:
>> > This WA is required when decoupled frequencies for slice and unslice
>> > are enabled. This disables DOP clock gating for gen9.
>> >
>> > v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
>> >     the hang issue is originally reported) to avoid rare hangs (David)
>> >
>> > Cc: David Weinehall <david.weinehall@linux.intel.com>
>> > Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>> > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>> >  1 file changed, 6 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index 3fc42aa..e369d77 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>> >         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>> >         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> >                    ILK_DPFC_DISABLE_DUMMY0);
>> > +
>> > +       if (IS_GEN9(dev_priv)) {
>>
>> I believe we should go with IS_SKYLAKE(dev_priv)
>
> Based on the info below that sounds sensible, yes. Good find.
>
>> Bspec only list this Wa for:
>> BDW: ALL
>> CHV: UNTIL A7
>>
>> WaDatabase only list this to:
>> SKL: SIWA_FOREVER
>> BDW: SIWA_FOREVER
>> CHV: SIWA_CHV_UNTIL_A7
>> SNB: SIWA_UNTIL_GT_MOBILE_D0
>
> Do we currently apply the fix on SNB?

I guess we are not...

>
> I must say that the list of platforms seem a bit arbitrary though; it
> seems weird that an issue on Sandybridge would disappear on Ivybridge
> and Haswell, then resurface again on Broadwell...
>
> Then again, it happens far too often in software land, so it might very
> well be that it happens in hardware land too.

I agree... that's so odd...

specially because this bit starts with GEN7...
let's just ignore this snb for now unless we find a good reason to
investigate back there...

>
>
> Kind regards, David



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[PATCH v3] drm/i915: enable WaDisableDopClkGating for skl

[Praveen Paneri]

This WA is required when decoupled frequencies for slice and unslice
are enabled. This disables DOP clock gating for skl.

v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
    the hang issue is originally reported) to avoid rare hangs (David)
v3: as per WaDatabase, enable it only for SKL (Rodrigo)

Cc: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 90c2d60..a880c94 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
+
+	if (IS_SKYLAKE(dev_priv)) {
+		/* WaDisableDopClockGating */
+		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
+			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	}
 }
 
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH v3] drm/i915: enable WaDisableDopClkGating for skl

[Rodrigo Vivi]

On Thu, Aug 3, 2017 at 10:32 AM, Praveen Paneri
<praveen.paneri@intel.com> wrote:
> This WA is required when decoupled frequencies for slice and unslice
> are enabled. This disables DOP clock gating for skl.
>
> v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
>     the hang issue is originally reported) to avoid rare hangs (David)
> v3: as per WaDatabase, enable it only for SKL (Rodrigo)

I think this deserved a "v4" mark to avoid confusions when checking
for the CI results.

But I will pay attention on results for 170168 which is the latest one
and if it pass I can merge that for you.
https://patchwork.freedesktop.org/patch/170168/

>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 90c2d60..a880c94 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>                    ILK_DPFC_DISABLE_DUMMY0);
> +
> +       if (IS_SKYLAKE(dev_priv)) {
> +               /* WaDisableDopClockGating */
> +               I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
> +                          & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> +       }
>  }
>
>  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH v3] drm/i915: enable WaDisableDopClkGating for skl

[Praveen Paneri]

On Thu, Aug 3, 2017 at 11:07 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> On Thu, Aug 3, 2017 at 10:32 AM, Praveen Paneri
> <praveen.paneri@intel.com> wrote:
>> This WA is required when decoupled frequencies for slice and unslice
>> are enabled. This disables DOP clock gating for skl.
>>
>> v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
>>     the hang issue is originally reported) to avoid rare hangs (David)
>> v3: as per WaDatabase, enable it only for SKL (Rodrigo)
>
> I think this deserved a "v4" mark to avoid confusions when checking
> for the CI results.
Will keep this in mind going fwd
>
> But I will pay attention on results for 170168 which is the latest one
> and if it pass I can merge that for you.
> https://patchwork.freedesktop.org/patch/170168/
that will be great

Thanks,
Praveen
>
>>
>> Cc: David Weinehall <david.weinehall@linux.intel.com>
>> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 90c2d60..a880c94 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>>         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>>         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>>                    ILK_DPFC_DISABLE_DUMMY0);
>> +
>> +       if (IS_SKYLAKE(dev_priv)) {
>> +               /* WaDisableDopClockGating */
>> +               I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
>> +                          & ~GEN7_DOP_CLOCK_GATE_ENABLE);
>> +       }
>>  }
>>
>>  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✓ Fi.CI.BAT: success for drm/i915: enable WaDisableDopClkGating for SKL GT4 (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: enable WaDisableDopClkGating for SKL GT4 (rev4)
URL   : https://patchwork.freedesktop.org/series/28068/
State : success

== Summary ==

Series 28068v4 drm/i915: enable WaDisableDopClkGating for SKL GT4
https://patchwork.freedesktop.org/api/1.0/series/28068/revisions/4/mbox/

Test kms_busy:
        Subgroup basic-flip-default-a:
                dmesg-warn -> PASS       (fi-skl-6700hq) fdo#101144
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                fail       -> PASS       (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-pnv-d510) fdo#101597

fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u     total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  time:446s
fi-blb-e6850     total:280  pass:225  dwarn:1   dfail:0   fail:0   skip:54  time:355s
fi-bsw-n3050     total:280  pass:244  dwarn:0   dfail:0   fail:0   skip:36  time:544s
fi-bxt-j4205     total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  time:507s
fi-byt-j1900     total:280  pass:255  dwarn:1   dfail:0   fail:0   skip:24  time:516s
fi-byt-n2820     total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-glk-2a        total:280  pass:261  dwarn:0   dfail:0   fail:0   skip:19  time:609s
fi-hsw-4770      total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  time:440s
fi-hsw-4770r     total:280  pass:264  dwarn:0   dfail:0   fail:0   skip:16  time:420s
fi-ilk-650       total:280  pass:230  dwarn:0   dfail:0   fail:0   skip:50  time:415s
fi-ivb-3520m     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:502s
fi-ivb-3770      total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:473s
fi-kbl-7500u     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:467s
fi-kbl-7560u     total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:580s
fi-kbl-r         total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:585s
fi-pnv-d510      total:280  pass:223  dwarn:2   dfail:0   fail:0   skip:55  time:558s
fi-skl-6260u     total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:463s
fi-skl-6700hq    total:280  pass:263  dwarn:0   dfail:0   fail:0   skip:17  time:594s
fi-skl-6700k     total:280  pass:262  dwarn:0   dfail:0   fail:0   skip:18  time:478s
fi-skl-6770hq    total:280  pass:270  dwarn:0   dfail:0   fail:0   skip:10  time:478s
fi-skl-gvtdvm    total:280  pass:267  dwarn:0   dfail:0   fail:0   skip:13  time:435s
fi-skl-x1585l    total:280  pass:269  dwarn:0   dfail:0   fail:0   skip:11  time:473s
fi-snb-2520m     total:280  pass:252  dwarn:0   dfail:0   fail:0   skip:28  time:542s
fi-snb-2600      total:280  pass:251  dwarn:0   dfail:0   fail:0   skip:29  time:405s
fi-bdw-gvtdvm failed to connect after reboot

e5a8ef89620771f5091859ab859a2ca2a464aca1 drm-tip: 2017y-08m-03d-10h-20m-34s UTC integration manifest
960e5718f5d0 drm/i915: enable WaDisableDopClkGating for skl

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5320/
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Re: [PATCH v3] drm/i915: enable WaDisableDopClkGating for skl

[Rodrigo Vivi]

merged to dinq.
thanks for patch and review

On Thu, Aug 3, 2017 at 10:41 AM, Praveen Paneri <paneri@gmail.com> wrote:
> On Thu, Aug 3, 2017 at 11:07 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>> On Thu, Aug 3, 2017 at 10:32 AM, Praveen Paneri
>> <praveen.paneri@intel.com> wrote:
>>> This WA is required when decoupled frequencies for slice and unslice
>>> are enabled. This disables DOP clock gating for skl.
>>>
>>> v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
>>>     the hang issue is originally reported) to avoid rare hangs (David)
>>> v3: as per WaDatabase, enable it only for SKL (Rodrigo)
>>
>> I think this deserved a "v4" mark to avoid confusions when checking
>> for the CI results.
> Will keep this in mind going fwd
>>
>> But I will pay attention on results for 170168 which is the latest one
>> and if it pass I can merge that for you.
>> https://patchwork.freedesktop.org/patch/170168/
> that will be great
>
> Thanks,
> Praveen
>>
>>>
>>> Cc: David Weinehall <david.weinehall@linux.intel.com>
>>> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>>> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 90c2d60..a880c94 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>>>         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>>>         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>>>                    ILK_DPFC_DISABLE_DUMMY0);
>>> +
>>> +       if (IS_SKYLAKE(dev_priv)) {
>>> +               /* WaDisableDopClockGating */
>>> +               I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
>>> +                          & ~GEN7_DOP_CLOCK_GATE_ENABLE);
>>> +       }
>>>  }
>>>
>>>  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
>>> --
>>> 1.9.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH] drm/i915: enable WaDisableDopClkGating for gen9

[Ville Syrjälä]

On Thu, Aug 03, 2017 at 10:31:11AM -0700, Rodrigo Vivi wrote:
> On Thu, Aug 3, 2017 at 4:13 AM, David Weinehall
> <david.weinehall@linux.intel.com> wrote:
> > On Wed, Aug 02, 2017 at 12:24:33PM -0700, Rodrigo Vivi wrote:
> >> On Wed, Aug 2, 2017 at 10:34 AM, Praveen Paneri
> >> <praveen.paneri@intel.com> wrote:
> >> > This WA is required when decoupled frequencies for slice and unslice
> >> > are enabled. This disables DOP clock gating for gen9.
> >> >
> >> > v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
> >> >     the hang issue is originally reported) to avoid rare hangs (David)
> >> >
> >> > Cc: David Weinehall <david.weinehall@linux.intel.com>
> >> > Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> >> > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> >> >  1 file changed, 6 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> > index 3fc42aa..e369d77 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> >> >         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
> >> >         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >> >                    ILK_DPFC_DISABLE_DUMMY0);
> >> > +
> >> > +       if (IS_GEN9(dev_priv)) {
> >>
> >> I believe we should go with IS_SKYLAKE(dev_priv)
> >
> > Based on the info below that sounds sensible, yes. Good find.
> >
> >> Bspec only list this Wa for:
> >> BDW: ALL
> >> CHV: UNTIL A7
> >>
> >> WaDatabase only list this to:
> >> SKL: SIWA_FOREVER
> >> BDW: SIWA_FOREVER
> >> CHV: SIWA_CHV_UNTIL_A7
> >> SNB: SIWA_UNTIL_GT_MOBILE_D0
> >
> > Do we currently apply the fix on SNB?
> 
> I guess we are not...
> 
> >
> > I must say that the list of platforms seem a bit arbitrary though; it
> > seems weird that an issue on Sandybridge would disappear on Ivybridge
> > and Haswell, then resurface again on Broadwell...
> >
> > Then again, it happens far too often in software land, so it might very
> > well be that it happens in hardware land too.
> 
> I agree... that's so odd...
> 
> specially because this bit starts with GEN7...

IIRC the register and bit do exist on SNB as well. Our defines are
simply named incorrectly for whatever reason.

> let's just ignore this snb for now unless we find a good reason to
> investigate back there...
> 
> >
> >
> > Kind regards, David
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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