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From: Christoph Hellwig <hch@infradead.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Huacai Chen <chenhc@lemote.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Fuxin Zhang <zhangfx@lemote.com>,
	linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	stable@vger.kernel.org
Subject: Re: [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode
Date: Mon, 18 Sep 2017 08:51:34 -0700	[thread overview]
Message-ID: <20170918155134.GC16672@infradead.org> (raw)
In-Reply-To: <601437ae-2860-c48a-aa7c-4da37aeb6256@arm.com>

On Mon, Sep 18, 2017 at 10:44:54AM +0100, Robin Murphy wrote:
> On 18/09/17 05:22, Huacai Chen wrote:
> > In non-coherent DMA mode, kernel uses cache flushing operations to
> > maintain I/O coherency, so the dmapool objects should be aligned to
> > ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least
> > on MIPS:
> > 
> > 	Step 1, dma_map_single
> > 	Step 2, cache_invalidate (no writeback)
> > 	Step 3, dma_from_device
> > 	Step 4, dma_unmap_single
> 
> This is a massive red warning flag for the whole series, because DMA
> pools don't work like that. At best, this will do nothing, and at worst
> it is papering over egregious bugs elsewhere. Streaming mappings of
> coherent allocations means completely broken code.

Oh, I hadn't even seen that part.  Yes, dma coherent (and pool)
allocations must never be used for streaming mappings.  I wish we'd
have some debug infrastructure to warn on such uses.

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Huacai Chen <chenhc@lemote.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Fuxin Zhang <zhangfx@lemote.com>,
	linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	stable@vger.kernel.org
Subject: Re: [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode
Date: Mon, 18 Sep 2017 08:51:34 -0700	[thread overview]
Message-ID: <20170918155134.GC16672@infradead.org> (raw)
In-Reply-To: <601437ae-2860-c48a-aa7c-4da37aeb6256@arm.com>

On Mon, Sep 18, 2017 at 10:44:54AM +0100, Robin Murphy wrote:
> On 18/09/17 05:22, Huacai Chen wrote:
> > In non-coherent DMA mode, kernel uses cache flushing operations to
> > maintain I/O coherency, so the dmapool objects should be aligned to
> > ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least
> > on MIPS:
> > 
> > 	Step 1, dma_map_single
> > 	Step 2, cache_invalidate (no writeback)
> > 	Step 3, dma_from_device
> > 	Step 4, dma_unmap_single
> 
> This is a massive red warning flag for the whole series, because DMA
> pools don't work like that. At best, this will do nothing, and at worst
> it is papering over egregious bugs elsewhere. Streaming mappings of
> coherent allocations means completely broken code.

Oh, I hadn't even seen that part.  Yes, dma coherent (and pool)
allocations must never be used for streaming mappings.  I wish we'd
have some debug infrastructure to warn on such uses.

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  reply	other threads:[~2017-09-18 15:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-18  4:22 [PATCH V5 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode Huacai Chen
2017-09-18  4:22 ` Huacai Chen
2017-09-18  5:22 ` Christoph Hellwig
2017-09-18  5:22   ` Christoph Hellwig
2017-09-18  6:55   ` [PATCH V5 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent " 陈华才
2017-09-18  9:44 ` [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent " Robin Murphy
2017-09-18  9:44   ` Robin Murphy
2017-09-18 15:51   ` Christoph Hellwig [this message]
2017-09-18 15:51     ` Christoph Hellwig
2017-09-19  2:23     ` [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent " 陈华才
2017-09-18 15:45 ` [PATCH V5 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent " Christoph Hellwig
2017-09-18 15:45   ` Christoph Hellwig

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