[U-Boot] [PATCH 1/6] ARM: rmobile: dts: Add EHCI USB nodes to r8a7796

[U-Boot] [PATCH 1/6] ARM: rmobile: dts: Add EHCI USB nodes to r8a7796

[Marek Vasut]

The R8A7796 EHCI USB nodes are missing from r8a7796 dtsi, add them.
These nodes don't come from mainline Linux, yet the DT binding is
similar enough to R8A7795 which already has those in mainline and
once the nodes hit mainline, this DT should be resynched.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 arch/arm/dts/r8a7796.dtsi | 51 ++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi
index c0cb4a952f..7e3b1d82a1 100644
--- a/arch/arm/dts/r8a7796.dtsi
+++ b/arch/arm/dts/r8a7796.dtsi
@@ -1106,7 +1106,17 @@
 		};
 
 		hsusb: usb at e6590000 {
-			/* placeholder */
+			compatible = "renesas,usbhs-r8a7796",
+				     "renesas,rcar-gen3-usbhs";
+			reg = <0 0xe6590000 0 0x100>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 704>;
+			renesas,buswait = <11>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 704>;
+			status = "disabled";
 		};
 
 		xhci0: usb at ee000000 {
@@ -1118,11 +1128,27 @@
 		};
 
 		ehci0: usb at ee080100 {
-			/* placeholder */
+			compatible = "generic-ehci";
+			reg = <0 0xee080100 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			status = "disabled";
 		};
 
 		usb2_phy0: usb-phy at ee080200 {
-			/* placeholder */
+			compatible = "renesas,usb2-phy-r8a7796",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee080200 0 0x700>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			#phy-cells = <0>;
+			status = "disabled";
 		};
 
 		ohci1: usb at ee0a0000 {
@@ -1130,11 +1156,26 @@
 		};
 
 		ehci1: usb at ee0a0100 {
-			/* placeholder */
+			compatible = "generic-ehci";
+			reg = <0 0xee0a0100 0 0x100>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>;
+			phys = <&usb2_phy1>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			status = "disabled";
 		};
 
 		usb2_phy1: usb-phy at ee0a0200 {
-			/* placeholder */
+			compatible = "renesas,usb2-phy-r8a7796",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee0a0200 0 0x700>;
+			clocks = <&cpg CPG_MOD 702>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			#phy-cells = <0>;
+			status = "disabled";
 		};
 
 		sdhi0: sd at ee100000 {
-- 
2.11.0

[U-Boot] [PATCH 2/6] ARM: rmobile: Move HSUSB configuration to board on Salvator-X

[Marek Vasut]

In order to use ehci-generic driver, move the configuration of HSUSB
block into the board file. This configuration should not have been in
the Gen3 EHCI USB driver in the first place, so move it to the board
file until there is a proper infrastructure and driver for the HSUSB
block.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 board/renesas/salvator-x/salvator-x.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index e260117802..37fcbbd448 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -55,6 +55,7 @@ void s_init(void)
 #define SD1_MSTP313		BIT(13)
 #define SD2_MSTP312		BIT(12)	/* either MMC0 */
 #define SD3_MSTP311		BIT(11)	/* either MMC1 */
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
 
 #define SD0CKCR			0xE6150074
 #define SD1CKCR			0xE6150078
@@ -92,6 +93,13 @@ int board_early_init_f(void)
 /* -/W 32 Power resume control register 2 (3DG) */
 #define	SYSC_PWRONCR2	0xE618010C
 
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
 int board_init(void)
 {
 	/* adress of boot parameters */
@@ -116,6 +124,14 @@ int board_init(void)
 	/* USB1 pull-up */
 	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
 #ifdef CONFIG_RENESAS_RAVB
 	/* EtherAVB Enable */
 	/* GPSR2 */
-- 
2.11.0

[U-Boot] [PATCH 3/6] ARM: rmobile: Move HSUSB configuration to board on ULCB

[Marek Vasut]

In order to use ehci-generic driver, move the configuration of HSUSB
block into the board file. This configuration should not have been in
the Gen3 EHCI USB driver in the first place, so move it to the board
file until there is a proper infrastructure and driver for the HSUSB
block.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 board/renesas/ulcb/ulcb.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index dc23228f4f..578b14be7b 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -53,6 +53,7 @@ void s_init(void)
 #define SD0_MSTP314		BIT(14)
 #define SD1_MSTP313		BIT(13)
 #define SD2_MSTP312		BIT(12)	/* either MMC0 */
+#define HSUSB_MSTP704		BIT(4)	/* HSUSB */
 
 #define SD0CKCR			0xE6150074
 #define SD1CKCR			0xE6150078
@@ -90,6 +91,13 @@ int board_early_init_f(void)
 /* -/W 32 Power resume control register 2 (3DG) */
 #define	SYSC_PWRONCR2	0xE618010C
 
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS			0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
+#define HSUSB_REG_UGCTRL2		0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
+
 int board_init(void)
 {
 	/* adress of boot parameters */
@@ -105,6 +113,14 @@ int board_init(void)
 	/* USB1 pull-up */
 	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
+	/* Configure the HSUSB block */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+	/* Choice USB0SEL */
+	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+	/* low power status */
+	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
 #ifdef CONFIG_RENESAS_RAVB
 	/* EtherAVB Enable */
 	/* GPSR2 */
-- 
2.11.0

[U-Boot] [PATCH 4/6] ARM: rmobile: Enable EHCI generic on Salvator-X

[Marek Vasut]

Enable the EHCI generic driver, which is superior to ad-hoc SoC specific one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 configs/r8a7795_salvator-x_defconfig | 1 +
 configs/r8a7796_salvator-x_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig
index 271b15da42..585eb64973 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -34,5 +34,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig
index 921fdf77ff..302e8999a6 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -35,5 +35,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
-- 
2.11.0

[U-Boot] [PATCH 5/6] ARM: rmobile: Enable EHCI generic on ULCB

[Marek Vasut]

Enable the EHCI generic driver, which is superior to ad-hoc SoC specific one.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 configs/r8a7795_ulcb_defconfig | 1 +
 configs/r8a7796_ulcb_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index 832998083a..6f30c8d870 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -30,5 +30,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index 5846147348..2ff91dfbf3 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -31,5 +31,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
-- 
2.11.0

[U-Boot] [PATCH 6/6] usb: Drop the EHCI RCar Gen3

[Marek Vasut]

Since we use EHCI generic driver on RCar Gen3 , this driver is useless.
Remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 drivers/usb/host/Kconfig          |   8 ---
 drivers/usb/host/Makefile         |   1 -
 drivers/usb/host/ehci-rcar_gen3.c | 106 --------------------------------------
 3 files changed, 115 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-rcar_gen3.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f797a2568c..f5f19ed775 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -157,14 +157,6 @@ config USB_EHCI_PCI
 	help
 	  Enables support for the PCI-based EHCI controller.
 
-config USB_EHCI_RCAR_GEN3
-	bool "Support for Renesas RCar M3/H3 EHCI USB controller"
-	depends on RCAR_GEN3
-	default y
-	---help---
-	  Enables support for the on-chip EHCI controller on Renesas
-	  R8A7795 and R8A7796 SoCs.
-
 config USB_EHCI_ZYNQ
 	bool "Support for Xilinx Zynq on-chip EHCI USB controller"
 	depends on ARCH_ZYNQ
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 29afb7cf1d..83903fcf99 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
-obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
diff --git a/drivers/usb/host/ehci-rcar_gen3.c b/drivers/usb/host/ehci-rcar_gen3.c
deleted file mode 100644
index 525e7f3573..0000000000
--- a/drivers/usb/host/ehci-rcar_gen3.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * drivers/usb/host/ehci-rcar_gen3.
- *	This file is EHCI HCD (Host Controller Driver) for USB.
- *
- * Copyright (C) 2015-2017 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <wait_bit.h>
-#include <asm/io.h>
-#include <usb/ehci-ci.h>
-#include "ehci.h"
-
-#define RCAR_GEN3_USB_BASE(n)	(0xEE080000 + ((n) * 0x20000))
-
-#define EHCI_USBCMD		0x120
-
-#define CORE_SPD_RSM_TIMSET	0x30c
-#define CORE_OC_TIMSET		0x310
-
-/* Register offset */
-#define AHB_OFFSET		0x200
-
-#define BASE_HSUSB		0xE6590000
-#define REG_LPSTS		(BASE_HSUSB + 0x0102)	/* 16bit */
-#define SUSPM			0x4000
-#define SUSPM_NORMAL		BIT(14)
-#define REG_UGCTRL2		(BASE_HSUSB + 0x0184)	/* 32bit */
-#define USB0SEL			0x00000030
-#define USB0SEL_EHCI		0x00000010
-
-#define SMSTPCR7		0xE615014C
-#define SMSTPCR700		BIT(0)	/* EHCI3 */
-#define SMSTPCR701		BIT(1)	/* EHCI2 */
-#define SMSTPCR702		BIT(2)	/* EHCI1 */
-#define SMSTPCR703		BIT(3)	/* EHCI0 */
-#define SMSTPCR704		BIT(4)	/* HSUSB */
-
-#define AHB_PLL_RST		BIT(1)
-
-#define USBH_INTBEN		BIT(2)
-#define USBH_INTAEN		BIT(1)
-
-#define AHB_INT_ENABLE		0x200
-#define AHB_USBCTR		0x20c
-
-int ehci_hcd_stop(int index)
-{
-#if defined(CONFIG_R8A7795)
-	const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
-#else
-	const u32 mask = SMSTPCR703 | SMSTPCR702;
-#endif
-	const u32 base = RCAR_GEN3_USB_BASE(index);
-	int ret;
-
-	/* Reset EHCI */
-	setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
-	ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
-			   CMD_RESET, false, 10, true);
-	if (ret) {
-		printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
-		       index, ret);
-	}
-
-	setbits_le32(SMSTPCR7, BIT(3 - index));
-
-	if ((readl(SMSTPCR7) & mask) == mask)
-		setbits_le32(SMSTPCR7, SMSTPCR704);
-
-	return 0;
-}
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	const void __iomem *base =
-		(void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
-	struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
-
-	clrbits_le32(SMSTPCR7, BIT(3 - index));
-	clrbits_le32(SMSTPCR7, SMSTPCR704);
-
-	*hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
-	*hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	/* Enable interrupt */
-	setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
-	writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
-	writel(0x000209ab, base + CORE_OC_TIMSET);
-
-	/* Choice USB0SEL */
-	clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
-
-	/* Clock & Reset */
-	clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
-
-	/* low power status */
-	clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
-
-	return 0;
-}
-- 
2.11.0

[U-Boot] [PATCH 1/6] ARM: rmobile: dts: Add EHCI USB nodes to r8a7796

[Marek Vasut]

The R8A7796 EHCI USB nodes are missing from r8a7796 dtsi, add them.
These nodes don't come from mainline Linux, yet the DT binding is
similar enough to R8A7795 which already has those in mainline and
once the nodes hit mainline, this DT should be resynched.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 arch/arm/dts/r8a7796.dtsi | 51 ++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi
index c0cb4a952f..7e3b1d82a1 100644
--- a/arch/arm/dts/r8a7796.dtsi
+++ b/arch/arm/dts/r8a7796.dtsi
@@ -1106,7 +1106,17 @@
 		};
 
 		hsusb: usb at e6590000 {
-			/* placeholder */
+			compatible = "renesas,usbhs-r8a7796",
+				     "renesas,rcar-gen3-usbhs";
+			reg = <0 0xe6590000 0 0x100>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 704>;
+			renesas,buswait = <11>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 704>;
+			status = "disabled";
 		};
 
 		xhci0: usb at ee000000 {
@@ -1118,11 +1128,27 @@
 		};
 
 		ehci0: usb at ee080100 {
-			/* placeholder */
+			compatible = "generic-ehci";
+			reg = <0 0xee080100 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			status = "disabled";
 		};
 
 		usb2_phy0: usb-phy at ee080200 {
-			/* placeholder */
+			compatible = "renesas,usb2-phy-r8a7796",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee080200 0 0x700>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			#phy-cells = <0>;
+			status = "disabled";
 		};
 
 		ohci1: usb at ee0a0000 {
@@ -1130,11 +1156,26 @@
 		};
 
 		ehci1: usb at ee0a0100 {
-			/* placeholder */
+			compatible = "generic-ehci";
+			reg = <0 0xee0a0100 0 0x100>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>;
+			phys = <&usb2_phy1>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			status = "disabled";
 		};
 
 		usb2_phy1: usb-phy at ee0a0200 {
-			/* placeholder */
+			compatible = "renesas,usb2-phy-r8a7796",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee0a0200 0 0x700>;
+			clocks = <&cpg CPG_MOD 702>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			#phy-cells = <0>;
+			status = "disabled";
 		};
 
 		sdhi0: sd at ee100000 {
-- 
2.11.0

[U-Boot] [PATCH 6/6] usb: Drop the EHCI RCar Gen3

[Marek Vasut]

Since we use EHCI generic driver on RCar Gen3 , this driver is useless.
Remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 drivers/usb/host/Kconfig          |   8 ---
 drivers/usb/host/Makefile         |   1 -
 drivers/usb/host/ehci-rcar_gen3.c | 106 --------------------------------------
 3 files changed, 115 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-rcar_gen3.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index eb035a476b..5438feb8f5 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -148,14 +148,6 @@ config USB_EHCI_PCI
 	help
 	  Enables support for the PCI-based EHCI controller.
 
-config USB_EHCI_RCAR_GEN3
-	bool "Support for Renesas RCar M3/H3 EHCI USB controller"
-	depends on RCAR_GEN3
-	default y
-	---help---
-	  Enables support for the on-chip EHCI controller on Renesas
-	  R8A7795 and R8A7796 SoCs.
-
 config USB_EHCI_ZYNQ
 	bool "Support for Xilinx Zynq on-chip EHCI USB controller"
 	depends on ARCH_ZYNQ
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index ab5a99faa8..d3ff591a71 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
-obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
diff --git a/drivers/usb/host/ehci-rcar_gen3.c b/drivers/usb/host/ehci-rcar_gen3.c
deleted file mode 100644
index 525e7f3573..0000000000
--- a/drivers/usb/host/ehci-rcar_gen3.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * drivers/usb/host/ehci-rcar_gen3.
- *	This file is EHCI HCD (Host Controller Driver) for USB.
- *
- * Copyright (C) 2015-2017 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <wait_bit.h>
-#include <asm/io.h>
-#include <usb/ehci-ci.h>
-#include "ehci.h"
-
-#define RCAR_GEN3_USB_BASE(n)	(0xEE080000 + ((n) * 0x20000))
-
-#define EHCI_USBCMD		0x120
-
-#define CORE_SPD_RSM_TIMSET	0x30c
-#define CORE_OC_TIMSET		0x310
-
-/* Register offset */
-#define AHB_OFFSET		0x200
-
-#define BASE_HSUSB		0xE6590000
-#define REG_LPSTS		(BASE_HSUSB + 0x0102)	/* 16bit */
-#define SUSPM			0x4000
-#define SUSPM_NORMAL		BIT(14)
-#define REG_UGCTRL2		(BASE_HSUSB + 0x0184)	/* 32bit */
-#define USB0SEL			0x00000030
-#define USB0SEL_EHCI		0x00000010
-
-#define SMSTPCR7		0xE615014C
-#define SMSTPCR700		BIT(0)	/* EHCI3 */
-#define SMSTPCR701		BIT(1)	/* EHCI2 */
-#define SMSTPCR702		BIT(2)	/* EHCI1 */
-#define SMSTPCR703		BIT(3)	/* EHCI0 */
-#define SMSTPCR704		BIT(4)	/* HSUSB */
-
-#define AHB_PLL_RST		BIT(1)
-
-#define USBH_INTBEN		BIT(2)
-#define USBH_INTAEN		BIT(1)
-
-#define AHB_INT_ENABLE		0x200
-#define AHB_USBCTR		0x20c
-
-int ehci_hcd_stop(int index)
-{
-#if defined(CONFIG_R8A7795)
-	const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
-#else
-	const u32 mask = SMSTPCR703 | SMSTPCR702;
-#endif
-	const u32 base = RCAR_GEN3_USB_BASE(index);
-	int ret;
-
-	/* Reset EHCI */
-	setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
-	ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
-			   CMD_RESET, false, 10, true);
-	if (ret) {
-		printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
-		       index, ret);
-	}
-
-	setbits_le32(SMSTPCR7, BIT(3 - index));
-
-	if ((readl(SMSTPCR7) & mask) == mask)
-		setbits_le32(SMSTPCR7, SMSTPCR704);
-
-	return 0;
-}
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	const void __iomem *base =
-		(void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
-	struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
-
-	clrbits_le32(SMSTPCR7, BIT(3 - index));
-	clrbits_le32(SMSTPCR7, SMSTPCR704);
-
-	*hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
-	*hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	/* Enable interrupt */
-	setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
-	writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
-	writel(0x000209ab, base + CORE_OC_TIMSET);
-
-	/* Choice USB0SEL */
-	clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
-
-	/* Clock & Reset */
-	clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
-
-	/* low power status */
-	clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
-
-	return 0;
-}
-- 
2.11.0

[U-Boot] [PATCH 6/6] usb: Drop the EHCI RCar Gen3

[Nobuhiro Iwamatsu]

Hi,

2017-09-13 2:07 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:
> Since we use EHCI generic driver on RCar Gen3 , this driver is useless.
> Remove it.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Best regards,
  Nobuhiro

> ---
>  drivers/usb/host/Kconfig          |   8 ---
>  drivers/usb/host/Makefile         |   1 -
>  drivers/usb/host/ehci-rcar_gen3.c | 106 --------------------------------------
>  3 files changed, 115 deletions(-)
>  delete mode 100644 drivers/usb/host/ehci-rcar_gen3.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index eb035a476b..5438feb8f5 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -148,14 +148,6 @@ config USB_EHCI_PCI
>         help
>           Enables support for the PCI-based EHCI controller.
>
> -config USB_EHCI_RCAR_GEN3
> -       bool "Support for Renesas RCar M3/H3 EHCI USB controller"
> -       depends on RCAR_GEN3
> -       default y
> -       ---help---
> -         Enables support for the on-chip EHCI controller on Renesas
> -         R8A7795 and R8A7796 SoCs.
> -
>  config USB_EHCI_ZYNQ
>         bool "Support for Xilinx Zynq on-chip EHCI USB controller"
>         depends on ARCH_ZYNQ
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index ab5a99faa8..d3ff591a71 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -46,7 +46,6 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
>  obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
>  obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
>  obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
> -obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
>  obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
>
>  # xhci
> diff --git a/drivers/usb/host/ehci-rcar_gen3.c b/drivers/usb/host/ehci-rcar_gen3.c
> deleted file mode 100644
> index 525e7f3573..0000000000
> --- a/drivers/usb/host/ehci-rcar_gen3.c
> +++ /dev/null
> @@ -1,106 +0,0 @@
> -/*
> - * drivers/usb/host/ehci-rcar_gen3.
> - *     This file is EHCI HCD (Host Controller Driver) for USB.
> - *
> - * Copyright (C) 2015-2017 Renesas Electronics Corporation
> - *
> - * SPDX-License-Identifier:     GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <errno.h>
> -#include <wait_bit.h>
> -#include <asm/io.h>
> -#include <usb/ehci-ci.h>
> -#include "ehci.h"
> -
> -#define RCAR_GEN3_USB_BASE(n)  (0xEE080000 + ((n) * 0x20000))
> -
> -#define EHCI_USBCMD            0x120
> -
> -#define CORE_SPD_RSM_TIMSET    0x30c
> -#define CORE_OC_TIMSET         0x310
> -
> -/* Register offset */
> -#define AHB_OFFSET             0x200
> -
> -#define BASE_HSUSB             0xE6590000
> -#define REG_LPSTS              (BASE_HSUSB + 0x0102)   /* 16bit */
> -#define SUSPM                  0x4000
> -#define SUSPM_NORMAL           BIT(14)
> -#define REG_UGCTRL2            (BASE_HSUSB + 0x0184)   /* 32bit */
> -#define USB0SEL                        0x00000030
> -#define USB0SEL_EHCI           0x00000010
> -
> -#define SMSTPCR7               0xE615014C
> -#define SMSTPCR700             BIT(0)  /* EHCI3 */
> -#define SMSTPCR701             BIT(1)  /* EHCI2 */
> -#define SMSTPCR702             BIT(2)  /* EHCI1 */
> -#define SMSTPCR703             BIT(3)  /* EHCI0 */
> -#define SMSTPCR704             BIT(4)  /* HSUSB */
> -
> -#define AHB_PLL_RST            BIT(1)
> -
> -#define USBH_INTBEN            BIT(2)
> -#define USBH_INTAEN            BIT(1)
> -
> -#define AHB_INT_ENABLE         0x200
> -#define AHB_USBCTR             0x20c
> -
> -int ehci_hcd_stop(int index)
> -{
> -#if defined(CONFIG_R8A7795)
> -       const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
> -#else
> -       const u32 mask = SMSTPCR703 | SMSTPCR702;
> -#endif
> -       const u32 base = RCAR_GEN3_USB_BASE(index);
> -       int ret;
> -
> -       /* Reset EHCI */
> -       setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
> -       ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
> -                          CMD_RESET, false, 10, true);
> -       if (ret) {
> -               printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
> -                      index, ret);
> -       }
> -
> -       setbits_le32(SMSTPCR7, BIT(3 - index));
> -
> -       if ((readl(SMSTPCR7) & mask) == mask)
> -               setbits_le32(SMSTPCR7, SMSTPCR704);
> -
> -       return 0;
> -}
> -
> -int ehci_hcd_init(int index, enum usb_init_type init,
> -                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
> -{
> -       const void __iomem *base =
> -               (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
> -       struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
> -
> -       clrbits_le32(SMSTPCR7, BIT(3 - index));
> -       clrbits_le32(SMSTPCR7, SMSTPCR704);
> -
> -       *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
> -       *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
> -                       HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
> -
> -       /* Enable interrupt */
> -       setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
> -       writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
> -       writel(0x000209ab, base + CORE_OC_TIMSET);
> -
> -       /* Choice USB0SEL */
> -       clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
> -
> -       /* Clock & Reset */
> -       clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
> -
> -       /* low power status */
> -       clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
> -
> -       return 0;
> -}
> --
> 2.11.0
>



-- 
Nobuhiro Iwamatsu
   iwamatsu at {nigauri.org / debian.org}
   GPG ID: 40AD1FA6