[PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This series aims to clean up some of the plane state readout and
sanitation, and clean up the enum plane mess a bit by renaming it
to enum old_plane_id.

The one actual bugfix here is the plane<->crtc sanitation
change. Previously we tried to shut down the entire pipe when
the plane mapping wasn't what we want, now we just shut down the
plane, which is easier.

Most of the other stuff is just polish, but I also decided to
throw the gen2/3 and chv primary plane windowing support on on top
just because it's been bugging me for years, and I was already
in the neighbourhood.

Series available here:
git://github.com/vsyrjala/linux.git plane_sanitation_2

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>

Ville Syrjälä (9):
  drm/i915: Add .get_hw_state() method for planes
  drm/i915: Redo plane sanitation during readout
  drm/i915: s/enum plane/enum old_plane_id/
  drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
  drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
    fb readout
  drm/i915: Nuke ironlake_get_initial_plane_config()
  drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
  drm/i915: Nuke crtc->plane
  drm/i915: Add windowing for primary planes on gen2/3 and chv

 drivers/gpu/drm/i915/i915_drv.h      |  16 +-
 drivers/gpu/drm/i915/intel_display.c | 500 +++++++++++++++--------------------
 drivers/gpu/drm/i915/intel_drv.h     |   8 +-
 drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
 drivers/gpu/drm/i915/intel_pm.c      |  36 +--
 drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
 6 files changed, 299 insertions(+), 331 deletions(-)

-- 
2.13.6

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[PATCH 1/9] drm/i915: Add .get_hw_state() method for planes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a .get_hw_state() method for planes, returning true or false
depending on whether the plane is enabled. Use it to rewrite the
plane enabled/disabled asserts in platform agnostic fashion.

We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
supposed sanitize that anyway it doesn't really matter.

v2: Reoder patches to not depend on enum old_plane_id
    Just call assert_plane_disabled() from assert_planes_disabled()

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 155 +++++++++++++----------------------
 drivers/gpu/drm/i915/intel_drv.h     |   1 +
 drivers/gpu/drm/i915/intel_sprite.c  |  43 ++++++++++
 3 files changed, 101 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b2c5fba102e1..825ab00b6639 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1192,23 +1192,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 	     pipe_name(pipe));
 }
 
-static void assert_cursor(struct drm_i915_private *dev_priv,
-			  enum pipe pipe, bool state)
-{
-	bool cur_state;
-
-	if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
-		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
-	else
-		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
-
-	I915_STATE_WARN(cur_state != state,
-	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
-			pipe_name(pipe), onoff(state), onoff(cur_state));
-}
-#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
-#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
-
 void assert_pipe(struct drm_i915_private *dev_priv,
 		 enum pipe pipe, bool state)
 {
@@ -1236,77 +1219,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 			pipe_name(pipe), onoff(state), onoff(cur_state));
 }
 
-static void assert_plane(struct drm_i915_private *dev_priv,
-			 enum plane plane, bool state)
+static void assert_plane(struct intel_plane *plane, bool state)
 {
-	u32 val;
-	bool cur_state;
+	bool cur_state = plane->get_hw_state(plane);
 
-	val = I915_READ(DSPCNTR(plane));
-	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 	I915_STATE_WARN(cur_state != state,
-	     "plane %c assertion failure (expected %s, current %s)\n",
-			plane_name(plane), onoff(state), onoff(cur_state));
+			"%s assertion failure (expected %s, current %s)\n",
+			plane->base.name, onoff(state), onoff(cur_state));
 }
 
-#define assert_plane_enabled(d, p) assert_plane(d, p, true)
-#define assert_plane_disabled(d, p) assert_plane(d, p, false)
+#define assert_plane_enabled(p) assert_plane(p, true)
+#define assert_plane_disabled(p) assert_plane(p, false)
 
-static void assert_planes_disabled(struct drm_i915_private *dev_priv,
-				   enum pipe pipe)
+static void assert_planes_disabled(struct intel_crtc *crtc)
 {
-	int i;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_plane *plane;
 
-	/* Primary planes are fixed to pipes on gen4+ */
-	if (INTEL_GEN(dev_priv) >= 4) {
-		u32 val = I915_READ(DSPCNTR(pipe));
-		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
-		     "plane %c assertion failure, should be disabled but not\n",
-		     plane_name(pipe));
-		return;
-	}
-
-	/* Need to check both planes against the pipe */
-	for_each_pipe(dev_priv, i) {
-		u32 val = I915_READ(DSPCNTR(i));
-		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
-			DISPPLANE_SEL_PIPE_SHIFT;
-		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
-		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
-		     plane_name(i), pipe_name(pipe));
-	}
-}
-
-static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
-				    enum pipe pipe)
-{
-	int sprite;
-
-	if (INTEL_GEN(dev_priv) >= 9) {
-		for_each_sprite(dev_priv, pipe, sprite) {
-			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
-			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
-			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
-			     sprite, pipe_name(pipe));
-		}
-	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		for_each_sprite(dev_priv, pipe, sprite) {
-			u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
-			I915_STATE_WARN(val & SP_ENABLE,
-			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
-			     sprite_name(pipe, sprite), pipe_name(pipe));
-		}
-	} else if (INTEL_GEN(dev_priv) >= 7) {
-		u32 val = I915_READ(SPRCTL(pipe));
-		I915_STATE_WARN(val & SPRITE_ENABLE,
-		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
-		     plane_name(pipe), pipe_name(pipe));
-	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
-		u32 val = I915_READ(DVSCNTR(pipe));
-		I915_STATE_WARN(val & DVS_ENABLE,
-		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
-		     plane_name(pipe), pipe_name(pipe));
-	}
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
+		assert_plane_disabled(plane);
 }
 
 static void assert_vblank_disabled(struct drm_crtc *crtc)
@@ -1899,9 +1830,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 
 	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
 
-	assert_planes_disabled(dev_priv, pipe);
-	assert_cursor_disabled(dev_priv, pipe);
-	assert_sprites_disabled(dev_priv, pipe);
+	assert_planes_disabled(crtc);
 
 	/*
 	 * A pipe without a PLL won't actually be able to drive bits from
@@ -1971,9 +1900,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
 	 * Make sure planes won't keep trying to pump pixels to us,
 	 * or we might hang the display.
 	 */
-	assert_planes_disabled(dev_priv, pipe);
-	assert_cursor_disabled(dev_priv, pipe);
-	assert_sprites_disabled(dev_priv, pipe);
+	assert_planes_disabled(crtc);
 
 	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
@@ -3370,6 +3297,14 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary,
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
+static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
+{
+	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
+	enum plane plane = primary->plane;
+
+	return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
+}
+
 static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
 {
@@ -3638,6 +3573,15 @@ static void skylake_disable_primary_plane(struct intel_plane *primary,
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
+static bool skylake_primary_get_hw_state(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum pipe pipe = plane->pipe;
+	enum plane_id plane_id = plane->id;
+
+	return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
+}
+
 static int
 __intel_display_resume(struct drm_device *dev,
 		       struct drm_atomic_state *state,
@@ -4944,7 +4888,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
 	 * a vblank wait.
 	 */
 
-	assert_plane_enabled(dev_priv, crtc->plane);
+	assert_plane_enabled(to_intel_plane(crtc->base.primary));
+
 	if (IS_BROADWELL(dev_priv)) {
 		mutex_lock(&dev_priv->pcu_lock);
 		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
@@ -4977,7 +4922,8 @@ void hsw_disable_ips(struct intel_crtc *crtc)
 	if (!crtc->config->ips_enabled)
 		return;
 
-	assert_plane_enabled(dev_priv, crtc->plane);
+	assert_plane_enabled(to_intel_plane(crtc->base.primary));
+
 	if (IS_BROADWELL(dev_priv)) {
 		mutex_lock(&dev_priv->pcu_lock);
 		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
@@ -9557,6 +9503,13 @@ static void i845_disable_cursor(struct intel_plane *plane,
 	i845_update_cursor(plane, NULL, NULL);
 }
 
+static bool i845_cursor_get_hw_state(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+	return I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
+}
+
 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 			   const struct intel_plane_state *plane_state)
 {
@@ -9750,6 +9703,13 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
 	i9xx_update_cursor(plane, NULL, NULL);
 }
 
+static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum pipe pipe = plane->pipe;
+
+	return I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
+}
 
 /* VESA 640x480x72Hz mode to set on the pipe */
 static const struct drm_display_mode load_detect_mode = {
@@ -13235,6 +13195,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 		primary->update_plane = skylake_update_primary_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
+		primary->get_hw_state = skylake_primary_get_hw_state;
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_primary_formats = skl_primary_formats;
 		num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -13245,6 +13206,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 		primary->update_plane = skylake_update_primary_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
+		primary->get_hw_state = skylake_primary_get_hw_state;
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
@@ -13252,6 +13214,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 		primary->update_plane = i9xx_update_primary_plane;
 		primary->disable_plane = i9xx_disable_primary_plane;
+		primary->get_hw_state = i9xx_plane_get_hw_state;
 	} else {
 		intel_primary_formats = i8xx_primary_formats;
 		num_formats = ARRAY_SIZE(i8xx_primary_formats);
@@ -13259,6 +13222,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 		primary->update_plane = i9xx_update_primary_plane;
 		primary->disable_plane = i9xx_disable_primary_plane;
+		primary->get_hw_state = i9xx_plane_get_hw_state;
 	}
 
 	if (INTEL_GEN(dev_priv) >= 9)
@@ -13348,10 +13312,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
 	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
 		cursor->update_plane = i845_update_cursor;
 		cursor->disable_plane = i845_disable_cursor;
+		cursor->get_hw_state = i845_cursor_get_hw_state;
 		cursor->check_plane = i845_check_cursor;
 	} else {
 		cursor->update_plane = i9xx_update_cursor;
 		cursor->disable_plane = i9xx_disable_cursor;
+		cursor->get_hw_state = i9xx_cursor_get_hw_state;
 		cursor->check_plane = i9xx_check_cursor;
 	}
 
@@ -14699,8 +14665,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
 		      pipe_name(pipe));
 
-	assert_plane_disabled(dev_priv, PLANE_A);
-	assert_plane_disabled(dev_priv, PLANE_B);
+	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A));
+	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B));
 
 	I915_WRITE(PIPECONF(pipe), 0);
 	POSTING_READ(PIPECONF(pipe));
@@ -14914,20 +14880,13 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
 	intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
 }
 
-static bool primary_get_hw_state(struct intel_plane *plane)
-{
-	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-
-	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
-}
-
 /* FIXME read out full plane state for all planes */
 static void readout_plane_state(struct intel_crtc *crtc)
 {
 	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
 	bool visible;
 
-	visible = crtc->active && primary_get_hw_state(primary);
+	visible = crtc->active && primary->get_hw_state(primary);
 
 	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
 				to_intel_plane_state(primary->base.state),
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cdda0a84babe..24bbf0518473 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -868,6 +868,7 @@ struct intel_plane {
 			     const struct intel_plane_state *plane_state);
 	void (*disable_plane)(struct intel_plane *plane,
 			      struct intel_crtc *crtc);
+	bool (*get_hw_state)(struct intel_plane *plane);
 	int (*check_plane)(struct intel_plane *plane,
 			   struct intel_crtc_state *crtc_state,
 			   struct intel_plane_state *state);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f29369622d2c..a533df6fe706 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -329,6 +329,16 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
+static bool
+skl_plane_get_hw_state(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+
+	return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
+}
+
 static void
 chv_update_csc(struct intel_plane *plane, uint32_t format)
 {
@@ -506,6 +516,16 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
+static bool
+vlv_plane_get_hw_state(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+
+	return I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
+}
+
 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
@@ -646,6 +666,15 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
+static bool
+ivb_plane_get_hw_state(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum pipe pipe = plane->pipe;
+
+	return I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
+}
+
 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
@@ -777,6 +806,15 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
+static bool
+g4x_plane_get_hw_state(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum pipe pipe = plane->pipe;
+
+	return I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
+}
+
 static int
 intel_check_sprite_plane(struct intel_plane *plane,
 			 struct intel_crtc_state *crtc_state,
@@ -1232,6 +1270,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 		intel_plane->update_plane = skl_update_plane;
 		intel_plane->disable_plane = skl_disable_plane;
+		intel_plane->get_hw_state = skl_plane_get_hw_state;
 
 		plane_formats = skl_plane_formats;
 		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
@@ -1242,6 +1281,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 		intel_plane->update_plane = skl_update_plane;
 		intel_plane->disable_plane = skl_disable_plane;
+		intel_plane->get_hw_state = skl_plane_get_hw_state;
 
 		plane_formats = skl_plane_formats;
 		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
@@ -1252,6 +1292,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 		intel_plane->update_plane = vlv_update_plane;
 		intel_plane->disable_plane = vlv_disable_plane;
+		intel_plane->get_hw_state = vlv_plane_get_hw_state;
 
 		plane_formats = vlv_plane_formats;
 		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
@@ -1267,6 +1308,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 		intel_plane->update_plane = ivb_update_plane;
 		intel_plane->disable_plane = ivb_disable_plane;
+		intel_plane->get_hw_state = ivb_plane_get_hw_state;
 
 		plane_formats = snb_plane_formats;
 		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
@@ -1277,6 +1319,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 		intel_plane->update_plane = g4x_update_plane;
 		intel_plane->disable_plane = g4x_disable_plane;
+		intel_plane->get_hw_state = g4x_plane_get_hw_state;
 
 		modifiers = i9xx_plane_format_modifiers;
 		if (IS_GEN6(dev_priv)) {
-- 
2.13.6

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Re: [PATCH 1/9] drm/i915: Add .get_hw_state() method for planes

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:47PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a .get_hw_state() method for planes, returning true or false
> depending on whether the plane is enabled. Use it to rewrite the
> plane enabled/disabled asserts in platform agnostic fashion.
> 
> We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
> supposed sanitize that anyway it doesn't really matter.
> 
> v2: Reoder patches to not depend on enum old_plane_id
>     Just call assert_plane_disabled() from assert_planes_disabled()
> 
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Would have been really nice to pimp our hw state checker (at least for
synchronous modesets) to verify these. That way I could just blindly trust
CI.

Anyway, seems correct, but if you can supply such a patch as a follow-up
would be even better:

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 155 +++++++++++++----------------------
>  drivers/gpu/drm/i915/intel_drv.h     |   1 +
>  drivers/gpu/drm/i915/intel_sprite.c  |  43 ++++++++++
>  3 files changed, 101 insertions(+), 98 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b2c5fba102e1..825ab00b6639 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1192,23 +1192,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	     pipe_name(pipe));
>  }
>  
> -static void assert_cursor(struct drm_i915_private *dev_priv,
> -			  enum pipe pipe, bool state)
> -{
> -	bool cur_state;
> -
> -	if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
> -		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> -	else
> -		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> -
> -	I915_STATE_WARN(cur_state != state,
> -	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
> -			pipe_name(pipe), onoff(state), onoff(cur_state));
> -}
> -#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
> -#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
> -
>  void assert_pipe(struct drm_i915_private *dev_priv,
>  		 enum pipe pipe, bool state)
>  {
> @@ -1236,77 +1219,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
>  			pipe_name(pipe), onoff(state), onoff(cur_state));
>  }
>  
> -static void assert_plane(struct drm_i915_private *dev_priv,
> -			 enum plane plane, bool state)
> +static void assert_plane(struct intel_plane *plane, bool state)
>  {
> -	u32 val;
> -	bool cur_state;
> +	bool cur_state = plane->get_hw_state(plane);
>  
> -	val = I915_READ(DSPCNTR(plane));
> -	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
> -	     "plane %c assertion failure (expected %s, current %s)\n",
> -			plane_name(plane), onoff(state), onoff(cur_state));
> +			"%s assertion failure (expected %s, current %s)\n",
> +			plane->base.name, onoff(state), onoff(cur_state));
>  }
>  
> -#define assert_plane_enabled(d, p) assert_plane(d, p, true)
> -#define assert_plane_disabled(d, p) assert_plane(d, p, false)
> +#define assert_plane_enabled(p) assert_plane(p, true)
> +#define assert_plane_disabled(p) assert_plane(p, false)
>  
> -static void assert_planes_disabled(struct drm_i915_private *dev_priv,
> -				   enum pipe pipe)
> +static void assert_planes_disabled(struct intel_crtc *crtc)
>  {
> -	int i;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_plane *plane;
>  
> -	/* Primary planes are fixed to pipes on gen4+ */
> -	if (INTEL_GEN(dev_priv) >= 4) {
> -		u32 val = I915_READ(DSPCNTR(pipe));
> -		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
> -		     "plane %c assertion failure, should be disabled but not\n",
> -		     plane_name(pipe));
> -		return;
> -	}
> -
> -	/* Need to check both planes against the pipe */
> -	for_each_pipe(dev_priv, i) {
> -		u32 val = I915_READ(DSPCNTR(i));
> -		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> -			DISPPLANE_SEL_PIPE_SHIFT;
> -		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
> -		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
> -		     plane_name(i), pipe_name(pipe));
> -	}
> -}
> -
> -static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> -				    enum pipe pipe)
> -{
> -	int sprite;
> -
> -	if (INTEL_GEN(dev_priv) >= 9) {
> -		for_each_sprite(dev_priv, pipe, sprite) {
> -			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
> -			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
> -			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
> -			     sprite, pipe_name(pipe));
> -		}
> -	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> -		for_each_sprite(dev_priv, pipe, sprite) {
> -			u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
> -			I915_STATE_WARN(val & SP_ENABLE,
> -			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> -			     sprite_name(pipe, sprite), pipe_name(pipe));
> -		}
> -	} else if (INTEL_GEN(dev_priv) >= 7) {
> -		u32 val = I915_READ(SPRCTL(pipe));
> -		I915_STATE_WARN(val & SPRITE_ENABLE,
> -		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> -		     plane_name(pipe), pipe_name(pipe));
> -	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> -		u32 val = I915_READ(DVSCNTR(pipe));
> -		I915_STATE_WARN(val & DVS_ENABLE,
> -		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> -		     plane_name(pipe), pipe_name(pipe));
> -	}
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
> +		assert_plane_disabled(plane);
>  }
>  
>  static void assert_vblank_disabled(struct drm_crtc *crtc)
> @@ -1899,9 +1830,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
>  
>  	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
>  
> -	assert_planes_disabled(dev_priv, pipe);
> -	assert_cursor_disabled(dev_priv, pipe);
> -	assert_sprites_disabled(dev_priv, pipe);
> +	assert_planes_disabled(crtc);
>  
>  	/*
>  	 * A pipe without a PLL won't actually be able to drive bits from
> @@ -1971,9 +1900,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
>  	 * Make sure planes won't keep trying to pump pixels to us,
>  	 * or we might hang the display.
>  	 */
> -	assert_planes_disabled(dev_priv, pipe);
> -	assert_cursor_disabled(dev_priv, pipe);
> -	assert_sprites_disabled(dev_priv, pipe);
> +	assert_planes_disabled(crtc);
>  
>  	reg = PIPECONF(cpu_transcoder);
>  	val = I915_READ(reg);
> @@ -3370,6 +3297,14 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary,
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> +static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> +	enum plane plane = primary->plane;
> +
> +	return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
> +}
> +
>  static u32
>  intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
>  {
> @@ -3638,6 +3573,15 @@ static void skylake_disable_primary_plane(struct intel_plane *primary,
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> +static bool skylake_primary_get_hw_state(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum pipe pipe = plane->pipe;
> +	enum plane_id plane_id = plane->id;
> +
> +	return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
> +}
> +
>  static int
>  __intel_display_resume(struct drm_device *dev,
>  		       struct drm_atomic_state *state,
> @@ -4944,7 +4888,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
>  	 * a vblank wait.
>  	 */
>  
> -	assert_plane_enabled(dev_priv, crtc->plane);
> +	assert_plane_enabled(to_intel_plane(crtc->base.primary));
> +
>  	if (IS_BROADWELL(dev_priv)) {
>  		mutex_lock(&dev_priv->pcu_lock);
>  		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> @@ -4977,7 +4922,8 @@ void hsw_disable_ips(struct intel_crtc *crtc)
>  	if (!crtc->config->ips_enabled)
>  		return;
>  
> -	assert_plane_enabled(dev_priv, crtc->plane);
> +	assert_plane_enabled(to_intel_plane(crtc->base.primary));
> +
>  	if (IS_BROADWELL(dev_priv)) {
>  		mutex_lock(&dev_priv->pcu_lock);
>  		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> @@ -9557,6 +9503,13 @@ static void i845_disable_cursor(struct intel_plane *plane,
>  	i845_update_cursor(plane, NULL, NULL);
>  }
>  
> +static bool i845_cursor_get_hw_state(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> +	return I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> +}
> +
>  static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
>  			   const struct intel_plane_state *plane_state)
>  {
> @@ -9750,6 +9703,13 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
>  	i9xx_update_cursor(plane, NULL, NULL);
>  }
>  
> +static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum pipe pipe = plane->pipe;
> +
> +	return I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> +}
>  
>  /* VESA 640x480x72Hz mode to set on the pipe */
>  static const struct drm_display_mode load_detect_mode = {
> @@ -13235,6 +13195,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  		primary->update_plane = skylake_update_primary_plane;
>  		primary->disable_plane = skylake_disable_primary_plane;
> +		primary->get_hw_state = skylake_primary_get_hw_state;
>  	} else if (INTEL_GEN(dev_priv) >= 9) {
>  		intel_primary_formats = skl_primary_formats;
>  		num_formats = ARRAY_SIZE(skl_primary_formats);
> @@ -13245,6 +13206,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  		primary->update_plane = skylake_update_primary_plane;
>  		primary->disable_plane = skylake_disable_primary_plane;
> +		primary->get_hw_state = skylake_primary_get_hw_state;
>  	} else if (INTEL_GEN(dev_priv) >= 4) {
>  		intel_primary_formats = i965_primary_formats;
>  		num_formats = ARRAY_SIZE(i965_primary_formats);
> @@ -13252,6 +13214,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  		primary->update_plane = i9xx_update_primary_plane;
>  		primary->disable_plane = i9xx_disable_primary_plane;
> +		primary->get_hw_state = i9xx_plane_get_hw_state;
>  	} else {
>  		intel_primary_formats = i8xx_primary_formats;
>  		num_formats = ARRAY_SIZE(i8xx_primary_formats);
> @@ -13259,6 +13222,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  		primary->update_plane = i9xx_update_primary_plane;
>  		primary->disable_plane = i9xx_disable_primary_plane;
> +		primary->get_hw_state = i9xx_plane_get_hw_state;
>  	}
>  
>  	if (INTEL_GEN(dev_priv) >= 9)
> @@ -13348,10 +13312,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>  	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
>  		cursor->update_plane = i845_update_cursor;
>  		cursor->disable_plane = i845_disable_cursor;
> +		cursor->get_hw_state = i845_cursor_get_hw_state;
>  		cursor->check_plane = i845_check_cursor;
>  	} else {
>  		cursor->update_plane = i9xx_update_cursor;
>  		cursor->disable_plane = i9xx_disable_cursor;
> +		cursor->get_hw_state = i9xx_cursor_get_hw_state;
>  		cursor->check_plane = i9xx_check_cursor;
>  	}
>  
> @@ -14699,8 +14665,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
>  		      pipe_name(pipe));
>  
> -	assert_plane_disabled(dev_priv, PLANE_A);
> -	assert_plane_disabled(dev_priv, PLANE_B);
> +	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A));
> +	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B));
>  
>  	I915_WRITE(PIPECONF(pipe), 0);
>  	POSTING_READ(PIPECONF(pipe));
> @@ -14914,20 +14880,13 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
>  }
>  
> -static bool primary_get_hw_state(struct intel_plane *plane)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> -
> -	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
> -}
> -
>  /* FIXME read out full plane state for all planes */
>  static void readout_plane_state(struct intel_crtc *crtc)
>  {
>  	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
>  	bool visible;
>  
> -	visible = crtc->active && primary_get_hw_state(primary);
> +	visible = crtc->active && primary->get_hw_state(primary);
>  
>  	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
>  				to_intel_plane_state(primary->base.state),
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cdda0a84babe..24bbf0518473 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -868,6 +868,7 @@ struct intel_plane {
>  			     const struct intel_plane_state *plane_state);
>  	void (*disable_plane)(struct intel_plane *plane,
>  			      struct intel_crtc *crtc);
> +	bool (*get_hw_state)(struct intel_plane *plane);
>  	int (*check_plane)(struct intel_plane *plane,
>  			   struct intel_crtc_state *crtc_state,
>  			   struct intel_plane_state *state);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f29369622d2c..a533df6fe706 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -329,6 +329,16 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> +static bool
> +skl_plane_get_hw_state(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +
> +	return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
> +}
> +
>  static void
>  chv_update_csc(struct intel_plane *plane, uint32_t format)
>  {
> @@ -506,6 +516,16 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> +static bool
> +vlv_plane_get_hw_state(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +
> +	return I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
> +}
> +
>  static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  			  const struct intel_plane_state *plane_state)
>  {
> @@ -646,6 +666,15 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> +static bool
> +ivb_plane_get_hw_state(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum pipe pipe = plane->pipe;
> +
> +	return I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
> +}
> +
>  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
>  			  const struct intel_plane_state *plane_state)
>  {
> @@ -777,6 +806,15 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> +static bool
> +g4x_plane_get_hw_state(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum pipe pipe = plane->pipe;
> +
> +	return I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
> +}
> +
>  static int
>  intel_check_sprite_plane(struct intel_plane *plane,
>  			 struct intel_crtc_state *crtc_state,
> @@ -1232,6 +1270,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  
>  		intel_plane->update_plane = skl_update_plane;
>  		intel_plane->disable_plane = skl_disable_plane;
> +		intel_plane->get_hw_state = skl_plane_get_hw_state;
>  
>  		plane_formats = skl_plane_formats;
>  		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> @@ -1242,6 +1281,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  
>  		intel_plane->update_plane = skl_update_plane;
>  		intel_plane->disable_plane = skl_disable_plane;
> +		intel_plane->get_hw_state = skl_plane_get_hw_state;
>  
>  		plane_formats = skl_plane_formats;
>  		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> @@ -1252,6 +1292,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  
>  		intel_plane->update_plane = vlv_update_plane;
>  		intel_plane->disable_plane = vlv_disable_plane;
> +		intel_plane->get_hw_state = vlv_plane_get_hw_state;
>  
>  		plane_formats = vlv_plane_formats;
>  		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> @@ -1267,6 +1308,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  
>  		intel_plane->update_plane = ivb_update_plane;
>  		intel_plane->disable_plane = ivb_disable_plane;
> +		intel_plane->get_hw_state = ivb_plane_get_hw_state;
>  
>  		plane_formats = snb_plane_formats;
>  		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> @@ -1277,6 +1319,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  
>  		intel_plane->update_plane = g4x_update_plane;
>  		intel_plane->disable_plane = g4x_disable_plane;
> +		intel_plane->get_hw_state = g4x_plane_get_hw_state;
>  
>  		modifiers = i9xx_plane_format_modifiers;
>  		if (IS_GEN6(dev_priv)) {
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/9] drm/i915: Add .get_hw_state() method for planes

[Ville Syrjälä]

On Thu, Oct 12, 2017 at 08:59:20PM +0200, Daniel Vetter wrote:
> On Wed, Oct 11, 2017 at 07:04:47PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add a .get_hw_state() method for planes, returning true or false
> > depending on whether the plane is enabled. Use it to rewrite the
> > plane enabled/disabled asserts in platform agnostic fashion.
> > 
> > We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
> > supposed sanitize that anyway it doesn't really matter.
> > 
> > v2: Reoder patches to not depend on enum old_plane_id
> >     Just call assert_plane_disabled() from assert_planes_disabled()
> > 
> > Cc: Thierry Reding <thierry.reding@gmail.com>
> > Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Would have been really nice to pimp our hw state checker (at least for
> synchronous modesets) to verify these. That way I could just blindly trust
> CI.
> 
> Anyway, seems correct, but if you can supply such a patch as a follow-up
> would be even better:

Sure, I can at least take a stab a it.

> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 155 +++++++++++++----------------------
> >  drivers/gpu/drm/i915/intel_drv.h     |   1 +
> >  drivers/gpu/drm/i915/intel_sprite.c  |  43 ++++++++++
> >  3 files changed, 101 insertions(+), 98 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b2c5fba102e1..825ab00b6639 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1192,23 +1192,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  	     pipe_name(pipe));
> >  }
> >  
> > -static void assert_cursor(struct drm_i915_private *dev_priv,
> > -			  enum pipe pipe, bool state)
> > -{
> > -	bool cur_state;
> > -
> > -	if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
> > -		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> > -	else
> > -		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> > -
> > -	I915_STATE_WARN(cur_state != state,
> > -	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",
> > -			pipe_name(pipe), onoff(state), onoff(cur_state));
> > -}
> > -#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
> > -#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
> > -
> >  void assert_pipe(struct drm_i915_private *dev_priv,
> >  		 enum pipe pipe, bool state)
> >  {
> > @@ -1236,77 +1219,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
> >  			pipe_name(pipe), onoff(state), onoff(cur_state));
> >  }
> >  
> > -static void assert_plane(struct drm_i915_private *dev_priv,
> > -			 enum plane plane, bool state)
> > +static void assert_plane(struct intel_plane *plane, bool state)
> >  {
> > -	u32 val;
> > -	bool cur_state;
> > +	bool cur_state = plane->get_hw_state(plane);
> >  
> > -	val = I915_READ(DSPCNTR(plane));
> > -	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
> >  	I915_STATE_WARN(cur_state != state,
> > -	     "plane %c assertion failure (expected %s, current %s)\n",
> > -			plane_name(plane), onoff(state), onoff(cur_state));
> > +			"%s assertion failure (expected %s, current %s)\n",
> > +			plane->base.name, onoff(state), onoff(cur_state));
> >  }
> >  
> > -#define assert_plane_enabled(d, p) assert_plane(d, p, true)
> > -#define assert_plane_disabled(d, p) assert_plane(d, p, false)
> > +#define assert_plane_enabled(p) assert_plane(p, true)
> > +#define assert_plane_disabled(p) assert_plane(p, false)
> >  
> > -static void assert_planes_disabled(struct drm_i915_private *dev_priv,
> > -				   enum pipe pipe)
> > +static void assert_planes_disabled(struct intel_crtc *crtc)
> >  {
> > -	int i;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	struct intel_plane *plane;
> >  
> > -	/* Primary planes are fixed to pipes on gen4+ */
> > -	if (INTEL_GEN(dev_priv) >= 4) {
> > -		u32 val = I915_READ(DSPCNTR(pipe));
> > -		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
> > -		     "plane %c assertion failure, should be disabled but not\n",
> > -		     plane_name(pipe));
> > -		return;
> > -	}
> > -
> > -	/* Need to check both planes against the pipe */
> > -	for_each_pipe(dev_priv, i) {
> > -		u32 val = I915_READ(DSPCNTR(i));
> > -		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> > -			DISPPLANE_SEL_PIPE_SHIFT;
> > -		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
> > -		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
> > -		     plane_name(i), pipe_name(pipe));
> > -	}
> > -}
> > -
> > -static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> > -				    enum pipe pipe)
> > -{
> > -	int sprite;
> > -
> > -	if (INTEL_GEN(dev_priv) >= 9) {
> > -		for_each_sprite(dev_priv, pipe, sprite) {
> > -			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
> > -			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
> > -			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
> > -			     sprite, pipe_name(pipe));
> > -		}
> > -	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > -		for_each_sprite(dev_priv, pipe, sprite) {
> > -			u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
> > -			I915_STATE_WARN(val & SP_ENABLE,
> > -			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> > -			     sprite_name(pipe, sprite), pipe_name(pipe));
> > -		}
> > -	} else if (INTEL_GEN(dev_priv) >= 7) {
> > -		u32 val = I915_READ(SPRCTL(pipe));
> > -		I915_STATE_WARN(val & SPRITE_ENABLE,
> > -		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> > -		     plane_name(pipe), pipe_name(pipe));
> > -	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> > -		u32 val = I915_READ(DVSCNTR(pipe));
> > -		I915_STATE_WARN(val & DVS_ENABLE,
> > -		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> > -		     plane_name(pipe), pipe_name(pipe));
> > -	}
> > +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
> > +		assert_plane_disabled(plane);
> >  }
> >  
> >  static void assert_vblank_disabled(struct drm_crtc *crtc)
> > @@ -1899,9 +1830,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
> >  
> >  	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
> >  
> > -	assert_planes_disabled(dev_priv, pipe);
> > -	assert_cursor_disabled(dev_priv, pipe);
> > -	assert_sprites_disabled(dev_priv, pipe);
> > +	assert_planes_disabled(crtc);
> >  
> >  	/*
> >  	 * A pipe without a PLL won't actually be able to drive bits from
> > @@ -1971,9 +1900,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
> >  	 * Make sure planes won't keep trying to pump pixels to us,
> >  	 * or we might hang the display.
> >  	 */
> > -	assert_planes_disabled(dev_priv, pipe);
> > -	assert_cursor_disabled(dev_priv, pipe);
> > -	assert_sprites_disabled(dev_priv, pipe);
> > +	assert_planes_disabled(crtc);
> >  
> >  	reg = PIPECONF(cpu_transcoder);
> >  	val = I915_READ(reg);
> > @@ -3370,6 +3297,14 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary,
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > +static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > +	enum plane plane = primary->plane;
> > +
> > +	return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
> > +}
> > +
> >  static u32
> >  intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
> >  {
> > @@ -3638,6 +3573,15 @@ static void skylake_disable_primary_plane(struct intel_plane *primary,
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > +static bool skylake_primary_get_hw_state(struct intel_plane *plane)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum pipe pipe = plane->pipe;
> > +	enum plane_id plane_id = plane->id;
> > +
> > +	return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
> > +}
> > +
> >  static int
> >  __intel_display_resume(struct drm_device *dev,
> >  		       struct drm_atomic_state *state,
> > @@ -4944,7 +4888,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> >  	 * a vblank wait.
> >  	 */
> >  
> > -	assert_plane_enabled(dev_priv, crtc->plane);
> > +	assert_plane_enabled(to_intel_plane(crtc->base.primary));
> > +
> >  	if (IS_BROADWELL(dev_priv)) {
> >  		mutex_lock(&dev_priv->pcu_lock);
> >  		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> > @@ -4977,7 +4922,8 @@ void hsw_disable_ips(struct intel_crtc *crtc)
> >  	if (!crtc->config->ips_enabled)
> >  		return;
> >  
> > -	assert_plane_enabled(dev_priv, crtc->plane);
> > +	assert_plane_enabled(to_intel_plane(crtc->base.primary));
> > +
> >  	if (IS_BROADWELL(dev_priv)) {
> >  		mutex_lock(&dev_priv->pcu_lock);
> >  		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> > @@ -9557,6 +9503,13 @@ static void i845_disable_cursor(struct intel_plane *plane,
> >  	i845_update_cursor(plane, NULL, NULL);
> >  }
> >  
> > +static bool i845_cursor_get_hw_state(struct intel_plane *plane)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +
> > +	return I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> > +}
> > +
> >  static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> >  			   const struct intel_plane_state *plane_state)
> >  {
> > @@ -9750,6 +9703,13 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
> >  	i9xx_update_cursor(plane, NULL, NULL);
> >  }
> >  
> > +static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum pipe pipe = plane->pipe;
> > +
> > +	return I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> > +}
> >  
> >  /* VESA 640x480x72Hz mode to set on the pipe */
> >  static const struct drm_display_mode load_detect_mode = {
> > @@ -13235,6 +13195,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  
> >  		primary->update_plane = skylake_update_primary_plane;
> >  		primary->disable_plane = skylake_disable_primary_plane;
> > +		primary->get_hw_state = skylake_primary_get_hw_state;
> >  	} else if (INTEL_GEN(dev_priv) >= 9) {
> >  		intel_primary_formats = skl_primary_formats;
> >  		num_formats = ARRAY_SIZE(skl_primary_formats);
> > @@ -13245,6 +13206,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  
> >  		primary->update_plane = skylake_update_primary_plane;
> >  		primary->disable_plane = skylake_disable_primary_plane;
> > +		primary->get_hw_state = skylake_primary_get_hw_state;
> >  	} else if (INTEL_GEN(dev_priv) >= 4) {
> >  		intel_primary_formats = i965_primary_formats;
> >  		num_formats = ARRAY_SIZE(i965_primary_formats);
> > @@ -13252,6 +13214,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  
> >  		primary->update_plane = i9xx_update_primary_plane;
> >  		primary->disable_plane = i9xx_disable_primary_plane;
> > +		primary->get_hw_state = i9xx_plane_get_hw_state;
> >  	} else {
> >  		intel_primary_formats = i8xx_primary_formats;
> >  		num_formats = ARRAY_SIZE(i8xx_primary_formats);
> > @@ -13259,6 +13222,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  
> >  		primary->update_plane = i9xx_update_primary_plane;
> >  		primary->disable_plane = i9xx_disable_primary_plane;
> > +		primary->get_hw_state = i9xx_plane_get_hw_state;
> >  	}
> >  
> >  	if (INTEL_GEN(dev_priv) >= 9)
> > @@ -13348,10 +13312,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> >  	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> >  		cursor->update_plane = i845_update_cursor;
> >  		cursor->disable_plane = i845_disable_cursor;
> > +		cursor->get_hw_state = i845_cursor_get_hw_state;
> >  		cursor->check_plane = i845_check_cursor;
> >  	} else {
> >  		cursor->update_plane = i9xx_update_cursor;
> >  		cursor->disable_plane = i9xx_disable_cursor;
> > +		cursor->get_hw_state = i9xx_cursor_get_hw_state;
> >  		cursor->check_plane = i9xx_check_cursor;
> >  	}
> >  
> > @@ -14699,8 +14665,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  	DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
> >  		      pipe_name(pipe));
> >  
> > -	assert_plane_disabled(dev_priv, PLANE_A);
> > -	assert_plane_disabled(dev_priv, PLANE_B);
> > +	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A));
> > +	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B));
> >  
> >  	I915_WRITE(PIPECONF(pipe), 0);
> >  	POSTING_READ(PIPECONF(pipe));
> > @@ -14914,20 +14880,13 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
> >  	intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
> >  }
> >  
> > -static bool primary_get_hw_state(struct intel_plane *plane)
> > -{
> > -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > -
> > -	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
> > -}
> > -
> >  /* FIXME read out full plane state for all planes */
> >  static void readout_plane_state(struct intel_crtc *crtc)
> >  {
> >  	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
> >  	bool visible;
> >  
> > -	visible = crtc->active && primary_get_hw_state(primary);
> > +	visible = crtc->active && primary->get_hw_state(primary);
> >  
> >  	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
> >  				to_intel_plane_state(primary->base.state),
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index cdda0a84babe..24bbf0518473 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -868,6 +868,7 @@ struct intel_plane {
> >  			     const struct intel_plane_state *plane_state);
> >  	void (*disable_plane)(struct intel_plane *plane,
> >  			      struct intel_crtc *crtc);
> > +	bool (*get_hw_state)(struct intel_plane *plane);
> >  	int (*check_plane)(struct intel_plane *plane,
> >  			   struct intel_crtc_state *crtc_state,
> >  			   struct intel_plane_state *state);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index f29369622d2c..a533df6fe706 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -329,6 +329,16 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > +static bool
> > +skl_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum plane_id plane_id = plane->id;
> > +	enum pipe pipe = plane->pipe;
> > +
> > +	return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
> > +}
> > +
> >  static void
> >  chv_update_csc(struct intel_plane *plane, uint32_t format)
> >  {
> > @@ -506,6 +516,16 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > +static bool
> > +vlv_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum plane_id plane_id = plane->id;
> > +	enum pipe pipe = plane->pipe;
> > +
> > +	return I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
> > +}
> > +
> >  static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  			  const struct intel_plane_state *plane_state)
> >  {
> > @@ -646,6 +666,15 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > +static bool
> > +ivb_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum pipe pipe = plane->pipe;
> > +
> > +	return I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
> > +}
> > +
> >  static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> >  			  const struct intel_plane_state *plane_state)
> >  {
> > @@ -777,6 +806,15 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > +static bool
> > +g4x_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum pipe pipe = plane->pipe;
> > +
> > +	return I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
> > +}
> > +
> >  static int
> >  intel_check_sprite_plane(struct intel_plane *plane,
> >  			 struct intel_crtc_state *crtc_state,
> > @@ -1232,6 +1270,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  		intel_plane->update_plane = skl_update_plane;
> >  		intel_plane->disable_plane = skl_disable_plane;
> > +		intel_plane->get_hw_state = skl_plane_get_hw_state;
> >  
> >  		plane_formats = skl_plane_formats;
> >  		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > @@ -1242,6 +1281,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  		intel_plane->update_plane = skl_update_plane;
> >  		intel_plane->disable_plane = skl_disable_plane;
> > +		intel_plane->get_hw_state = skl_plane_get_hw_state;
> >  
> >  		plane_formats = skl_plane_formats;
> >  		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > @@ -1252,6 +1292,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  		intel_plane->update_plane = vlv_update_plane;
> >  		intel_plane->disable_plane = vlv_disable_plane;
> > +		intel_plane->get_hw_state = vlv_plane_get_hw_state;
> >  
> >  		plane_formats = vlv_plane_formats;
> >  		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> > @@ -1267,6 +1308,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  		intel_plane->update_plane = ivb_update_plane;
> >  		intel_plane->disable_plane = ivb_disable_plane;
> > +		intel_plane->get_hw_state = ivb_plane_get_hw_state;
> >  
> >  		plane_formats = snb_plane_formats;
> >  		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> > @@ -1277,6 +1319,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  		intel_plane->update_plane = g4x_update_plane;
> >  		intel_plane->disable_plane = g4x_disable_plane;
> > +		intel_plane->get_hw_state = g4x_plane_get_hw_state;
> >  
> >  		modifiers = i9xx_plane_format_modifiers;
> >  		if (IS_GEN6(dev_priv)) {
> > -- 
> > 2.13.6
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/9] drm/i915: Redo plane sanitation during readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unify the plane disabling during state readout by pulling the code into
a new helper intel_plane_disable_noatomic(). We'll also read out the
state of all planes, so that we know which planes really need to be
diabled.

Additonally we change the plane<->pipe mapping sanitation to work by
simply disabling the offending planes instead of entire pipes. And
we do it before we otherwise sanitize the crtcs, which means we don't
have to worry about misassigned planes during crtc sanitation anymore.

v2: Reoder patches to not depend on enum old_plane_id

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103223
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 116 ++++++++++++++++++++---------------
 1 file changed, 67 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 825ab00b6639..a9fd3b8fa922 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2729,6 +2729,23 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 		      crtc_state->active_planes);
 }
 
+static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
+					 struct intel_plane *plane)
+{
+	struct intel_crtc_state *crtc_state =
+		to_intel_crtc_state(crtc->base.state);
+	struct intel_plane_state *plane_state =
+		to_intel_plane_state(plane->base.state);
+
+	intel_set_plane_visible(crtc_state, plane_state, false);
+
+	if (plane->id == PLANE_PRIMARY)
+		intel_pre_disable_primary_noatomic(&crtc->base);
+
+	trace_intel_disable_plane(&plane->base, crtc);
+	plane->disable_plane(plane, crtc);
+}
+
 static void
 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 			     struct intel_initial_plane_config *plane_config)
@@ -2786,12 +2803,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 	 * simplest solution is to just disable the primary plane now and
 	 * pretend the BIOS never had it enabled.
 	 */
-	intel_set_plane_visible(to_intel_crtc_state(crtc_state),
-				to_intel_plane_state(plane_state),
-				false);
-	intel_pre_disable_primary_noatomic(&intel_crtc->base);
-	trace_intel_disable_plane(primary, intel_crtc);
-	intel_plane->disable_plane(intel_plane, intel_crtc);
+	intel_plane_disable_noatomic(intel_crtc, intel_plane);
 
 	return;
 
@@ -5923,6 +5935,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	enum intel_display_power_domain domain;
+	struct intel_plane *plane;
 	u64 domains;
 	struct drm_atomic_state *state;
 	struct intel_crtc_state *crtc_state;
@@ -5931,11 +5944,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 	if (!intel_crtc->active)
 		return;
 
-	if (crtc->primary->state->visible) {
-		intel_pre_disable_primary_noatomic(crtc);
+	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+		const struct intel_plane_state *plane_state =
+			to_intel_plane_state(plane->base.state);
 
-		intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
-		crtc->primary->state->visible = false;
+		if (plane_state->base.visible)
+			intel_plane_disable_noatomic(intel_crtc, plane);
 	}
 
 	state = drm_atomic_state_alloc(crtc->dev);
@@ -14678,22 +14692,38 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	POSTING_READ(DPLL(pipe));
 }
 
-static bool
-intel_check_plane_mapping(struct intel_crtc *crtc)
+static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
+				   struct intel_plane *primary)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 val;
+	enum plane plane = primary->plane;
+	u32 val = I915_READ(DSPCNTR(plane));
 
-	if (INTEL_INFO(dev_priv)->num_pipes == 1)
-		return true;
+	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
+		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
+}
 
-	val = I915_READ(DSPCNTR(!crtc->plane));
+static void
+intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
+{
+	enum pipe pipe;
 
-	if ((val & DISPLAY_PLANE_ENABLE) &&
-	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
-		return false;
+	if (INTEL_GEN(dev_priv) >= 4)
+		return;
 
-	return true;
+	for_each_pipe(dev_priv, pipe) {
+		struct intel_crtc *crtc =
+			intel_get_crtc_for_pipe(dev_priv, pipe);
+		struct intel_plane *plane =
+			to_intel_plane(crtc->base.primary);
+
+		if (intel_plane_mapping_ok(crtc, plane))
+			continue;
+
+		DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
+			      plane->base.name);
+		intel_plane_disable_noatomic(crtc, plane);
+	}
 }
 
 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
@@ -14749,33 +14779,15 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 
 		/* Disable everything but the primary plane */
 		for_each_intel_plane_on_crtc(dev, crtc, plane) {
-			if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
-				continue;
+			const struct intel_plane_state *plane_state =
+				to_intel_plane_state(plane->base.state);
 
-			trace_intel_disable_plane(&plane->base, crtc);
-			plane->disable_plane(plane, crtc);
+			if (plane_state->base.visible &&
+			    plane->base.type != DRM_PLANE_TYPE_PRIMARY)
+				intel_plane_disable_noatomic(crtc, plane);
 		}
 	}
 
-	/* We need to sanitize the plane -> pipe mapping first because this will
-	 * disable the crtc (and hence change the state) if it is wrong. Note
-	 * that gen4+ has a fixed plane -> pipe mapping.  */
-	if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
-		bool plane;
-
-		DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
-			      crtc->base.base.id, crtc->base.name);
-
-		/* Pipe has the wrong plane attached and the plane is active.
-		 * Temporarily change the plane mapping and disable everything
-		 * ...  */
-		plane = crtc->plane;
-		crtc->base.primary->state->visible = true;
-		crtc->plane = !plane;
-		intel_crtc_disable_noatomic(&crtc->base, ctx);
-		crtc->plane = plane;
-	}
-
 	/* Adjust the state of the output pipe according to whether we
 	 * have active connectors/encoders. */
 	if (crtc->active && !intel_crtc_has_encoders(crtc))
@@ -14883,14 +14895,18 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
 /* FIXME read out full plane state for all planes */
 static void readout_plane_state(struct intel_crtc *crtc)
 {
-	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
-	bool visible;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc_state *crtc_state =
+		to_intel_crtc_state(crtc->base.state);
+	struct intel_plane *plane;
 
-	visible = crtc->active && primary->get_hw_state(primary);
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		struct intel_plane_state *plane_state =
+			to_intel_plane_state(plane->base.state);
+		bool visible = plane->get_hw_state(plane);
 
-	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
-				to_intel_plane_state(primary->base.state),
-				visible);
+		intel_set_plane_visible(crtc_state, plane_state, visible);
+	}
 }
 
 static void intel_modeset_readout_hw_state(struct drm_device *dev)
@@ -15079,6 +15095,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 	/* HW state is read out, now we need to sanitize this mess. */
 	get_encoder_power_domains(dev_priv);
 
+	intel_sanitize_plane_mapping(dev_priv);
+
 	for_each_intel_encoder(dev, encoder) {
 		intel_sanitize_encoder(encoder);
 	}
-- 
2.13.6

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Re: [PATCH 2/9] drm/i915: Redo plane sanitation during readout

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:48PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Unify the plane disabling during state readout by pulling the code into
> a new helper intel_plane_disable_noatomic(). We'll also read out the
> state of all planes, so that we know which planes really need to be
> diabled.
> 
> Additonally we change the plane<->pipe mapping sanitation to work by
> simply disabling the offending planes instead of entire pipes. And
> we do it before we otherwise sanitize the crtcs, which means we don't
> have to worry about misassigned planes during crtc sanitation anymore.
> 
> v2: Reoder patches to not depend on enum old_plane_id
> 
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103223
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 116 ++++++++++++++++++++---------------
>  1 file changed, 67 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 825ab00b6639..a9fd3b8fa922 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2729,6 +2729,23 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
>  		      crtc_state->active_planes);
>  }
>  
> +static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> +					 struct intel_plane *plane)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		to_intel_crtc_state(crtc->base.state);
> +	struct intel_plane_state *plane_state =
> +		to_intel_plane_state(plane->base.state);
> +
> +	intel_set_plane_visible(crtc_state, plane_state, false);
> +
> +	if (plane->id == PLANE_PRIMARY)
> +		intel_pre_disable_primary_noatomic(&crtc->base);
> +
> +	trace_intel_disable_plane(&plane->base, crtc);
> +	plane->disable_plane(plane, crtc);
> +}

Wooot, I asked Maarten ages ago to extract this, thanks for doing this!

Just for that:

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

(ah no I'm kidding, I did check a few things, but thankfully CI now at
least covers some gen3 fun).

Cheers, Daniel


> +
>  static void
>  intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
>  			     struct intel_initial_plane_config *plane_config)
> @@ -2786,12 +2803,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
>  	 * simplest solution is to just disable the primary plane now and
>  	 * pretend the BIOS never had it enabled.
>  	 */
> -	intel_set_plane_visible(to_intel_crtc_state(crtc_state),
> -				to_intel_plane_state(plane_state),
> -				false);
> -	intel_pre_disable_primary_noatomic(&intel_crtc->base);
> -	trace_intel_disable_plane(primary, intel_crtc);
> -	intel_plane->disable_plane(intel_plane, intel_crtc);
> +	intel_plane_disable_noatomic(intel_crtc, intel_plane);
>  
>  	return;
>  
> @@ -5923,6 +5935,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	enum intel_display_power_domain domain;
> +	struct intel_plane *plane;
>  	u64 domains;
>  	struct drm_atomic_state *state;
>  	struct intel_crtc_state *crtc_state;
> @@ -5931,11 +5944,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
>  	if (!intel_crtc->active)
>  		return;
>  
> -	if (crtc->primary->state->visible) {
> -		intel_pre_disable_primary_noatomic(crtc);
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> +		const struct intel_plane_state *plane_state =
> +			to_intel_plane_state(plane->base.state);
>  
> -		intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
> -		crtc->primary->state->visible = false;
> +		if (plane_state->base.visible)
> +			intel_plane_disable_noatomic(intel_crtc, plane);


>  	}
>  
>  	state = drm_atomic_state_alloc(crtc->dev);
> @@ -14678,22 +14692,38 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	POSTING_READ(DPLL(pipe));
>  }
>  
> -static bool
> -intel_check_plane_mapping(struct intel_crtc *crtc)
> +static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
> +				   struct intel_plane *primary)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	u32 val;
> +	enum plane plane = primary->plane;
> +	u32 val = I915_READ(DSPCNTR(plane));
>  
> -	if (INTEL_INFO(dev_priv)->num_pipes == 1)
> -		return true;
> +	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
> +		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
> +}
>  
> -	val = I915_READ(DSPCNTR(!crtc->plane));
> +static void
> +intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
> +{
> +	enum pipe pipe;
>  
> -	if ((val & DISPLAY_PLANE_ENABLE) &&
> -	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
> -		return false;
> +	if (INTEL_GEN(dev_priv) >= 4)
> +		return;
>  
> -	return true;
> +	for_each_pipe(dev_priv, pipe) {
> +		struct intel_crtc *crtc =
> +			intel_get_crtc_for_pipe(dev_priv, pipe);
> +		struct intel_plane *plane =
> +			to_intel_plane(crtc->base.primary);
> +
> +		if (intel_plane_mapping_ok(crtc, plane))
> +			continue;
> +
> +		DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
> +			      plane->base.name);
> +		intel_plane_disable_noatomic(crtc, plane);
> +	}
>  }
>  
>  static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
> @@ -14749,33 +14779,15 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>  
>  		/* Disable everything but the primary plane */
>  		for_each_intel_plane_on_crtc(dev, crtc, plane) {
> -			if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
> -				continue;
> +			const struct intel_plane_state *plane_state =
> +				to_intel_plane_state(plane->base.state);
>  
> -			trace_intel_disable_plane(&plane->base, crtc);
> -			plane->disable_plane(plane, crtc);
> +			if (plane_state->base.visible &&
> +			    plane->base.type != DRM_PLANE_TYPE_PRIMARY)
> +				intel_plane_disable_noatomic(crtc, plane);
>  		}
>  	}
>  
> -	/* We need to sanitize the plane -> pipe mapping first because this will
> -	 * disable the crtc (and hence change the state) if it is wrong. Note
> -	 * that gen4+ has a fixed plane -> pipe mapping.  */
> -	if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
> -		bool plane;
> -
> -		DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
> -			      crtc->base.base.id, crtc->base.name);
> -
> -		/* Pipe has the wrong plane attached and the plane is active.
> -		 * Temporarily change the plane mapping and disable everything
> -		 * ...  */
> -		plane = crtc->plane;
> -		crtc->base.primary->state->visible = true;
> -		crtc->plane = !plane;
> -		intel_crtc_disable_noatomic(&crtc->base, ctx);
> -		crtc->plane = plane;
> -	}
> -
>  	/* Adjust the state of the output pipe according to whether we
>  	 * have active connectors/encoders. */
>  	if (crtc->active && !intel_crtc_has_encoders(crtc))
> @@ -14883,14 +14895,18 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
>  /* FIXME read out full plane state for all planes */
>  static void readout_plane_state(struct intel_crtc *crtc)
>  {
> -	struct intel_plane *primary = to_intel_plane(crtc->base.primary);
> -	bool visible;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		to_intel_crtc_state(crtc->base.state);
> +	struct intel_plane *plane;
>  
> -	visible = crtc->active && primary->get_hw_state(primary);
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +		struct intel_plane_state *plane_state =
> +			to_intel_plane_state(plane->base.state);
> +		bool visible = plane->get_hw_state(plane);
>  
> -	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
> -				to_intel_plane_state(primary->base.state),
> -				visible);
> +		intel_set_plane_visible(crtc_state, plane_state, visible);
> +	}
>  }
>  
>  static void intel_modeset_readout_hw_state(struct drm_device *dev)
> @@ -15079,6 +15095,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>  	/* HW state is read out, now we need to sanitize this mess. */
>  	get_encoder_power_domains(dev_priv);
>  
> +	intel_sanitize_plane_mapping(dev_priv);
> +
>  	for_each_intel_encoder(dev, encoder) {
>  		intel_sanitize_encoder(encoder);
>  	}
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 3/9] drm/i915: s/enum plane/enum old_plane_id/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename enum plane to enum old_plane_id to make it clear that it only
applies to pre-SKL platforms.

v2: Reorder patches

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  4 +-
 drivers/gpu/drm/i915/intel_display.c | 84 ++++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_drv.h     |  6 +--
 3 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6bbc4b83aa0a..7280f9eb2e95 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -307,7 +307,7 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
  * Global legacy plane identifier. Valid only for primary/sprite
  * planes on pre-g4x, and only for primary planes on g4x+.
  */
-enum plane {
+enum old_plane_id {
 	PLANE_A,
 	PLANE_B,
 	PLANE_C,
@@ -1128,7 +1128,7 @@ struct intel_fbc {
 
 		struct {
 			enum pipe pipe;
-			enum plane plane;
+			enum old_plane_id plane;
 			unsigned int fence_y_offset;
 		} crtc;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a9fd3b8fa922..9d37c758f7b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3223,17 +3223,17 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 	return 0;
 }
 
-static void i9xx_update_primary_plane(struct intel_plane *primary,
-				      const struct intel_crtc_state *crtc_state,
-				      const struct intel_plane_state *plane_state)
+static void i9xx_update_plane(struct intel_plane *plane,
+			      const struct intel_crtc_state *crtc_state,
+			      const struct intel_plane_state *plane_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
-	enum plane plane = primary->plane;
+	enum old_plane_id plane_id = plane->plane;
 	u32 linear_offset;
 	u32 dspcntr = plane_state->ctl;
-	i915_reg_t reg = DSPCNTR(plane);
+	i915_reg_t reg = DSPCNTR(plane_id);
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
 	unsigned long irqflags;
@@ -3254,34 +3254,34 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 		/* pipesrc and dspsize control the size that is scaled from,
 		 * which should always be the user's requested size.
 		 */
-		I915_WRITE_FW(DSPSIZE(plane),
+		I915_WRITE_FW(DSPSIZE(plane_id),
 			      ((crtc_state->pipe_src_h - 1) << 16) |
 			      (crtc_state->pipe_src_w - 1));
-		I915_WRITE_FW(DSPPOS(plane), 0);
-	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
-		I915_WRITE_FW(PRIMSIZE(plane),
+		I915_WRITE_FW(DSPPOS(plane_id), 0);
+	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
+		I915_WRITE_FW(PRIMSIZE(plane_id),
 			      ((crtc_state->pipe_src_h - 1) << 16) |
 			      (crtc_state->pipe_src_w - 1));
-		I915_WRITE_FW(PRIMPOS(plane), 0);
-		I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
+		I915_WRITE_FW(PRIMPOS(plane_id), 0);
+		I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
 	}
 
 	I915_WRITE_FW(reg, dspcntr);
 
-	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
+	I915_WRITE_FW(DSPSTRIDE(plane_id), fb->pitches[0]);
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		I915_WRITE_FW(DSPSURF(plane),
+		I915_WRITE_FW(DSPSURF(plane_id),
 			      intel_plane_ggtt_offset(plane_state) +
 			      crtc->dspaddr_offset);
-		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
+		I915_WRITE_FW(DSPOFFSET(plane_id), (y << 16) | x);
 	} else if (INTEL_GEN(dev_priv) >= 4) {
-		I915_WRITE_FW(DSPSURF(plane),
+		I915_WRITE_FW(DSPSURF(plane_id),
 			      intel_plane_ggtt_offset(plane_state) +
 			      crtc->dspaddr_offset);
-		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
-		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
+		I915_WRITE_FW(DSPTILEOFF(plane_id), (y << 16) | x);
+		I915_WRITE_FW(DSPLINOFF(plane_id), linear_offset);
 	} else {
-		I915_WRITE_FW(DSPADDR(plane),
+		I915_WRITE_FW(DSPADDR(plane_id),
 			      intel_plane_ggtt_offset(plane_state) +
 			      crtc->dspaddr_offset);
 	}
@@ -3290,31 +3290,31 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void i9xx_disable_primary_plane(struct intel_plane *primary,
-				       struct intel_crtc *crtc)
+static void i9xx_disable_plane(struct intel_plane *plane,
+			       struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-	enum plane plane = primary->plane;
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum old_plane_id plane_id = plane->plane;
 	unsigned long irqflags;
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	I915_WRITE_FW(DSPCNTR(plane), 0);
-	if (INTEL_INFO(dev_priv)->gen >= 4)
-		I915_WRITE_FW(DSPSURF(plane), 0);
+	I915_WRITE_FW(DSPCNTR(plane_id), 0);
+	if (INTEL_GEN(dev_priv) >= 4)
+		I915_WRITE_FW(DSPSURF(plane_id), 0);
 	else
-		I915_WRITE_FW(DSPADDR(plane), 0);
-	POSTING_READ_FW(DSPCNTR(plane));
+		I915_WRITE_FW(DSPADDR(plane_id), 0);
+	POSTING_READ_FW(DSPCNTR(plane_id));
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
+static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
 {
-	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-	enum plane plane = primary->plane;
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum old_plane_id plane_id = plane->plane;
 
-	return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
+	return I915_READ(DSPCNTR(plane_id)) & DISPLAY_PLANE_ENABLE;
 }
 
 static u32
@@ -13195,9 +13195,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
 	 */
 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
-		primary->plane = (enum plane) !pipe;
+		primary->plane = (enum old_plane_id) !pipe;
 	else
-		primary->plane = (enum plane) pipe;
+		primary->plane = (enum old_plane_id) pipe;
 	primary->id = PLANE_PRIMARY;
 	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
 	primary->check_plane = intel_check_primary_plane;
@@ -13226,16 +13226,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		num_formats = ARRAY_SIZE(i965_primary_formats);
 		modifiers = i9xx_format_modifiers;
 
-		primary->update_plane = i9xx_update_primary_plane;
-		primary->disable_plane = i9xx_disable_primary_plane;
+		primary->update_plane = i9xx_update_plane;
+		primary->disable_plane = i9xx_disable_plane;
 		primary->get_hw_state = i9xx_plane_get_hw_state;
 	} else {
 		intel_primary_formats = i8xx_primary_formats;
 		num_formats = ARRAY_SIZE(i8xx_primary_formats);
 		modifiers = i9xx_format_modifiers;
 
-		primary->update_plane = i9xx_update_primary_plane;
-		primary->disable_plane = i9xx_disable_primary_plane;
+		primary->update_plane = i9xx_update_plane;
+		primary->disable_plane = i9xx_disable_plane;
 		primary->get_hw_state = i9xx_plane_get_hw_state;
 	}
 
@@ -13319,7 +13319,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
 	cursor->can_scale = false;
 	cursor->max_downscale = 1;
 	cursor->pipe = pipe;
-	cursor->plane = pipe;
+	cursor->plane = (enum old_plane_id) pipe;
 	cursor->id = PLANE_CURSOR;
 	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
 
@@ -14693,11 +14693,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 }
 
 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
-				   struct intel_plane *primary)
+				   struct intel_plane *plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum plane plane = primary->plane;
-	u32 val = I915_READ(DSPCNTR(plane));
+	enum old_plane_id plane_id = plane->plane;
+	u32 val = I915_READ(DSPCNTR(plane_id));
 
 	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
 		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 24bbf0518473..08318260453b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -793,7 +793,7 @@ struct intel_crtc_state {
 struct intel_crtc {
 	struct drm_crtc base;
 	enum pipe pipe;
-	enum plane plane;
+	enum old_plane_id plane;
 	/*
 	 * Whether the crtc and the connected output pipeline is active. Implies
 	 * that crtc->enabled is set, i.e. the current mode configuration has
@@ -846,7 +846,7 @@ struct intel_crtc {
 
 struct intel_plane {
 	struct drm_plane base;
-	u8 plane;
+	enum old_plane_id plane;
 	enum plane_id id;
 	enum pipe pipe;
 	bool can_scale;
@@ -1133,7 +1133,7 @@ intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 }
 
 static inline struct intel_crtc *
-intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
+intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum old_plane_id plane)
 {
 	return dev_priv->plane_to_crtc_mapping[plane];
 }
-- 
2.13.6

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Re: [PATCH 3/9] drm/i915: s/enum plane/enum old_plane_id/

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:49PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Rename enum plane to enum old_plane_id to make it clear that it only
> applies to pre-SKL platforms.
> 
> v2: Reorder patches
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

old_ sounds to me like the previous in a temporal aka at runtime sense.
Which is confusing, why exactly do we want to have different enums for the
current vs. previous plane id?

This needs a better prefix, please pick one of:

i8xx_
i9xx_
i915_
legacy_

Since you stare at this code way more than I do, pls pick the one you
think is most consistent.

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  4 +-
>  drivers/gpu/drm/i915/intel_display.c | 84 ++++++++++++++++++------------------
>  drivers/gpu/drm/i915/intel_drv.h     |  6 +--
>  3 files changed, 47 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6bbc4b83aa0a..7280f9eb2e95 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -307,7 +307,7 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
>   * Global legacy plane identifier. Valid only for primary/sprite
>   * planes on pre-g4x, and only for primary planes on g4x+.
>   */
> -enum plane {
> +enum old_plane_id {
>  	PLANE_A,
>  	PLANE_B,
>  	PLANE_C,
> @@ -1128,7 +1128,7 @@ struct intel_fbc {
>  
>  		struct {
>  			enum pipe pipe;
> -			enum plane plane;
> +			enum old_plane_id plane;
>  			unsigned int fence_y_offset;
>  		} crtc;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a9fd3b8fa922..9d37c758f7b5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3223,17 +3223,17 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
>  	return 0;
>  }
>  
> -static void i9xx_update_primary_plane(struct intel_plane *primary,
> -				      const struct intel_crtc_state *crtc_state,
> -				      const struct intel_plane_state *plane_state)
> +static void i9xx_update_plane(struct intel_plane *plane,
> +			      const struct intel_crtc_state *crtc_state,
> +			      const struct intel_plane_state *plane_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
> -	enum plane plane = primary->plane;
> +	enum old_plane_id plane_id = plane->plane;
>  	u32 linear_offset;
>  	u32 dspcntr = plane_state->ctl;
> -	i915_reg_t reg = DSPCNTR(plane);
> +	i915_reg_t reg = DSPCNTR(plane_id);
>  	int x = plane_state->main.x;
>  	int y = plane_state->main.y;
>  	unsigned long irqflags;
> @@ -3254,34 +3254,34 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  		/* pipesrc and dspsize control the size that is scaled from,
>  		 * which should always be the user's requested size.
>  		 */
> -		I915_WRITE_FW(DSPSIZE(plane),
> +		I915_WRITE_FW(DSPSIZE(plane_id),
>  			      ((crtc_state->pipe_src_h - 1) << 16) |
>  			      (crtc_state->pipe_src_w - 1));
> -		I915_WRITE_FW(DSPPOS(plane), 0);
> -	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> -		I915_WRITE_FW(PRIMSIZE(plane),
> +		I915_WRITE_FW(DSPPOS(plane_id), 0);
> +	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
> +		I915_WRITE_FW(PRIMSIZE(plane_id),
>  			      ((crtc_state->pipe_src_h - 1) << 16) |
>  			      (crtc_state->pipe_src_w - 1));
> -		I915_WRITE_FW(PRIMPOS(plane), 0);
> -		I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
> +		I915_WRITE_FW(PRIMPOS(plane_id), 0);
> +		I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
>  	}
>  
>  	I915_WRITE_FW(reg, dspcntr);
>  
> -	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
> +	I915_WRITE_FW(DSPSTRIDE(plane_id), fb->pitches[0]);
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		I915_WRITE_FW(DSPSURF(plane),
> +		I915_WRITE_FW(DSPSURF(plane_id),
>  			      intel_plane_ggtt_offset(plane_state) +
>  			      crtc->dspaddr_offset);
> -		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
> +		I915_WRITE_FW(DSPOFFSET(plane_id), (y << 16) | x);
>  	} else if (INTEL_GEN(dev_priv) >= 4) {
> -		I915_WRITE_FW(DSPSURF(plane),
> +		I915_WRITE_FW(DSPSURF(plane_id),
>  			      intel_plane_ggtt_offset(plane_state) +
>  			      crtc->dspaddr_offset);
> -		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
> -		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
> +		I915_WRITE_FW(DSPTILEOFF(plane_id), (y << 16) | x);
> +		I915_WRITE_FW(DSPLINOFF(plane_id), linear_offset);
>  	} else {
> -		I915_WRITE_FW(DSPADDR(plane),
> +		I915_WRITE_FW(DSPADDR(plane_id),
>  			      intel_plane_ggtt_offset(plane_state) +
>  			      crtc->dspaddr_offset);
>  	}
> @@ -3290,31 +3290,31 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> -static void i9xx_disable_primary_plane(struct intel_plane *primary,
> -				       struct intel_crtc *crtc)
> +static void i9xx_disable_plane(struct intel_plane *plane,
> +			       struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> -	enum plane plane = primary->plane;
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum old_plane_id plane_id = plane->plane;
>  	unsigned long irqflags;
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	I915_WRITE_FW(DSPCNTR(plane), 0);
> -	if (INTEL_INFO(dev_priv)->gen >= 4)
> -		I915_WRITE_FW(DSPSURF(plane), 0);
> +	I915_WRITE_FW(DSPCNTR(plane_id), 0);
> +	if (INTEL_GEN(dev_priv) >= 4)
> +		I915_WRITE_FW(DSPSURF(plane_id), 0);
>  	else
> -		I915_WRITE_FW(DSPADDR(plane), 0);
> -	POSTING_READ_FW(DSPCNTR(plane));
> +		I915_WRITE_FW(DSPADDR(plane_id), 0);
> +	POSTING_READ_FW(DSPCNTR(plane_id));
>  
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> -static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
> +static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> -	enum plane plane = primary->plane;
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum old_plane_id plane_id = plane->plane;
>  
> -	return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
> +	return I915_READ(DSPCNTR(plane_id)) & DISPLAY_PLANE_ENABLE;
>  }
>  
>  static u32
> @@ -13195,9 +13195,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
>  	 */
>  	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
> -		primary->plane = (enum plane) !pipe;
> +		primary->plane = (enum old_plane_id) !pipe;
>  	else
> -		primary->plane = (enum plane) pipe;
> +		primary->plane = (enum old_plane_id) pipe;
>  	primary->id = PLANE_PRIMARY;
>  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
>  	primary->check_plane = intel_check_primary_plane;
> @@ -13226,16 +13226,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		num_formats = ARRAY_SIZE(i965_primary_formats);
>  		modifiers = i9xx_format_modifiers;
>  
> -		primary->update_plane = i9xx_update_primary_plane;
> -		primary->disable_plane = i9xx_disable_primary_plane;
> +		primary->update_plane = i9xx_update_plane;
> +		primary->disable_plane = i9xx_disable_plane;
>  		primary->get_hw_state = i9xx_plane_get_hw_state;
>  	} else {
>  		intel_primary_formats = i8xx_primary_formats;
>  		num_formats = ARRAY_SIZE(i8xx_primary_formats);
>  		modifiers = i9xx_format_modifiers;
>  
> -		primary->update_plane = i9xx_update_primary_plane;
> -		primary->disable_plane = i9xx_disable_primary_plane;
> +		primary->update_plane = i9xx_update_plane;
> +		primary->disable_plane = i9xx_disable_plane;
>  		primary->get_hw_state = i9xx_plane_get_hw_state;

Misplace hunk I presume, presumable in the patch reordering. Please split
out.

With those two bikesheds addressed:

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

(for both of the resulting patches, assuming you still appease CI and gcc
and the 2nd patch has a reasonable commit message ofc).

Cheers, Daniel

>  	}
>  
> @@ -13319,7 +13319,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>  	cursor->can_scale = false;
>  	cursor->max_downscale = 1;
>  	cursor->pipe = pipe;
> -	cursor->plane = pipe;
> +	cursor->plane = (enum old_plane_id) pipe;
>  	cursor->id = PLANE_CURSOR;
>  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
>  
> @@ -14693,11 +14693,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  }
>  
>  static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
> -				   struct intel_plane *primary)
> +				   struct intel_plane *plane)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum plane plane = primary->plane;
> -	u32 val = I915_READ(DSPCNTR(plane));
> +	enum old_plane_id plane_id = plane->plane;
> +	u32 val = I915_READ(DSPCNTR(plane_id));
>  
>  	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
>  		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 24bbf0518473..08318260453b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -793,7 +793,7 @@ struct intel_crtc_state {
>  struct intel_crtc {
>  	struct drm_crtc base;
>  	enum pipe pipe;
> -	enum plane plane;
> +	enum old_plane_id plane;
>  	/*
>  	 * Whether the crtc and the connected output pipeline is active. Implies
>  	 * that crtc->enabled is set, i.e. the current mode configuration has
> @@ -846,7 +846,7 @@ struct intel_crtc {
>  
>  struct intel_plane {
>  	struct drm_plane base;
> -	u8 plane;
> +	enum old_plane_id plane;
>  	enum plane_id id;
>  	enum pipe pipe;
>  	bool can_scale;
> @@ -1133,7 +1133,7 @@ intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  }
>  
>  static inline struct intel_crtc *
> -intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
> +intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum old_plane_id plane)
>  {
>  	return dev_priv->plane_to_crtc_mapping[plane];
>  }
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 3/9] drm/i915: s/enum plane/enum old_plane_id/

[Ville Syrjälä]

On Thu, Oct 12, 2017 at 09:06:24PM +0200, Daniel Vetter wrote:
> On Wed, Oct 11, 2017 at 07:04:49PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Rename enum plane to enum old_plane_id to make it clear that it only
> > applies to pre-SKL platforms.
> > 
> > v2: Reorder patches
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> old_ sounds to me like the previous in a temporal aka at runtime sense.
> Which is confusing, why exactly do we want to have different enums for the
> current vs. previous plane id?

The "old" ID is a global identifier, the "new" one is per-pipe. We need
the old one to index the primary plane registers on pre-skl. I've not yet
entirely figured out how we should handle planes that can move between
pipes (on pre-g4x) when it comes to the per-pipe identifier. But for now
I'm happy to defer that until I really need to ;)

> 
> This needs a better prefix, please pick one of:
> 
> i8xx_
> i9xx_
> i915_
> legacy_

legacy_ is what I proposed previously, but I don't particularly like it
on account of its length. i9xx_ might be a decent choice actually, since
all the pre-skl (primary) plane functions are now called i9xx_ as well.
I'll respin with that, unless someone has a better idea?

> 
> Since you stare at this code way more than I do, pls pick the one you
> think is most consistent.
> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  4 +-
> >  drivers/gpu/drm/i915/intel_display.c | 84 ++++++++++++++++++------------------
> >  drivers/gpu/drm/i915/intel_drv.h     |  6 +--
> >  3 files changed, 47 insertions(+), 47 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 6bbc4b83aa0a..7280f9eb2e95 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -307,7 +307,7 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
> >   * Global legacy plane identifier. Valid only for primary/sprite
> >   * planes on pre-g4x, and only for primary planes on g4x+.
> >   */
> > -enum plane {
> > +enum old_plane_id {
> >  	PLANE_A,
> >  	PLANE_B,
> >  	PLANE_C,
> > @@ -1128,7 +1128,7 @@ struct intel_fbc {
> >  
> >  		struct {
> >  			enum pipe pipe;
> > -			enum plane plane;
> > +			enum old_plane_id plane;
> >  			unsigned int fence_y_offset;
> >  		} crtc;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a9fd3b8fa922..9d37c758f7b5 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3223,17 +3223,17 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> >  	return 0;
> >  }
> >  
> > -static void i9xx_update_primary_plane(struct intel_plane *primary,
> > -				      const struct intel_crtc_state *crtc_state,
> > -				      const struct intel_plane_state *plane_state)
> > +static void i9xx_update_plane(struct intel_plane *plane,
> > +			      const struct intel_crtc_state *crtc_state,
> > +			      const struct intel_plane_state *plane_state)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> > -	enum plane plane = primary->plane;
> > +	enum old_plane_id plane_id = plane->plane;
> >  	u32 linear_offset;
> >  	u32 dspcntr = plane_state->ctl;
> > -	i915_reg_t reg = DSPCNTR(plane);
> > +	i915_reg_t reg = DSPCNTR(plane_id);
> >  	int x = plane_state->main.x;
> >  	int y = plane_state->main.y;
> >  	unsigned long irqflags;
> > @@ -3254,34 +3254,34 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
> >  		/* pipesrc and dspsize control the size that is scaled from,
> >  		 * which should always be the user's requested size.
> >  		 */
> > -		I915_WRITE_FW(DSPSIZE(plane),
> > +		I915_WRITE_FW(DSPSIZE(plane_id),
> >  			      ((crtc_state->pipe_src_h - 1) << 16) |
> >  			      (crtc_state->pipe_src_w - 1));
> > -		I915_WRITE_FW(DSPPOS(plane), 0);
> > -	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> > -		I915_WRITE_FW(PRIMSIZE(plane),
> > +		I915_WRITE_FW(DSPPOS(plane_id), 0);
> > +	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
> > +		I915_WRITE_FW(PRIMSIZE(plane_id),
> >  			      ((crtc_state->pipe_src_h - 1) << 16) |
> >  			      (crtc_state->pipe_src_w - 1));
> > -		I915_WRITE_FW(PRIMPOS(plane), 0);
> > -		I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
> > +		I915_WRITE_FW(PRIMPOS(plane_id), 0);
> > +		I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
> >  	}
> >  
> >  	I915_WRITE_FW(reg, dspcntr);
> >  
> > -	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
> > +	I915_WRITE_FW(DSPSTRIDE(plane_id), fb->pitches[0]);
> >  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > -		I915_WRITE_FW(DSPSURF(plane),
> > +		I915_WRITE_FW(DSPSURF(plane_id),
> >  			      intel_plane_ggtt_offset(plane_state) +
> >  			      crtc->dspaddr_offset);
> > -		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
> > +		I915_WRITE_FW(DSPOFFSET(plane_id), (y << 16) | x);
> >  	} else if (INTEL_GEN(dev_priv) >= 4) {
> > -		I915_WRITE_FW(DSPSURF(plane),
> > +		I915_WRITE_FW(DSPSURF(plane_id),
> >  			      intel_plane_ggtt_offset(plane_state) +
> >  			      crtc->dspaddr_offset);
> > -		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
> > -		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
> > +		I915_WRITE_FW(DSPTILEOFF(plane_id), (y << 16) | x);
> > +		I915_WRITE_FW(DSPLINOFF(plane_id), linear_offset);
> >  	} else {
> > -		I915_WRITE_FW(DSPADDR(plane),
> > +		I915_WRITE_FW(DSPADDR(plane_id),
> >  			      intel_plane_ggtt_offset(plane_state) +
> >  			      crtc->dspaddr_offset);
> >  	}
> > @@ -3290,31 +3290,31 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > -static void i9xx_disable_primary_plane(struct intel_plane *primary,
> > -				       struct intel_crtc *crtc)
> > +static void i9xx_disable_plane(struct intel_plane *plane,
> > +			       struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > -	enum plane plane = primary->plane;
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum old_plane_id plane_id = plane->plane;
> >  	unsigned long irqflags;
> >  
> >  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >  
> > -	I915_WRITE_FW(DSPCNTR(plane), 0);
> > -	if (INTEL_INFO(dev_priv)->gen >= 4)
> > -		I915_WRITE_FW(DSPSURF(plane), 0);
> > +	I915_WRITE_FW(DSPCNTR(plane_id), 0);
> > +	if (INTEL_GEN(dev_priv) >= 4)
> > +		I915_WRITE_FW(DSPSURF(plane_id), 0);
> >  	else
> > -		I915_WRITE_FW(DSPADDR(plane), 0);
> > -	POSTING_READ_FW(DSPCNTR(plane));
> > +		I915_WRITE_FW(DSPADDR(plane_id), 0);
> > +	POSTING_READ_FW(DSPCNTR(plane_id));
> >  
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  }
> >  
> > -static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
> > +static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > -	enum plane plane = primary->plane;
> > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	enum old_plane_id plane_id = plane->plane;
> >  
> > -	return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
> > +	return I915_READ(DSPCNTR(plane_id)) & DISPLAY_PLANE_ENABLE;
> >  }
> >  
> >  static u32
> > @@ -13195,9 +13195,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
> >  	 */
> >  	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
> > -		primary->plane = (enum plane) !pipe;
> > +		primary->plane = (enum old_plane_id) !pipe;
> >  	else
> > -		primary->plane = (enum plane) pipe;
> > +		primary->plane = (enum old_plane_id) pipe;
> >  	primary->id = PLANE_PRIMARY;
> >  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
> >  	primary->check_plane = intel_check_primary_plane;
> > @@ -13226,16 +13226,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  		num_formats = ARRAY_SIZE(i965_primary_formats);
> >  		modifiers = i9xx_format_modifiers;
> >  
> > -		primary->update_plane = i9xx_update_primary_plane;
> > -		primary->disable_plane = i9xx_disable_primary_plane;
> > +		primary->update_plane = i9xx_update_plane;
> > +		primary->disable_plane = i9xx_disable_plane;
> >  		primary->get_hw_state = i9xx_plane_get_hw_state;
> >  	} else {
> >  		intel_primary_formats = i8xx_primary_formats;
> >  		num_formats = ARRAY_SIZE(i8xx_primary_formats);
> >  		modifiers = i9xx_format_modifiers;
> >  
> > -		primary->update_plane = i9xx_update_primary_plane;
> > -		primary->disable_plane = i9xx_disable_primary_plane;
> > +		primary->update_plane = i9xx_update_plane;
> > +		primary->disable_plane = i9xx_disable_plane;
> >  		primary->get_hw_state = i9xx_plane_get_hw_state;
> 
> Misplace hunk I presume, presumable in the patch reordering. Please split
> out.
> 
> With those two bikesheds addressed:
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> (for both of the resulting patches, assuming you still appease CI and gcc
> and the 2nd patch has a reasonable commit message ofc).
> 
> Cheers, Daniel
> 
> >  	}
> >  
> > @@ -13319,7 +13319,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> >  	cursor->can_scale = false;
> >  	cursor->max_downscale = 1;
> >  	cursor->pipe = pipe;
> > -	cursor->plane = pipe;
> > +	cursor->plane = (enum old_plane_id) pipe;
> >  	cursor->id = PLANE_CURSOR;
> >  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
> >  
> > @@ -14693,11 +14693,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  }
> >  
> >  static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
> > -				   struct intel_plane *primary)
> > +				   struct intel_plane *plane)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	enum plane plane = primary->plane;
> > -	u32 val = I915_READ(DSPCNTR(plane));
> > +	enum old_plane_id plane_id = plane->plane;
> > +	u32 val = I915_READ(DSPCNTR(plane_id));
> >  
> >  	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
> >  		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 24bbf0518473..08318260453b 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -793,7 +793,7 @@ struct intel_crtc_state {
> >  struct intel_crtc {
> >  	struct drm_crtc base;
> >  	enum pipe pipe;
> > -	enum plane plane;
> > +	enum old_plane_id plane;
> >  	/*
> >  	 * Whether the crtc and the connected output pipeline is active. Implies
> >  	 * that crtc->enabled is set, i.e. the current mode configuration has
> > @@ -846,7 +846,7 @@ struct intel_crtc {
> >  
> >  struct intel_plane {
> >  	struct drm_plane base;
> > -	u8 plane;
> > +	enum old_plane_id plane;
> >  	enum plane_id id;
> >  	enum pipe pipe;
> >  	bool can_scale;
> > @@ -1133,7 +1133,7 @@ intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  }
> >  
> >  static inline struct intel_crtc *
> > -intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
> > +intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum old_plane_id plane)
> >  {
> >  	return dev_priv->plane_to_crtc_mapping[plane];
> >  }
> > -- 
> > 2.13.6
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/9] drm/i915: s/enum plane/enum old_plane_id/

[Daniel Vetter]

On Fri, Oct 13, 2017 at 01:35:05PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 12, 2017 at 09:06:24PM +0200, Daniel Vetter wrote:
> > On Wed, Oct 11, 2017 at 07:04:49PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Rename enum plane to enum old_plane_id to make it clear that it only
> > > applies to pre-SKL platforms.
> > > 
> > > v2: Reorder patches
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > old_ sounds to me like the previous in a temporal aka at runtime sense.
> > Which is confusing, why exactly do we want to have different enums for the
> > current vs. previous plane id?
> 
> The "old" ID is a global identifier, the "new" one is per-pipe. We need
> the old one to index the primary plane registers on pre-skl. I've not yet
> entirely figured out how we should handle planes that can move between
> pipes (on pre-g4x) when it comes to the per-pipe identifier. But for now
> I'm happy to defer that until I really need to ;)
> 
> > 
> > This needs a better prefix, please pick one of:
> > 
> > i8xx_
> > i9xx_
> > i915_
> > legacy_
> 
> legacy_ is what I proposed previously, but I don't particularly like it
> on account of its length. i9xx_ might be a decent choice actually, since
> all the pre-skl (primary) plane functions are now called i9xx_ as well.
> I'll respin with that, unless someone has a better idea?

+1 from me on i9xx_, seems like the best choice. I just tried to list all
the ones that crossed my mind.
-Daniel

> 
> > 
> > Since you stare at this code way more than I do, pls pick the one you
> > think is most consistent.
> > 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h      |  4 +-
> > >  drivers/gpu/drm/i915/intel_display.c | 84 ++++++++++++++++++------------------
> > >  drivers/gpu/drm/i915/intel_drv.h     |  6 +--
> > >  3 files changed, 47 insertions(+), 47 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 6bbc4b83aa0a..7280f9eb2e95 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -307,7 +307,7 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
> > >   * Global legacy plane identifier. Valid only for primary/sprite
> > >   * planes on pre-g4x, and only for primary planes on g4x+.
> > >   */
> > > -enum plane {
> > > +enum old_plane_id {
> > >  	PLANE_A,
> > >  	PLANE_B,
> > >  	PLANE_C,
> > > @@ -1128,7 +1128,7 @@ struct intel_fbc {
> > >  
> > >  		struct {
> > >  			enum pipe pipe;
> > > -			enum plane plane;
> > > +			enum old_plane_id plane;
> > >  			unsigned int fence_y_offset;
> > >  		} crtc;
> > >  
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index a9fd3b8fa922..9d37c758f7b5 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3223,17 +3223,17 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> > >  	return 0;
> > >  }
> > >  
> > > -static void i9xx_update_primary_plane(struct intel_plane *primary,
> > > -				      const struct intel_crtc_state *crtc_state,
> > > -				      const struct intel_plane_state *plane_state)
> > > +static void i9xx_update_plane(struct intel_plane *plane,
> > > +			      const struct intel_crtc_state *crtc_state,
> > > +			      const struct intel_plane_state *plane_state)
> > >  {
> > > -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> > > -	enum plane plane = primary->plane;
> > > +	enum old_plane_id plane_id = plane->plane;
> > >  	u32 linear_offset;
> > >  	u32 dspcntr = plane_state->ctl;
> > > -	i915_reg_t reg = DSPCNTR(plane);
> > > +	i915_reg_t reg = DSPCNTR(plane_id);
> > >  	int x = plane_state->main.x;
> > >  	int y = plane_state->main.y;
> > >  	unsigned long irqflags;
> > > @@ -3254,34 +3254,34 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
> > >  		/* pipesrc and dspsize control the size that is scaled from,
> > >  		 * which should always be the user's requested size.
> > >  		 */
> > > -		I915_WRITE_FW(DSPSIZE(plane),
> > > +		I915_WRITE_FW(DSPSIZE(plane_id),
> > >  			      ((crtc_state->pipe_src_h - 1) << 16) |
> > >  			      (crtc_state->pipe_src_w - 1));
> > > -		I915_WRITE_FW(DSPPOS(plane), 0);
> > > -	} else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> > > -		I915_WRITE_FW(PRIMSIZE(plane),
> > > +		I915_WRITE_FW(DSPPOS(plane_id), 0);
> > > +	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
> > > +		I915_WRITE_FW(PRIMSIZE(plane_id),
> > >  			      ((crtc_state->pipe_src_h - 1) << 16) |
> > >  			      (crtc_state->pipe_src_w - 1));
> > > -		I915_WRITE_FW(PRIMPOS(plane), 0);
> > > -		I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
> > > +		I915_WRITE_FW(PRIMPOS(plane_id), 0);
> > > +		I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
> > >  	}
> > >  
> > >  	I915_WRITE_FW(reg, dspcntr);
> > >  
> > > -	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
> > > +	I915_WRITE_FW(DSPSTRIDE(plane_id), fb->pitches[0]);
> > >  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > -		I915_WRITE_FW(DSPSURF(plane),
> > > +		I915_WRITE_FW(DSPSURF(plane_id),
> > >  			      intel_plane_ggtt_offset(plane_state) +
> > >  			      crtc->dspaddr_offset);
> > > -		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
> > > +		I915_WRITE_FW(DSPOFFSET(plane_id), (y << 16) | x);
> > >  	} else if (INTEL_GEN(dev_priv) >= 4) {
> > > -		I915_WRITE_FW(DSPSURF(plane),
> > > +		I915_WRITE_FW(DSPSURF(plane_id),
> > >  			      intel_plane_ggtt_offset(plane_state) +
> > >  			      crtc->dspaddr_offset);
> > > -		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
> > > -		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
> > > +		I915_WRITE_FW(DSPTILEOFF(plane_id), (y << 16) | x);
> > > +		I915_WRITE_FW(DSPLINOFF(plane_id), linear_offset);
> > >  	} else {
> > > -		I915_WRITE_FW(DSPADDR(plane),
> > > +		I915_WRITE_FW(DSPADDR(plane_id),
> > >  			      intel_plane_ggtt_offset(plane_state) +
> > >  			      crtc->dspaddr_offset);
> > >  	}
> > > @@ -3290,31 +3290,31 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
> > >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > >  }
> > >  
> > > -static void i9xx_disable_primary_plane(struct intel_plane *primary,
> > > -				       struct intel_crtc *crtc)
> > > +static void i9xx_disable_plane(struct intel_plane *plane,
> > > +			       struct intel_crtc *crtc)
> > >  {
> > > -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > > -	enum plane plane = primary->plane;
> > > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > +	enum old_plane_id plane_id = plane->plane;
> > >  	unsigned long irqflags;
> > >  
> > >  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >  
> > > -	I915_WRITE_FW(DSPCNTR(plane), 0);
> > > -	if (INTEL_INFO(dev_priv)->gen >= 4)
> > > -		I915_WRITE_FW(DSPSURF(plane), 0);
> > > +	I915_WRITE_FW(DSPCNTR(plane_id), 0);
> > > +	if (INTEL_GEN(dev_priv) >= 4)
> > > +		I915_WRITE_FW(DSPSURF(plane_id), 0);
> > >  	else
> > > -		I915_WRITE_FW(DSPADDR(plane), 0);
> > > -	POSTING_READ_FW(DSPCNTR(plane));
> > > +		I915_WRITE_FW(DSPADDR(plane_id), 0);
> > > +	POSTING_READ_FW(DSPCNTR(plane_id));
> > >  
> > >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > >  }
> > >  
> > > -static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
> > > +static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
> > >  {
> > > -	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > > -	enum plane plane = primary->plane;
> > > +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > +	enum old_plane_id plane_id = plane->plane;
> > >  
> > > -	return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
> > > +	return I915_READ(DSPCNTR(plane_id)) & DISPLAY_PLANE_ENABLE;
> > >  }
> > >  
> > >  static u32
> > > @@ -13195,9 +13195,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> > >  	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
> > >  	 */
> > >  	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
> > > -		primary->plane = (enum plane) !pipe;
> > > +		primary->plane = (enum old_plane_id) !pipe;
> > >  	else
> > > -		primary->plane = (enum plane) pipe;
> > > +		primary->plane = (enum old_plane_id) pipe;
> > >  	primary->id = PLANE_PRIMARY;
> > >  	primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
> > >  	primary->check_plane = intel_check_primary_plane;
> > > @@ -13226,16 +13226,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> > >  		num_formats = ARRAY_SIZE(i965_primary_formats);
> > >  		modifiers = i9xx_format_modifiers;
> > >  
> > > -		primary->update_plane = i9xx_update_primary_plane;
> > > -		primary->disable_plane = i9xx_disable_primary_plane;
> > > +		primary->update_plane = i9xx_update_plane;
> > > +		primary->disable_plane = i9xx_disable_plane;
> > >  		primary->get_hw_state = i9xx_plane_get_hw_state;
> > >  	} else {
> > >  		intel_primary_formats = i8xx_primary_formats;
> > >  		num_formats = ARRAY_SIZE(i8xx_primary_formats);
> > >  		modifiers = i9xx_format_modifiers;
> > >  
> > > -		primary->update_plane = i9xx_update_primary_plane;
> > > -		primary->disable_plane = i9xx_disable_primary_plane;
> > > +		primary->update_plane = i9xx_update_plane;
> > > +		primary->disable_plane = i9xx_disable_plane;
> > >  		primary->get_hw_state = i9xx_plane_get_hw_state;
> > 
> > Misplace hunk I presume, presumable in the patch reordering. Please split
> > out.
> > 
> > With those two bikesheds addressed:
> > 
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > 
> > (for both of the resulting patches, assuming you still appease CI and gcc
> > and the 2nd patch has a reasonable commit message ofc).
> > 
> > Cheers, Daniel
> > 
> > >  	}
> > >  
> > > @@ -13319,7 +13319,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > >  	cursor->can_scale = false;
> > >  	cursor->max_downscale = 1;
> > >  	cursor->pipe = pipe;
> > > -	cursor->plane = pipe;
> > > +	cursor->plane = (enum old_plane_id) pipe;
> > >  	cursor->id = PLANE_CURSOR;
> > >  	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
> > >  
> > > @@ -14693,11 +14693,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> > >  }
> > >  
> > >  static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
> > > -				   struct intel_plane *primary)
> > > +				   struct intel_plane *plane)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > -	enum plane plane = primary->plane;
> > > -	u32 val = I915_READ(DSPCNTR(plane));
> > > +	enum old_plane_id plane_id = plane->plane;
> > > +	u32 val = I915_READ(DSPCNTR(plane_id));
> > >  
> > >  	return (val & DISPLAY_PLANE_ENABLE) == 0 ||
> > >  		(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index 24bbf0518473..08318260453b 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -793,7 +793,7 @@ struct intel_crtc_state {
> > >  struct intel_crtc {
> > >  	struct drm_crtc base;
> > >  	enum pipe pipe;
> > > -	enum plane plane;
> > > +	enum old_plane_id plane;
> > >  	/*
> > >  	 * Whether the crtc and the connected output pipeline is active. Implies
> > >  	 * that crtc->enabled is set, i.e. the current mode configuration has
> > > @@ -846,7 +846,7 @@ struct intel_crtc {
> > >  
> > >  struct intel_plane {
> > >  	struct drm_plane base;
> > > -	u8 plane;
> > > +	enum old_plane_id plane;
> > >  	enum plane_id id;
> > >  	enum pipe pipe;
> > >  	bool can_scale;
> > > @@ -1133,7 +1133,7 @@ intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> > >  }
> > >  
> > >  static inline struct intel_crtc *
> > > -intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
> > > +intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum old_plane_id plane)
> > >  {
> > >  	return dev_priv->plane_to_crtc_mapping[plane];
> > >  }
> > > -- 
> > > 2.13.6
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 4/9] drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++-
 drivers/gpu/drm/i915/intel_pm.c | 36 +++++++++++++++++++-----------------
 2 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7280f9eb2e95..df120a38ae42 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -699,7 +699,8 @@ struct drm_i915_display_funcs {
 			  struct intel_cdclk_state *cdclk_state);
 	void (*set_cdclk)(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_state *cdclk_state);
-	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
+	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
+			     enum old_plane_id plane_id);
 	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
 	int (*compute_intermediate_wm)(struct drm_device *dev,
 				       struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2fcff9788b6f..13f1010eea77 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -521,38 +521,41 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 	fifo_state->plane[PLANE_CURSOR] = 63;
 }
 
-static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
+			      enum old_plane_id plane_id)
 {
 	uint32_t dsparb = I915_READ(DSPARB);
 	int size;
 
 	size = dsparb & 0x7f;
-	if (plane)
+	if (plane_id == PLANE_B)
 		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 
-	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
-		      plane ? "B" : "A", size);
+	DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+		      dsparb, plane_name(plane_id), size);
 
 	return size;
 }
 
-static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
+			      enum old_plane_id plane_id)
 {
 	uint32_t dsparb = I915_READ(DSPARB);
 	int size;
 
 	size = dsparb & 0x1ff;
-	if (plane)
+	if (plane_id == PLANE_B)
 		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 	size >>= 1; /* Convert to cachelines */
 
-	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
-		      plane ? "B" : "A", size);
+	DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+		      dsparb, plane_name(plane_id), size);
 
 	return size;
 }
 
-static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
+static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
+			      enum old_plane_id plane_id)
 {
 	uint32_t dsparb = I915_READ(DSPARB);
 	int size;
@@ -560,9 +563,8 @@ static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 	size = dsparb & 0x7f;
 	size >>= 2; /* Convert to cachelines */
 
-	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
-		      plane ? "B" : "A",
-		      size);
+	DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
+		      dsparb, plane_name(plane_id), size);
 
 	return size;
 }
@@ -2261,8 +2263,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	else
 		wm_info = &i830_a_wm_info;
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
-	crtc = intel_get_crtc_for_plane(dev_priv, 0);
+	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
 	if (intel_crtc_active(crtc)) {
 		const struct drm_display_mode *adjusted_mode =
 			&crtc->config->base.adjusted_mode;
@@ -2288,8 +2290,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	if (IS_GEN2(dev_priv))
 		wm_info = &i830_bc_wm_info;
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
-	crtc = intel_get_crtc_for_plane(dev_priv, 1);
+	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
 	if (intel_crtc_active(crtc)) {
 		const struct drm_display_mode *adjusted_mode =
 			&crtc->config->base.adjusted_mode;
@@ -2401,7 +2403,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 	adjusted_mode = &crtc->config->base.adjusted_mode;
 	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
 				       &i845_wm_info,
-				       dev_priv->display.get_fifo_size(dev_priv, 0),
+				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
 				       4, pessimal_latency_ns);
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
 	fwater_lo |= (3<<8) | planea_wm;
-- 
2.13.6

_______________________________________________
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Re: [PATCH 4/9] drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:50PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

With the bikeshed from the preceeding patch applied here too:

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> ---
>  drivers/gpu/drm/i915/i915_drv.h |  3 ++-
>  drivers/gpu/drm/i915/intel_pm.c | 36 +++++++++++++++++++-----------------
>  2 files changed, 21 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7280f9eb2e95..df120a38ae42 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -699,7 +699,8 @@ struct drm_i915_display_funcs {
>  			  struct intel_cdclk_state *cdclk_state);
>  	void (*set_cdclk)(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_state *cdclk_state);
> -	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
> +	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
> +			     enum old_plane_id plane_id);
>  	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
>  	int (*compute_intermediate_wm)(struct drm_device *dev,
>  				       struct intel_crtc *intel_crtc,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2fcff9788b6f..13f1010eea77 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -521,38 +521,41 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  	fifo_state->plane[PLANE_CURSOR] = 63;
>  }
>  
> -static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
> +static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
> +			      enum old_plane_id plane_id)
>  {
>  	uint32_t dsparb = I915_READ(DSPARB);
>  	int size;
>  
>  	size = dsparb & 0x7f;
> -	if (plane)
> +	if (plane_id == PLANE_B)
>  		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
>  
> -	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
> -		      plane ? "B" : "A", size);
> +	DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
> +		      dsparb, plane_name(plane_id), size);
>  
>  	return size;
>  }
>  
> -static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
> +static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
> +			      enum old_plane_id plane_id)
>  {
>  	uint32_t dsparb = I915_READ(DSPARB);
>  	int size;
>  
>  	size = dsparb & 0x1ff;
> -	if (plane)
> +	if (plane_id == PLANE_B)
>  		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
>  	size >>= 1; /* Convert to cachelines */
>  
> -	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
> -		      plane ? "B" : "A", size);
> +	DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
> +		      dsparb, plane_name(plane_id), size);
>  
>  	return size;
>  }
>  
> -static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
> +static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
> +			      enum old_plane_id plane_id)
>  {
>  	uint32_t dsparb = I915_READ(DSPARB);
>  	int size;
> @@ -560,9 +563,8 @@ static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
>  	size = dsparb & 0x7f;
>  	size >>= 2; /* Convert to cachelines */
>  
> -	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
> -		      plane ? "B" : "A",
> -		      size);
> +	DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
> +		      dsparb, plane_name(plane_id), size);
>  
>  	return size;
>  }
> @@ -2261,8 +2263,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	else
>  		wm_info = &i830_a_wm_info;
>  
> -	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
> -	crtc = intel_get_crtc_for_plane(dev_priv, 0);
> +	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
> +	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
>  	if (intel_crtc_active(crtc)) {
>  		const struct drm_display_mode *adjusted_mode =
>  			&crtc->config->base.adjusted_mode;
> @@ -2288,8 +2290,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	if (IS_GEN2(dev_priv))
>  		wm_info = &i830_bc_wm_info;
>  
> -	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
> -	crtc = intel_get_crtc_for_plane(dev_priv, 1);
> +	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> +	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
>  	if (intel_crtc_active(crtc)) {
>  		const struct drm_display_mode *adjusted_mode =
>  			&crtc->config->base.adjusted_mode;
> @@ -2401,7 +2403,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
>  	adjusted_mode = &crtc->config->base.adjusted_mode;
>  	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
>  				       &i845_wm_info,
> -				       dev_priv->display.get_fifo_size(dev_priv, 0),
> +				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
>  				       4, pessimal_latency_ns);
>  	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
>  	fwater_lo |= (3<<8) | planea_wm;
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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[PATCH 5/9] drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial fb readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use enum pipe, enum plane_id, and enum old_plane_id consistently in the
initial framebuffe readout.

v2: Use old_plane_id in the ilk code

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 58 ++++++++++++++++++++----------------
 1 file changed, 32 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9d37c758f7b5..21160a06ab36 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7456,14 +7456,16 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	enum old_plane_id plane_id = plane->plane;
+	enum pipe pipe = crtc->pipe;
 	u32 val, base, offset;
-	int pipe = crtc->pipe, plane = crtc->plane;
 	int fourcc, pixel_format;
 	unsigned int aligned_height;
 	struct drm_framebuffer *fb;
 	struct intel_framebuffer *intel_fb;
 
-	val = I915_READ(DSPCNTR(plane));
+	val = I915_READ(DSPCNTR(plane_id));
 	if (!(val & DISPLAY_PLANE_ENABLE))
 		return;
 
@@ -7490,12 +7492,12 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	if (INTEL_GEN(dev_priv) >= 4) {
 		if (plane_config->tiling)
-			offset = I915_READ(DSPTILEOFF(plane));
+			offset = I915_READ(DSPTILEOFF(plane_id));
 		else
-			offset = I915_READ(DSPLINOFF(plane));
-		base = I915_READ(DSPSURF(plane)) & 0xfffff000;
+			offset = I915_READ(DSPLINOFF(plane_id));
+		base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
 	} else {
-		base = I915_READ(DSPADDR(plane));
+		base = I915_READ(DSPADDR(plane_id));
 	}
 	plane_config->base = base;
 
@@ -7503,15 +7505,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	fb->width = ((val >> 16) & 0xfff) + 1;
 	fb->height = ((val >> 0) & 0xfff) + 1;
 
-	val = I915_READ(DSPSTRIDE(pipe));
+	val = I915_READ(DSPSTRIDE(plane_id));
 	fb->pitches[0] = val & 0xffffffc0;
 
 	aligned_height = intel_fb_align_height(fb, 0, fb->height);
 
 	plane_config->size = fb->pitches[0] * aligned_height;
 
-	DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
-		      pipe_name(pipe), plane, fb->width, fb->height,
+	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
+		      crtc->base.name, plane->base.name, fb->width, fb->height,
 		      fb->format->cpp[0] * 8, base, fb->pitches[0],
 		      plane_config->size);
 
@@ -8482,8 +8484,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = crtc->pipe;
 	u32 val, base, offset, stride_mult, tiling;
-	int pipe = crtc->pipe;
 	int fourcc, pixel_format;
 	unsigned int aligned_height;
 	struct drm_framebuffer *fb;
@@ -8499,7 +8503,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	fb->dev = dev;
 
-	val = I915_READ(PLANE_CTL(pipe, 0));
+	val = I915_READ(PLANE_CTL(pipe, plane_id));
 	if (!(val & PLANE_CTL_ENABLE))
 		goto error;
 
@@ -8535,16 +8539,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 		goto error;
 	}
 
-	base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
+	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
 	plane_config->base = base;
 
-	offset = I915_READ(PLANE_OFFSET(pipe, 0));
+	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
 
-	val = I915_READ(PLANE_SIZE(pipe, 0));
+	val = I915_READ(PLANE_SIZE(pipe, plane_id));
 	fb->height = ((val >> 16) & 0xfff) + 1;
 	fb->width = ((val >> 0) & 0x1fff) + 1;
 
-	val = I915_READ(PLANE_STRIDE(pipe, 0));
+	val = I915_READ(PLANE_STRIDE(pipe, plane_id));
 	stride_mult = intel_fb_stride_alignment(fb, 0);
 	fb->pitches[0] = (val & 0x3ff) * stride_mult;
 
@@ -8552,8 +8556,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	plane_config->size = fb->pitches[0] * aligned_height;
 
-	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
-		      pipe_name(pipe), fb->width, fb->height,
+	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
+		      crtc->base.name, plane->base.name, fb->width, fb->height,
 		      fb->format->cpp[0] * 8, base, fb->pitches[0],
 		      plane_config->size);
 
@@ -8594,14 +8598,16 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	enum old_plane_id plane_id = plane->plane;
+	enum pipe pipe = crtc->pipe;
 	u32 val, base, offset;
-	int pipe = crtc->pipe;
 	int fourcc, pixel_format;
 	unsigned int aligned_height;
 	struct drm_framebuffer *fb;
 	struct intel_framebuffer *intel_fb;
 
-	val = I915_READ(DSPCNTR(pipe));
+	val = I915_READ(DSPCNTR(plane_id));
 	if (!(val & DISPLAY_PLANE_ENABLE))
 		return;
 
@@ -8626,14 +8632,14 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 	fourcc = i9xx_format_to_fourcc(pixel_format);
 	fb->format = drm_format_info(fourcc);
 
-	base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
+	base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		offset = I915_READ(DSPOFFSET(pipe));
+		offset = I915_READ(DSPOFFSET(plane_id));
 	} else {
 		if (plane_config->tiling)
-			offset = I915_READ(DSPTILEOFF(pipe));
+			offset = I915_READ(DSPTILEOFF(plane_id));
 		else
-			offset = I915_READ(DSPLINOFF(pipe));
+			offset = I915_READ(DSPLINOFF(plane_id));
 	}
 	plane_config->base = base;
 
@@ -8641,15 +8647,15 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 	fb->width = ((val >> 16) & 0xfff) + 1;
 	fb->height = ((val >> 0) & 0xfff) + 1;
 
-	val = I915_READ(DSPSTRIDE(pipe));
+	val = I915_READ(DSPSTRIDE(plane_id));
 	fb->pitches[0] = val & 0xffffffc0;
 
 	aligned_height = intel_fb_align_height(fb, 0, fb->height);
 
 	plane_config->size = fb->pitches[0] * aligned_height;
 
-	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
-		      pipe_name(pipe), fb->width, fb->height,
+	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
+		      crtc->base.name, plane->base.name, fb->width, fb->height,
 		      fb->format->cpp[0] * 8, base, fb->pitches[0],
 		      plane_config->size);
 
-- 
2.13.6

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Re: [PATCH 5/9] drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial fb readout

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:51PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use enum pipe, enum plane_id, and enum old_plane_id consistently in the
> initial framebuffe readout.
> 
> v2: Use old_plane_id in the ilk code
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I didn't check whether you caught them all, but I hope someone with the
pain tolerance to compile the kernel with clang with catch those :-)

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 58 ++++++++++++++++++++----------------
>  1 file changed, 32 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9d37c758f7b5..21160a06ab36 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7456,14 +7456,16 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	enum old_plane_id plane_id = plane->plane;
> +	enum pipe pipe = crtc->pipe;
>  	u32 val, base, offset;
> -	int pipe = crtc->pipe, plane = crtc->plane;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
>  	struct intel_framebuffer *intel_fb;
>  
> -	val = I915_READ(DSPCNTR(plane));
> +	val = I915_READ(DSPCNTR(plane_id));
>  	if (!(val & DISPLAY_PLANE_ENABLE))
>  		return;
>  
> @@ -7490,12 +7492,12 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	if (INTEL_GEN(dev_priv) >= 4) {
>  		if (plane_config->tiling)
> -			offset = I915_READ(DSPTILEOFF(plane));
> +			offset = I915_READ(DSPTILEOFF(plane_id));
>  		else
> -			offset = I915_READ(DSPLINOFF(plane));
> -		base = I915_READ(DSPSURF(plane)) & 0xfffff000;
> +			offset = I915_READ(DSPLINOFF(plane_id));
> +		base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
>  	} else {
> -		base = I915_READ(DSPADDR(plane));
> +		base = I915_READ(DSPADDR(plane_id));
>  	}
>  	plane_config->base = base;
>  
> @@ -7503,15 +7505,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  	fb->width = ((val >> 16) & 0xfff) + 1;
>  	fb->height = ((val >> 0) & 0xfff) + 1;
>  
> -	val = I915_READ(DSPSTRIDE(pipe));
> +	val = I915_READ(DSPSTRIDE(plane_id));
>  	fb->pitches[0] = val & 0xffffffc0;
>  
>  	aligned_height = intel_fb_align_height(fb, 0, fb->height);
>  
>  	plane_config->size = fb->pitches[0] * aligned_height;
>  
> -	DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> -		      pipe_name(pipe), plane, fb->width, fb->height,
> +	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> +		      crtc->base.name, plane->base.name, fb->width, fb->height,
>  		      fb->format->cpp[0] * 8, base, fb->pitches[0],
>  		      plane_config->size);
>  
> @@ -8482,8 +8484,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = crtc->pipe;
>  	u32 val, base, offset, stride_mult, tiling;
> -	int pipe = crtc->pipe;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
> @@ -8499,7 +8503,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	fb->dev = dev;
>  
> -	val = I915_READ(PLANE_CTL(pipe, 0));
> +	val = I915_READ(PLANE_CTL(pipe, plane_id));
>  	if (!(val & PLANE_CTL_ENABLE))
>  		goto error;
>  
> @@ -8535,16 +8539,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  		goto error;
>  	}
>  
> -	base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
> +	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
>  	plane_config->base = base;
>  
> -	offset = I915_READ(PLANE_OFFSET(pipe, 0));
> +	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
>  
> -	val = I915_READ(PLANE_SIZE(pipe, 0));
> +	val = I915_READ(PLANE_SIZE(pipe, plane_id));
>  	fb->height = ((val >> 16) & 0xfff) + 1;
>  	fb->width = ((val >> 0) & 0x1fff) + 1;
>  
> -	val = I915_READ(PLANE_STRIDE(pipe, 0));
> +	val = I915_READ(PLANE_STRIDE(pipe, plane_id));
>  	stride_mult = intel_fb_stride_alignment(fb, 0);
>  	fb->pitches[0] = (val & 0x3ff) * stride_mult;
>  
> @@ -8552,8 +8556,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	plane_config->size = fb->pitches[0] * aligned_height;
>  
> -	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> -		      pipe_name(pipe), fb->width, fb->height,
> +	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> +		      crtc->base.name, plane->base.name, fb->width, fb->height,
>  		      fb->format->cpp[0] * 8, base, fb->pitches[0],
>  		      plane_config->size);
>  
> @@ -8594,14 +8598,16 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	enum old_plane_id plane_id = plane->plane;
> +	enum pipe pipe = crtc->pipe;
>  	u32 val, base, offset;
> -	int pipe = crtc->pipe;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
>  	struct intel_framebuffer *intel_fb;
>  
> -	val = I915_READ(DSPCNTR(pipe));
> +	val = I915_READ(DSPCNTR(plane_id));
>  	if (!(val & DISPLAY_PLANE_ENABLE))
>  		return;
>  
> @@ -8626,14 +8632,14 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
>  	fourcc = i9xx_format_to_fourcc(pixel_format);
>  	fb->format = drm_format_info(fourcc);
>  
> -	base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
> +	base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		offset = I915_READ(DSPOFFSET(pipe));
> +		offset = I915_READ(DSPOFFSET(plane_id));
>  	} else {
>  		if (plane_config->tiling)
> -			offset = I915_READ(DSPTILEOFF(pipe));
> +			offset = I915_READ(DSPTILEOFF(plane_id));
>  		else
> -			offset = I915_READ(DSPLINOFF(pipe));
> +			offset = I915_READ(DSPLINOFF(plane_id));
>  	}
>  	plane_config->base = base;
>  
> @@ -8641,15 +8647,15 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
>  	fb->width = ((val >> 16) & 0xfff) + 1;
>  	fb->height = ((val >> 0) & 0xfff) + 1;
>  
> -	val = I915_READ(DSPSTRIDE(pipe));
> +	val = I915_READ(DSPSTRIDE(plane_id));
>  	fb->pitches[0] = val & 0xffffffc0;
>  
>  	aligned_height = intel_fb_align_height(fb, 0, fb->height);
>  
>  	plane_config->size = fb->pitches[0] * aligned_height;
>  
> -	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> -		      pipe_name(pipe), fb->width, fb->height,
> +	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> +		      crtc->base.name, plane->base.name, fb->width, fb->height,
>  		      fb->format->cpp[0] * 8, base, fb->pitches[0],
>  		      plane_config->size);
>  
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 6/9] drm/i915: Nuke ironlake_get_initial_plane_config()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The only relevant difference between i9xx_get_initial_plane_config() and
ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling.
Add that to i9xx_get_initial_plane_config() and nuke
ironlake_get_initial_plane_config().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 79 +++---------------------------------
 1 file changed, 6 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 21160a06ab36..82be2342d1c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7490,7 +7490,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	fourcc = i9xx_format_to_fourcc(pixel_format);
 	fb->format = drm_format_info(fourcc);
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+		offset = I915_READ(DSPOFFSET(plane_id));
+		base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
+	} else if (INTEL_GEN(dev_priv) >= 4) {
 		if (plane_config->tiling)
 			offset = I915_READ(DSPTILEOFF(plane_id));
 		else
@@ -8592,76 +8595,6 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
 	}
 }
 
-static void
-ironlake_get_initial_plane_config(struct intel_crtc *crtc,
-				  struct intel_initial_plane_config *plane_config)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
-	enum old_plane_id plane_id = plane->plane;
-	enum pipe pipe = crtc->pipe;
-	u32 val, base, offset;
-	int fourcc, pixel_format;
-	unsigned int aligned_height;
-	struct drm_framebuffer *fb;
-	struct intel_framebuffer *intel_fb;
-
-	val = I915_READ(DSPCNTR(plane_id));
-	if (!(val & DISPLAY_PLANE_ENABLE))
-		return;
-
-	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
-	if (!intel_fb) {
-		DRM_DEBUG_KMS("failed to alloc fb\n");
-		return;
-	}
-
-	fb = &intel_fb->base;
-
-	fb->dev = dev;
-
-	if (INTEL_GEN(dev_priv) >= 4) {
-		if (val & DISPPLANE_TILED) {
-			plane_config->tiling = I915_TILING_X;
-			fb->modifier = I915_FORMAT_MOD_X_TILED;
-		}
-	}
-
-	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
-	fourcc = i9xx_format_to_fourcc(pixel_format);
-	fb->format = drm_format_info(fourcc);
-
-	base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		offset = I915_READ(DSPOFFSET(plane_id));
-	} else {
-		if (plane_config->tiling)
-			offset = I915_READ(DSPTILEOFF(plane_id));
-		else
-			offset = I915_READ(DSPLINOFF(plane_id));
-	}
-	plane_config->base = base;
-
-	val = I915_READ(PIPESRC(pipe));
-	fb->width = ((val >> 16) & 0xfff) + 1;
-	fb->height = ((val >> 0) & 0xfff) + 1;
-
-	val = I915_READ(DSPSTRIDE(plane_id));
-	fb->pitches[0] = val & 0xffffffc0;
-
-	aligned_height = intel_fb_align_height(fb, 0, fb->height);
-
-	plane_config->size = fb->pitches[0] * aligned_height;
-
-	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
-		      crtc->base.name, plane->base.name, fb->width, fb->height,
-		      fb->format->cpp[0] * 8, base, fb->pitches[0],
-		      plane_config->size);
-
-	plane_config->fb = intel_fb;
-}
-
 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 				     struct intel_crtc_state *pipe_config)
 {
@@ -14140,7 +14073,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 	} else if (HAS_DDI(dev_priv)) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
-			ironlake_get_initial_plane_config;
+			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
@@ -14148,7 +14081,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
-			ironlake_get_initial_plane_config;
+			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			ironlake_crtc_compute_clock;
 		dev_priv->display.crtc_enable = ironlake_crtc_enable;
-- 
2.13.6

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Re: [PATCH 6/9] drm/i915: Nuke ironlake_get_initial_plane_config()

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:52PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The only relevant difference between i9xx_get_initial_plane_config() and
> ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling.
> Add that to i9xx_get_initial_plane_config() and nuke
> ironlake_get_initial_plane_config().
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I'm still kinda wanting some way to test this here with every modeset, but
still can't come up with something simple&neat.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 79 +++---------------------------------
>  1 file changed, 6 insertions(+), 73 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 21160a06ab36..82be2342d1c6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7490,7 +7490,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  	fourcc = i9xx_format_to_fourcc(pixel_format);
>  	fb->format = drm_format_info(fourcc);
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> +		offset = I915_READ(DSPOFFSET(plane_id));
> +		base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
> +	} else if (INTEL_GEN(dev_priv) >= 4) {
>  		if (plane_config->tiling)
>  			offset = I915_READ(DSPTILEOFF(plane_id));
>  		else
> @@ -8592,76 +8595,6 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
>  	}
>  }
>  
> -static void
> -ironlake_get_initial_plane_config(struct intel_crtc *crtc,
> -				  struct intel_initial_plane_config *plane_config)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> -	enum old_plane_id plane_id = plane->plane;
> -	enum pipe pipe = crtc->pipe;
> -	u32 val, base, offset;
> -	int fourcc, pixel_format;
> -	unsigned int aligned_height;
> -	struct drm_framebuffer *fb;
> -	struct intel_framebuffer *intel_fb;
> -
> -	val = I915_READ(DSPCNTR(plane_id));
> -	if (!(val & DISPLAY_PLANE_ENABLE))

Hm, should we use plane->get_hw_state to take out this check? At least to
partially get close to the hw state readout approach we have for
crtc/encoders/connectors.

Aside form these two notes, patch itself looks good.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> -		return;
> -
> -	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
> -	if (!intel_fb) {
> -		DRM_DEBUG_KMS("failed to alloc fb\n");
> -		return;
> -	}
> -
> -	fb = &intel_fb->base;
> -
> -	fb->dev = dev;
> -
> -	if (INTEL_GEN(dev_priv) >= 4) {
> -		if (val & DISPPLANE_TILED) {
> -			plane_config->tiling = I915_TILING_X;
> -			fb->modifier = I915_FORMAT_MOD_X_TILED;
> -		}
> -	}
> -
> -	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
> -	fourcc = i9xx_format_to_fourcc(pixel_format);
> -	fb->format = drm_format_info(fourcc);
> -
> -	base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		offset = I915_READ(DSPOFFSET(plane_id));
> -	} else {
> -		if (plane_config->tiling)
> -			offset = I915_READ(DSPTILEOFF(plane_id));
> -		else
> -			offset = I915_READ(DSPLINOFF(plane_id));
> -	}
> -	plane_config->base = base;
> -
> -	val = I915_READ(PIPESRC(pipe));
> -	fb->width = ((val >> 16) & 0xfff) + 1;
> -	fb->height = ((val >> 0) & 0xfff) + 1;
> -
> -	val = I915_READ(DSPSTRIDE(plane_id));
> -	fb->pitches[0] = val & 0xffffffc0;
> -
> -	aligned_height = intel_fb_align_height(fb, 0, fb->height);
> -
> -	plane_config->size = fb->pitches[0] * aligned_height;
> -
> -	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> -		      crtc->base.name, plane->base.name, fb->width, fb->height,
> -		      fb->format->cpp[0] * 8, base, fb->pitches[0],
> -		      plane_config->size);
> -
> -	plane_config->fb = intel_fb;
> -}
> -
>  static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  				     struct intel_crtc_state *pipe_config)
>  {
> @@ -14140,7 +14073,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  	} else if (HAS_DDI(dev_priv)) {
>  		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
> -			ironlake_get_initial_plane_config;
> +			i9xx_get_initial_plane_config;
>  		dev_priv->display.crtc_compute_clock =
>  			haswell_crtc_compute_clock;
>  		dev_priv->display.crtc_enable = haswell_crtc_enable;
> @@ -14148,7 +14081,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
> -			ironlake_get_initial_plane_config;
> +			i9xx_get_initial_plane_config;
>  		dev_priv->display.crtc_compute_clock =
>  			ironlake_crtc_compute_clock;
>  		dev_priv->display.crtc_enable = ironlake_crtc_enable;
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 6/9] drm/i915: Nuke ironlake_get_initial_plane_config()

[Ville Syrjälä]

On Thu, Oct 12, 2017 at 09:17:40PM +0200, Daniel Vetter wrote:
> On Wed, Oct 11, 2017 at 07:04:52PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The only relevant difference between i9xx_get_initial_plane_config() and
> > ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling.
> > Add that to i9xx_get_initial_plane_config() and nuke
> > ironlake_get_initial_plane_config().
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I'm still kinda wanting some way to test this here with every modeset, but
> still can't come up with something simple&neat.
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 79 +++---------------------------------
> >  1 file changed, 6 insertions(+), 73 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 21160a06ab36..82be2342d1c6 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -7490,7 +7490,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> >  	fourcc = i9xx_format_to_fourcc(pixel_format);
> >  	fb->format = drm_format_info(fourcc);
> >  
> > -	if (INTEL_GEN(dev_priv) >= 4) {
> > +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > +		offset = I915_READ(DSPOFFSET(plane_id));
> > +		base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
> > +	} else if (INTEL_GEN(dev_priv) >= 4) {
> >  		if (plane_config->tiling)
> >  			offset = I915_READ(DSPTILEOFF(plane_id));
> >  		else
> > @@ -8592,76 +8595,6 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
> >  	}
> >  }
> >  
> > -static void
> > -ironlake_get_initial_plane_config(struct intel_crtc *crtc,
> > -				  struct intel_initial_plane_config *plane_config)
> > -{
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> > -	enum old_plane_id plane_id = plane->plane;
> > -	enum pipe pipe = crtc->pipe;
> > -	u32 val, base, offset;
> > -	int fourcc, pixel_format;
> > -	unsigned int aligned_height;
> > -	struct drm_framebuffer *fb;
> > -	struct intel_framebuffer *intel_fb;
> > -
> > -	val = I915_READ(DSPCNTR(plane_id));
> > -	if (!(val & DISPLAY_PLANE_ENABLE))
> 
> Hm, should we use plane->get_hw_state to take out this check? At least to
> partially get close to the hw state readout approach we have for
> crtc/encoders/connectors.

I guess we could. We'll still need to read DSPCNTR anyway, but I don't
think reading it twice is a real issue. I'll post a follow up with this.

> 
> Aside form these two notes, patch itself looks good.
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> > -		return;
> > -
> > -	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
> > -	if (!intel_fb) {
> > -		DRM_DEBUG_KMS("failed to alloc fb\n");
> > -		return;
> > -	}
> > -
> > -	fb = &intel_fb->base;
> > -
> > -	fb->dev = dev;
> > -
> > -	if (INTEL_GEN(dev_priv) >= 4) {
> > -		if (val & DISPPLANE_TILED) {
> > -			plane_config->tiling = I915_TILING_X;
> > -			fb->modifier = I915_FORMAT_MOD_X_TILED;
> > -		}
> > -	}
> > -
> > -	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
> > -	fourcc = i9xx_format_to_fourcc(pixel_format);
> > -	fb->format = drm_format_info(fourcc);
> > -
> > -	base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
> > -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > -		offset = I915_READ(DSPOFFSET(plane_id));
> > -	} else {
> > -		if (plane_config->tiling)
> > -			offset = I915_READ(DSPTILEOFF(plane_id));
> > -		else
> > -			offset = I915_READ(DSPLINOFF(plane_id));
> > -	}
> > -	plane_config->base = base;
> > -
> > -	val = I915_READ(PIPESRC(pipe));
> > -	fb->width = ((val >> 16) & 0xfff) + 1;
> > -	fb->height = ((val >> 0) & 0xfff) + 1;
> > -
> > -	val = I915_READ(DSPSTRIDE(plane_id));
> > -	fb->pitches[0] = val & 0xffffffc0;
> > -
> > -	aligned_height = intel_fb_align_height(fb, 0, fb->height);
> > -
> > -	plane_config->size = fb->pitches[0] * aligned_height;
> > -
> > -	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> > -		      crtc->base.name, plane->base.name, fb->width, fb->height,
> > -		      fb->format->cpp[0] * 8, base, fb->pitches[0],
> > -		      plane_config->size);
> > -
> > -	plane_config->fb = intel_fb;
> > -}
> > -
> >  static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> >  				     struct intel_crtc_state *pipe_config)
> >  {
> > @@ -14140,7 +14073,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> >  	} else if (HAS_DDI(dev_priv)) {
> >  		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
> >  		dev_priv->display.get_initial_plane_config =
> > -			ironlake_get_initial_plane_config;
> > +			i9xx_get_initial_plane_config;
> >  		dev_priv->display.crtc_compute_clock =
> >  			haswell_crtc_compute_clock;
> >  		dev_priv->display.crtc_enable = haswell_crtc_enable;
> > @@ -14148,7 +14081,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> >  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> >  		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
> >  		dev_priv->display.get_initial_plane_config =
> > -			ironlake_get_initial_plane_config;
> > +			i9xx_get_initial_plane_config;
> >  		dev_priv->display.crtc_compute_clock =
> >  			ironlake_crtc_compute_clock;
> >  		dev_priv->display.crtc_enable = ironlake_crtc_enable;
> > -- 
> > 2.13.6
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/9] drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Stop using the old for_each_intel_plane_in_state() type iteration
macro and replace it with for_each_new_intel_plane_in_state().
And similarly replace drm_atomic_get_existing_crtc_state() with
intel_atomic_get_new_crtc_state(). Switch over to intel_ types
as well to make the code less cluttered.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  7 +++----
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 drivers/gpu/drm/i915/intel_fbc.c     | 23 ++++++++++-------------
 4 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index df120a38ae42..9c4735da2169 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -561,13 +561,13 @@ struct i915_hotplug {
 	for_each_power_well_rev(__dev_priv, __power_well)		        \
 		for_each_if ((__power_well)->domains & (__domain_mask))
 
-#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
+#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 	for ((__i) = 0; \
 	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
-		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
+		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 	     (__i)++) \
-		for_each_if (plane_state)
+		for_each_if (plane)
 
 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 	for ((__i) = 0; \
@@ -577,7 +577,6 @@ struct i915_hotplug {
 	     (__i)++) \
 		for_each_if (crtc)
 
-
 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 	for ((__i) = 0; \
 	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 82be2342d1c6..ccdfd922fe5b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12025,7 +12025,7 @@ static int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		return ret;
 
-	intel_fbc_choose_crtc(dev_priv, state);
+	intel_fbc_choose_crtc(dev_priv, intel_state);
 	return calc_watermark_data(state);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 08318260453b..0852b33712b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1645,7 +1645,7 @@ static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 
 /* intel_fbc.c */
 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
-			   struct drm_atomic_state *state);
+			   struct intel_atomic_state *state);
 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
 void intel_fbc_pre_update(struct intel_crtc *crtc,
 			  struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 8e3a05505f49..0b40b89f8e2b 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1051,11 +1051,11 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
  */
 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
-			   struct drm_atomic_state *state)
+			   struct intel_atomic_state *state)
 {
 	struct intel_fbc *fbc = &dev_priv->fbc;
-	struct drm_plane *plane;
-	struct drm_plane_state *plane_state;
+	struct intel_plane *plane;
+	struct intel_plane_state *plane_state;
 	bool crtc_chosen = false;
 	int i;
 
@@ -1063,7 +1063,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 
 	/* Does this atomic commit involve the CRTC currently tied to FBC? */
 	if (fbc->crtc &&
-	    !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
+	    !intel_atomic_get_new_crtc_state(state, fbc->crtc))
 		goto out;
 
 	if (!intel_fbc_can_enable(dev_priv))
@@ -1073,13 +1073,11 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 	 * plane. We could go for fancier schemes such as checking the plane
 	 * size, but this would just affect the few platforms that don't tie FBC
 	 * to pipe or plane A. */
-	for_each_new_plane_in_state(state, plane, plane_state, i) {
-		struct intel_plane_state *intel_plane_state =
-			to_intel_plane_state(plane_state);
-		struct intel_crtc_state *intel_crtc_state;
-		struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		struct intel_crtc_state *crtc_state;
+		struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
 
-		if (!intel_plane_state->base.visible)
+		if (!plane_state->base.visible)
 			continue;
 
 		if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
@@ -1088,10 +1086,9 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
 			continue;
 
-		intel_crtc_state = to_intel_crtc_state(
-			drm_atomic_get_existing_crtc_state(state, &crtc->base));
+		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 
-		intel_crtc_state->enable_fbc = true;
+		crtc_state->enable_fbc = true;
 		crtc_chosen = true;
 		break;
 	}
-- 
2.13.6

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Re: [PATCH 7/9] drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:53PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Stop using the old for_each_intel_plane_in_state() type iteration
> macro and replace it with for_each_new_intel_plane_in_state().
> And similarly replace drm_atomic_get_existing_crtc_state() with
> intel_atomic_get_new_crtc_state(). Switch over to intel_ types
> as well to make the code less cluttered.
> 
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  7 +++----
>  drivers/gpu/drm/i915/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/intel_drv.h     |  2 +-
>  drivers/gpu/drm/i915/intel_fbc.c     | 23 ++++++++++-------------
>  4 files changed, 15 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index df120a38ae42..9c4735da2169 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -561,13 +561,13 @@ struct i915_hotplug {
>  	for_each_power_well_rev(__dev_priv, __power_well)		        \
>  		for_each_if ((__power_well)->domains & (__domain_mask))
>  
> -#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
> +#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
>  	for ((__i) = 0; \
>  	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
>  		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
> -		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
> +		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
>  	     (__i)++) \
> -		for_each_if (plane_state)
> +		for_each_if (plane)
>  
>  #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
>  	for ((__i) = 0; \
> @@ -577,7 +577,6 @@ struct i915_hotplug {
>  	     (__i)++) \
>  		for_each_if (crtc)

Would be nice to co-evolve our versions of these along the lines of

commit 331494eb51002d0ee99414e3918e06d5e9a3962d
Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Date:   Wed Sep 27 10:35:32 2017 +0200

    drm/atomic: Make atomic iterators less surprising

On the patch itself:

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

>  
> -
>  #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
>  	for ((__i) = 0; \
>  	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 82be2342d1c6..ccdfd922fe5b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12025,7 +12025,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  	if (ret)
>  		return ret;
>  
> -	intel_fbc_choose_crtc(dev_priv, state);
> +	intel_fbc_choose_crtc(dev_priv, intel_state);
>  	return calc_watermark_data(state);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 08318260453b..0852b33712b1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1645,7 +1645,7 @@ static inline void intel_fbdev_restore_mode(struct drm_device *dev)
>  
>  /* intel_fbc.c */
>  void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> -			   struct drm_atomic_state *state);
> +			   struct intel_atomic_state *state);
>  bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
>  void intel_fbc_pre_update(struct intel_crtc *crtc,
>  			  struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 8e3a05505f49..0b40b89f8e2b 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -1051,11 +1051,11 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
>   * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
>   */
>  void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> -			   struct drm_atomic_state *state)
> +			   struct intel_atomic_state *state)
>  {
>  	struct intel_fbc *fbc = &dev_priv->fbc;
> -	struct drm_plane *plane;
> -	struct drm_plane_state *plane_state;
> +	struct intel_plane *plane;
> +	struct intel_plane_state *plane_state;
>  	bool crtc_chosen = false;
>  	int i;
>  
> @@ -1063,7 +1063,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
>  
>  	/* Does this atomic commit involve the CRTC currently tied to FBC? */
>  	if (fbc->crtc &&
> -	    !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
> +	    !intel_atomic_get_new_crtc_state(state, fbc->crtc))
>  		goto out;
>  
>  	if (!intel_fbc_can_enable(dev_priv))
> @@ -1073,13 +1073,11 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
>  	 * plane. We could go for fancier schemes such as checking the plane
>  	 * size, but this would just affect the few platforms that don't tie FBC
>  	 * to pipe or plane A. */
> -	for_each_new_plane_in_state(state, plane, plane_state, i) {
> -		struct intel_plane_state *intel_plane_state =
> -			to_intel_plane_state(plane_state);
> -		struct intel_crtc_state *intel_crtc_state;
> -		struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		struct intel_crtc_state *crtc_state;
> +		struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
>  
> -		if (!intel_plane_state->base.visible)
> +		if (!plane_state->base.visible)
>  			continue;
>  
>  		if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
> @@ -1088,10 +1086,9 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
>  		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
>  			continue;
>  
> -		intel_crtc_state = to_intel_crtc_state(
> -			drm_atomic_get_existing_crtc_state(state, &crtc->base));
> +		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>  
> -		intel_crtc_state->enable_fbc = true;
> +		crtc_state->enable_fbc = true;
>  		crtc_chosen = true;
>  		break;
>  	}
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 7/9] drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()

[Ville Syrjälä]

On Thu, Oct 12, 2017 at 09:21:07PM +0200, Daniel Vetter wrote:
> On Wed, Oct 11, 2017 at 07:04:53PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Stop using the old for_each_intel_plane_in_state() type iteration
> > macro and replace it with for_each_new_intel_plane_in_state().
> > And similarly replace drm_atomic_get_existing_crtc_state() with
> > intel_atomic_get_new_crtc_state(). Switch over to intel_ types
> > as well to make the code less cluttered.
> > 
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  7 +++----
> >  drivers/gpu/drm/i915/intel_display.c |  2 +-
> >  drivers/gpu/drm/i915/intel_drv.h     |  2 +-
> >  drivers/gpu/drm/i915/intel_fbc.c     | 23 ++++++++++-------------
> >  4 files changed, 15 insertions(+), 19 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index df120a38ae42..9c4735da2169 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -561,13 +561,13 @@ struct i915_hotplug {
> >  	for_each_power_well_rev(__dev_priv, __power_well)		        \
> >  		for_each_if ((__power_well)->domains & (__domain_mask))
> >  
> > -#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
> > +#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
> >  	for ((__i) = 0; \
> >  	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
> >  		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
> > -		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
> > +		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
> >  	     (__i)++) \
> > -		for_each_if (plane_state)
> > +		for_each_if (plane)
> >  
> >  #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
> >  	for ((__i) = 0; \
> > @@ -577,7 +577,6 @@ struct i915_hotplug {
> >  	     (__i)++) \
> >  		for_each_if (crtc)
> 
> Would be nice to co-evolve our versions of these along the lines of
> 
> commit 331494eb51002d0ee99414e3918e06d5e9a3962d
> Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Date:   Wed Sep 27 10:35:32 2017 +0200
> 
>     drm/atomic: Make atomic iterators less surprising

Indeed. The same idea popped into my head when I saw Maarten's patch,
but apparently I forgot to reply to the patch to propose it.

> 
> On the patch itself:
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> >  
> > -
> >  #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
> >  	for ((__i) = 0; \
> >  	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 82be2342d1c6..ccdfd922fe5b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12025,7 +12025,7 @@ static int intel_atomic_check(struct drm_device *dev,
> >  	if (ret)
> >  		return ret;
> >  
> > -	intel_fbc_choose_crtc(dev_priv, state);
> > +	intel_fbc_choose_crtc(dev_priv, intel_state);
> >  	return calc_watermark_data(state);
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 08318260453b..0852b33712b1 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1645,7 +1645,7 @@ static inline void intel_fbdev_restore_mode(struct drm_device *dev)
> >  
> >  /* intel_fbc.c */
> >  void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> > -			   struct drm_atomic_state *state);
> > +			   struct intel_atomic_state *state);
> >  bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
> >  void intel_fbc_pre_update(struct intel_crtc *crtc,
> >  			  struct intel_crtc_state *crtc_state,
> > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > index 8e3a05505f49..0b40b89f8e2b 100644
> > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > @@ -1051,11 +1051,11 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
> >   * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
> >   */
> >  void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> > -			   struct drm_atomic_state *state)
> > +			   struct intel_atomic_state *state)
> >  {
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > -	struct drm_plane *plane;
> > -	struct drm_plane_state *plane_state;
> > +	struct intel_plane *plane;
> > +	struct intel_plane_state *plane_state;
> >  	bool crtc_chosen = false;
> >  	int i;
> >  
> > @@ -1063,7 +1063,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> >  
> >  	/* Does this atomic commit involve the CRTC currently tied to FBC? */
> >  	if (fbc->crtc &&
> > -	    !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
> > +	    !intel_atomic_get_new_crtc_state(state, fbc->crtc))
> >  		goto out;
> >  
> >  	if (!intel_fbc_can_enable(dev_priv))
> > @@ -1073,13 +1073,11 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> >  	 * plane. We could go for fancier schemes such as checking the plane
> >  	 * size, but this would just affect the few platforms that don't tie FBC
> >  	 * to pipe or plane A. */
> > -	for_each_new_plane_in_state(state, plane, plane_state, i) {
> > -		struct intel_plane_state *intel_plane_state =
> > -			to_intel_plane_state(plane_state);
> > -		struct intel_crtc_state *intel_crtc_state;
> > -		struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
> > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > +		struct intel_crtc_state *crtc_state;
> > +		struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
> >  
> > -		if (!intel_plane_state->base.visible)
> > +		if (!plane_state->base.visible)
> >  			continue;
> >  
> >  		if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
> > @@ -1088,10 +1086,9 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> >  		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
> >  			continue;
> >  
> > -		intel_crtc_state = to_intel_crtc_state(
> > -			drm_atomic_get_existing_crtc_state(state, &crtc->base));
> > +		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> >  
> > -		intel_crtc_state->enable_fbc = true;
> > +		crtc_state->enable_fbc = true;
> >  		crtc_chosen = true;
> >  		break;
> >  	}
> > -- 
> > 2.13.6
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 8/9] drm/i915: Nuke crtc->plane

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Eliminate crtc->plane since it's pretty much a layering violation.
We can always get the plane via crtc->primary if we actually need it.

The only ugly thing left is plane_to_crtc_mapping[], but that's
still needed by the pre-g4x watermark code.

Also revise the comment about emum old_plane_id to make it clear
one should not use it for SKL+ ever.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      | 2 +-
 drivers/gpu/drm/i915/intel_display.c | 5 ++---
 drivers/gpu/drm/i915/intel_drv.h     | 1 -
 drivers/gpu/drm/i915/intel_fbc.c     | 4 ++--
 4 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9c4735da2169..0b97860ba39c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -305,7 +305,7 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
 
 /*
  * Global legacy plane identifier. Valid only for primary/sprite
- * planes on pre-g4x, and only for primary planes on g4x+.
+ * planes on pre-g4x, and only for primary planes on g4x-bdw.
  */
 enum old_plane_id {
 	PLANE_A,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ccdfd922fe5b..622b487629d7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13386,14 +13386,13 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 		goto fail;
 
 	intel_crtc->pipe = pipe;
-	intel_crtc->plane = primary->plane;
 
 	/* initialize shared scalers */
 	intel_crtc_init_scalers(intel_crtc, crtc_state);
 
 	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
-	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
-	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
+	       dev_priv->plane_to_crtc_mapping[primary->plane] != NULL);
+	dev_priv->plane_to_crtc_mapping[primary->plane] = intel_crtc;
 	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
 
 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0852b33712b1..8396d4de9299 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -793,7 +793,6 @@ struct intel_crtc_state {
 struct intel_crtc {
 	struct drm_crtc base;
 	enum pipe pipe;
-	enum old_plane_id plane;
 	/*
 	 * Whether the crtc and the connected output pipeline is active. Implies
 	 * that crtc->enabled is set, i.e. the current mode configuration has
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 0b40b89f8e2b..567f10380a0f 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -887,7 +887,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 	params->vma = cache->vma;
 
 	params->crtc.pipe = crtc->pipe;
-	params->crtc.plane = crtc->plane;
+	params->crtc.plane = to_intel_plane(crtc->base.primary)->plane;
 	params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 
 	params->fb.format = cache->fb.format;
@@ -1083,7 +1083,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 		if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
 			continue;
 
-		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
+		if (fbc_on_plane_a_only(dev_priv) && plane->plane != PLANE_A)
 			continue;
 
 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-- 
2.13.6

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Re: [PATCH 8/9] drm/i915: Nuke crtc->plane

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:54PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Eliminate crtc->plane since it's pretty much a layering violation.
> We can always get the plane via crtc->primary if we actually need it.
> 
> The only ugly thing left is plane_to_crtc_mapping[], but that's
> still needed by the pre-g4x watermark code.
> 
> Also revise the comment about emum old_plane_id to make it clear
> one should not use it for SKL+ ever.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 2 +-
>  drivers/gpu/drm/i915/intel_display.c | 5 ++---
>  drivers/gpu/drm/i915/intel_drv.h     | 1 -
>  drivers/gpu/drm/i915/intel_fbc.c     | 4 ++--
>  4 files changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9c4735da2169..0b97860ba39c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -305,7 +305,7 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
>  
>  /*
>   * Global legacy plane identifier. Valid only for primary/sprite
> - * planes on pre-g4x, and only for primary planes on g4x+.
> + * planes on pre-g4x, and only for primary planes on g4x-bdw.
>   */

Hm, should be moved into the patch that introduces old_plane_id?

Anyway, with or without that hunk moved.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

>  enum old_plane_id {
>  	PLANE_A,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ccdfd922fe5b..622b487629d7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13386,14 +13386,13 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		goto fail;
>  
>  	intel_crtc->pipe = pipe;
> -	intel_crtc->plane = primary->plane;
>  
>  	/* initialize shared scalers */
>  	intel_crtc_init_scalers(intel_crtc, crtc_state);
>  
>  	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
> -	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
> -	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
> +	       dev_priv->plane_to_crtc_mapping[primary->plane] != NULL);
> +	dev_priv->plane_to_crtc_mapping[primary->plane] = intel_crtc;
>  	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
>  
>  	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 0852b33712b1..8396d4de9299 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -793,7 +793,6 @@ struct intel_crtc_state {
>  struct intel_crtc {
>  	struct drm_crtc base;
>  	enum pipe pipe;
> -	enum old_plane_id plane;
>  	/*
>  	 * Whether the crtc and the connected output pipeline is active. Implies
>  	 * that crtc->enabled is set, i.e. the current mode configuration has
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 0b40b89f8e2b..567f10380a0f 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -887,7 +887,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
>  	params->vma = cache->vma;
>  
>  	params->crtc.pipe = crtc->pipe;
> -	params->crtc.plane = crtc->plane;
> +	params->crtc.plane = to_intel_plane(crtc->base.primary)->plane;
>  	params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
>  
>  	params->fb.format = cache->fb.format;
> @@ -1083,7 +1083,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
>  		if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
>  			continue;
>  
> -		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
> +		if (fbc_on_plane_a_only(dev_priv) && plane->plane != PLANE_A)
>  			continue;
>  
>  		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Re: [PATCH 8/9] drm/i915: Nuke crtc->plane

[Ville Syrjälä]

On Thu, Oct 12, 2017 at 09:38:20PM +0200, Daniel Vetter wrote:
> On Wed, Oct 11, 2017 at 07:04:54PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Eliminate crtc->plane since it's pretty much a layering violation.
> > We can always get the plane via crtc->primary if we actually need it.
> > 
> > The only ugly thing left is plane_to_crtc_mapping[], but that's
> > still needed by the pre-g4x watermark code.
> > 
> > Also revise the comment about emum old_plane_id to make it clear
> > one should not use it for SKL+ ever.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      | 2 +-
> >  drivers/gpu/drm/i915/intel_display.c | 5 ++---
> >  drivers/gpu/drm/i915/intel_drv.h     | 1 -
> >  drivers/gpu/drm/i915/intel_fbc.c     | 4 ++--
> >  4 files changed, 5 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 9c4735da2169..0b97860ba39c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -305,7 +305,7 @@ static inline bool transcoder_is_dsi(enum transcoder transcoder)
> >  
> >  /*
> >   * Global legacy plane identifier. Valid only for primary/sprite
> > - * planes on pre-g4x, and only for primary planes on g4x+.
> > + * planes on pre-g4x, and only for primary planes on g4x-bdw.
> >   */
> 
> Hm, should be moved into the patch that introduces old_plane_id?

Hmm. Not sure thy this eneded up here. It was supposed to be either in
the patch that adds old_plane_id, or the one that nukes the old
primary_get_hw_state() functioon (since that one was still using DSPCNTR
even on SKL+). I can't recall which patch ended up being earlier in the
series, but I'll take another look and move this.

> 
> Anyway, with or without that hunk moved.
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> >  enum old_plane_id {
> >  	PLANE_A,
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ccdfd922fe5b..622b487629d7 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13386,14 +13386,13 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  		goto fail;
> >  
> >  	intel_crtc->pipe = pipe;
> > -	intel_crtc->plane = primary->plane;
> >  
> >  	/* initialize shared scalers */
> >  	intel_crtc_init_scalers(intel_crtc, crtc_state);
> >  
> >  	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
> > -	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
> > -	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
> > +	       dev_priv->plane_to_crtc_mapping[primary->plane] != NULL);
> > +	dev_priv->plane_to_crtc_mapping[primary->plane] = intel_crtc;
> >  	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
> >  
> >  	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 0852b33712b1..8396d4de9299 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -793,7 +793,6 @@ struct intel_crtc_state {
> >  struct intel_crtc {
> >  	struct drm_crtc base;
> >  	enum pipe pipe;
> > -	enum old_plane_id plane;
> >  	/*
> >  	 * Whether the crtc and the connected output pipeline is active. Implies
> >  	 * that crtc->enabled is set, i.e. the current mode configuration has
> > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > index 0b40b89f8e2b..567f10380a0f 100644
> > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > @@ -887,7 +887,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
> >  	params->vma = cache->vma;
> >  
> >  	params->crtc.pipe = crtc->pipe;
> > -	params->crtc.plane = crtc->plane;
> > +	params->crtc.plane = to_intel_plane(crtc->base.primary)->plane;
> >  	params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
> >  
> >  	params->fb.format = cache->fb.format;
> > @@ -1083,7 +1083,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> >  		if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
> >  			continue;
> >  
> > -		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
> > +		if (fbc_on_plane_a_only(dev_priv) && plane->plane != PLANE_A)
> >  			continue;
> >  
> >  		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > -- 
> > 2.13.6
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
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[PATCH 9/9] drm/i915: Add windowing for primary planes on gen2/3 and chv

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Plane B and C (note that we don't actually expose plane C currently)
on gen2/3 have a window generator, as does the primary plane on CHV
pipe B. So let's allow positioning of these planes freely within the
pipe source area.

Plane A on gen2/3 seems to have some kind of partial window generator
which would allow you to cut the plane off midway through the scanout,
but it would still have to start at the top-left corner of the pipe,
and it would have to be full width. That's doesn't sound all that
useful, so for simplicity let's just keep to the idea that plane A
has to be fullscreen.

Gen4 removed the plane A/B windowing support entirely, and it wasn't
reintroduced until SKL (apart from the CHV pipe B special case).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 622b487629d7..595b46255dd2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3236,6 +3236,10 @@ static void i9xx_update_plane(struct intel_plane *plane,
 	i915_reg_t reg = DSPCNTR(plane_id);
 	int x = plane_state->main.x;
 	int y = plane_state->main.y;
+	int crtc_x = plane_state->base.dst.x1;
+	int crtc_y = plane_state->base.dst.y1;
+	int crtc_w = drm_rect_width(&plane_state->base.dst);
+	int crtc_h = drm_rect_height(&plane_state->base.dst);
 	unsigned long irqflags;
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
@@ -3251,18 +3255,18 @@ static void i9xx_update_plane(struct intel_plane *plane,
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	if (INTEL_GEN(dev_priv) < 4) {
-		/* pipesrc and dspsize control the size that is scaled from,
-		 * which should always be the user's requested size.
+		/*
+		 * PLANE_A doesn't actually have a full window
+		 * generator but let's assume we still need to
+		 * program whatever is there.
 		 */
+		I915_WRITE_FW(DSPPOS(plane_id), (crtc_y << 16) | crtc_x);
 		I915_WRITE_FW(DSPSIZE(plane_id),
-			      ((crtc_state->pipe_src_h - 1) << 16) |
-			      (crtc_state->pipe_src_w - 1));
-		I915_WRITE_FW(DSPPOS(plane_id), 0);
+			      ((crtc_h - 1) << 16) | (crtc_w - 1));
 	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
+		I915_WRITE_FW(PRIMPOS(plane_id), (crtc_y << 16) | crtc_x);
 		I915_WRITE_FW(PRIMSIZE(plane_id),
-			      ((crtc_state->pipe_src_h - 1) << 16) |
-			      (crtc_state->pipe_src_w - 1));
-		I915_WRITE_FW(PRIMPOS(plane_id), 0);
+			      ((crtc_h - 1) << 16) | (crtc_w - 1));
 		I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
 	}
 
@@ -12737,6 +12741,15 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	return max_scale;
 }
 
+static bool intel_primary_plane_has_windowing(struct intel_plane *plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+	return INTEL_GEN(dev_priv) >= 9 ||
+		(IS_CHERRYVIEW(dev_priv) && plane->plane == PLANE_B) ||
+		(INTEL_GEN(dev_priv) < 4 && plane->plane != PLANE_A);
+}
+
 static int
 intel_check_primary_plane(struct intel_plane *plane,
 			  struct intel_crtc_state *crtc_state,
@@ -12746,16 +12759,14 @@ intel_check_primary_plane(struct intel_plane *plane,
 	struct drm_crtc *crtc = state->base.crtc;
 	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
 	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
-	bool can_position = false;
+	bool can_position = intel_primary_plane_has_windowing(plane);
 	int ret;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
-		/* use scaler when colorkey is not required */
-		if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
-			min_scale = 1;
-			max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
-		}
-		can_position = true;
+	/* use scaler when colorkey is not required */
+	if (INTEL_GEN(dev_priv) >= 9 &&
+	    state->ckey.flags == I915_SET_COLORKEY_NONE) {
+		min_scale = 1;
+		max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
 	}
 
 	ret = drm_plane_helper_check_state(&state->base,
-- 
2.13.6

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Re: [PATCH 9/9] drm/i915: Add windowing for primary planes on gen2/3 and chv

[Daniel Vetter]

On Wed, Oct 11, 2017 at 07:04:55PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Plane B and C (note that we don't actually expose plane C currently)
> on gen2/3 have a window generator, as does the primary plane on CHV
> pipe B. So let's allow positioning of these planes freely within the
> pipe source area.
> 
> Plane A on gen2/3 seems to have some kind of partial window generator
> which would allow you to cut the plane off midway through the scanout,
> but it would still have to start at the top-left corner of the pipe,
> and it would have to be full width. That's doesn't sound all that
> useful, so for simplicity let's just keep to the idea that plane A
> has to be fullscreen.
> 
> Gen4 removed the plane A/B windowing support entirely, and it wasn't
> reintroduced until SKL (apart from the CHV pipe B special case).
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hm, not really liking to r-b this since I don't have a metric pile of igts
switching from skip -> pass due to this. Which is because:

- no chv or gen2/3 in our shards
- and I think still no good primary plane position testcases in igt

I'd want both before I rb this (and chv in CI shards would be kinda neat,
so perhaps start working on Jani about this).
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++++++--------------
>  1 file changed, 27 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 622b487629d7..595b46255dd2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3236,6 +3236,10 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  	i915_reg_t reg = DSPCNTR(plane_id);
>  	int x = plane_state->main.x;
>  	int y = plane_state->main.y;
> +	int crtc_x = plane_state->base.dst.x1;
> +	int crtc_y = plane_state->base.dst.y1;
> +	int crtc_w = drm_rect_width(&plane_state->base.dst);
> +	int crtc_h = drm_rect_height(&plane_state->base.dst);
>  	unsigned long irqflags;
>  
>  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> @@ -3251,18 +3255,18 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
>  	if (INTEL_GEN(dev_priv) < 4) {
> -		/* pipesrc and dspsize control the size that is scaled from,
> -		 * which should always be the user's requested size.
> +		/*
> +		 * PLANE_A doesn't actually have a full window
> +		 * generator but let's assume we still need to
> +		 * program whatever is there.
>  		 */
> +		I915_WRITE_FW(DSPPOS(plane_id), (crtc_y << 16) | crtc_x);
>  		I915_WRITE_FW(DSPSIZE(plane_id),
> -			      ((crtc_state->pipe_src_h - 1) << 16) |
> -			      (crtc_state->pipe_src_w - 1));
> -		I915_WRITE_FW(DSPPOS(plane_id), 0);
> +			      ((crtc_h - 1) << 16) | (crtc_w - 1));
>  	} else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
> +		I915_WRITE_FW(PRIMPOS(plane_id), (crtc_y << 16) | crtc_x);
>  		I915_WRITE_FW(PRIMSIZE(plane_id),
> -			      ((crtc_state->pipe_src_h - 1) << 16) |
> -			      (crtc_state->pipe_src_w - 1));
> -		I915_WRITE_FW(PRIMPOS(plane_id), 0);
> +			      ((crtc_h - 1) << 16) | (crtc_w - 1));
>  		I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
>  	}
>  
> @@ -12737,6 +12741,15 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
>  	return max_scale;
>  }
>  
> +static bool intel_primary_plane_has_windowing(struct intel_plane *plane)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> +	return INTEL_GEN(dev_priv) >= 9 ||
> +		(IS_CHERRYVIEW(dev_priv) && plane->plane == PLANE_B) ||
> +		(INTEL_GEN(dev_priv) < 4 && plane->plane != PLANE_A);
> +}
> +
>  static int
>  intel_check_primary_plane(struct intel_plane *plane,
>  			  struct intel_crtc_state *crtc_state,
> @@ -12746,16 +12759,14 @@ intel_check_primary_plane(struct intel_plane *plane,
>  	struct drm_crtc *crtc = state->base.crtc;
>  	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
>  	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
> -	bool can_position = false;
> +	bool can_position = intel_primary_plane_has_windowing(plane);
>  	int ret;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> -		/* use scaler when colorkey is not required */
> -		if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> -			min_scale = 1;
> -			max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
> -		}
> -		can_position = true;
> +	/* use scaler when colorkey is not required */
> +	if (INTEL_GEN(dev_priv) >= 9 &&
> +	    state->ckey.flags == I915_SET_COLORKEY_NONE) {
> +		min_scale = 1;
> +		max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
>  	}
>  
>  	ret = drm_plane_helper_check_state(&state->base,
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Alex Villacis Lasso]

El 11/10/17 a las 11:04, Ville Syrjala escribió:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> This series aims to clean up some of the plane state readout and
> sanitation, and clean up the enum plane mess a bit by renaming it
> to enum old_plane_id.
>
> The one actual bugfix here is the plane<->crtc sanitation
> change. Previously we tried to shut down the entire pipe when
> the plane mapping wasn't what we want, now we just shut down the
> plane, which is easier.
>
> Most of the other stuff is just polish, but I also decided to
> throw the gen2/3 and chv primary plane windowing support on on top
> just because it's been bugging me for years, and I was already
> in the neighbourhood.
>
> Series available here:
> git://github.com/vsyrjala/linux.git plane_sanitation_2
>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
>
> Ville Syrjälä (9):
>    drm/i915: Add .get_hw_state() method for planes
>    drm/i915: Redo plane sanitation during readout
>    drm/i915: s/enum plane/enum old_plane_id/
>    drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
>    drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
>      fb readout
>    drm/i915: Nuke ironlake_get_initial_plane_config()
>    drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
>    drm/i915: Nuke crtc->plane
>    drm/i915: Add windowing for primary planes on gen2/3 and chv
>
>   drivers/gpu/drm/i915/i915_drv.h      |  16 +-
>   drivers/gpu/drm/i915/intel_display.c | 500 +++++++++++++++--------------------
>   drivers/gpu/drm/i915/intel_drv.h     |   8 +-
>   drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
>   drivers/gpu/drm/i915/intel_pm.c      |  36 +--
>   drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
>   6 files changed, 299 insertions(+), 331 deletions(-)
>
Sorry if this sounds like a newbie question, but what kernel version should these two patches be applied against? Can they be applied on top of 4.13.5?

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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Ville Syrjälä]

On Wed, Oct 11, 2017 at 04:21:58PM +0000, Alex Villacis Lasso wrote:
> El 11/10/17 a las 11:04, Ville Syrjala escribió:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > This series aims to clean up some of the plane state readout and
> > sanitation, and clean up the enum plane mess a bit by renaming it
> > to enum old_plane_id.
> >
> > The one actual bugfix here is the plane<->crtc sanitation
> > change. Previously we tried to shut down the entire pipe when
> > the plane mapping wasn't what we want, now we just shut down the
> > plane, which is easier.
> >
> > Most of the other stuff is just polish, but I also decided to
> > throw the gen2/3 and chv primary plane windowing support on on top
> > just because it's been bugging me for years, and I was already
> > in the neighbourhood.
> >
> > Series available here:
> > git://github.com/vsyrjala/linux.git plane_sanitation_2
> >
> > Cc: Thierry Reding <thierry.reding@gmail.com>
> > Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
> >
> > Ville Syrjälä (9):
> >    drm/i915: Add .get_hw_state() method for planes
> >    drm/i915: Redo plane sanitation during readout
> >    drm/i915: s/enum plane/enum old_plane_id/
> >    drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
> >    drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
> >      fb readout
> >    drm/i915: Nuke ironlake_get_initial_plane_config()
> >    drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
> >    drm/i915: Nuke crtc->plane
> >    drm/i915: Add windowing for primary planes on gen2/3 and chv
> >
> >   drivers/gpu/drm/i915/i915_drv.h      |  16 +-
> >   drivers/gpu/drm/i915/intel_display.c | 500 +++++++++++++++--------------------
> >   drivers/gpu/drm/i915/intel_drv.h     |   8 +-
> >   drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
> >   drivers/gpu/drm/i915/intel_pm.c      |  36 +--
> >   drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
> >   6 files changed, 299 insertions(+), 331 deletions(-)
> >
> Sorry if this sounds like a newbie question, but what kernel version should these two patches be applied against? Can they be applied on top of 4.13.5?

Not sure they apply cleanly to something so old. In general we develop
everything on top of 'git://anongit.freedesktop.org/drm-tip drm-tip' so
that's where they would at least apply. But in that case it's actually
easier to just grab my plane_sanitation_2 branch directly since it's
sitting on top of the latest drm-tip.

Hmm. Looks like only trivial conflicts when cherry-picking the first
two patches onto 4.13.5. I pushed the result to here:
git://github.com/vsyrjala/linux.git plane_sanitation_2_v4.13
but note that I only compile tested it so it's still possible it won't
actually work.

-- 
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Intel OTC
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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Alex Villacis Lasso]

El 11/10/17 a las 11:38, Ville Syrjälä escribió:
> On Wed, Oct 11, 2017 at 04:21:58PM +0000, Alex Villacis Lasso wrote:
>> El 11/10/17 a las 11:04, Ville Syrjala escribió:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> This series aims to clean up some of the plane state readout and
>>> sanitation, and clean up the enum plane mess a bit by renaming it
>>> to enum old_plane_id.
>>>
>>> The one actual bugfix here is the plane<->crtc sanitation
>>> change. Previously we tried to shut down the entire pipe when
>>> the plane mapping wasn't what we want, now we just shut down the
>>> plane, which is easier.
>>>
>>> Most of the other stuff is just polish, but I also decided to
>>> throw the gen2/3 and chv primary plane windowing support on on top
>>> just because it's been bugging me for years, and I was already
>>> in the neighbourhood.
>>>
>>> Series available here:
>>> git://github.com/vsyrjala/linux.git plane_sanitation_2
>>>
>>> Cc: Thierry Reding <thierry.reding@gmail.com>
>>> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
>>>
>>> Ville Syrjälä (9):
>>>     drm/i915: Add .get_hw_state() method for planes
>>>     drm/i915: Redo plane sanitation during readout
>>>     drm/i915: s/enum plane/enum old_plane_id/
>>>     drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
>>>     drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
>>>       fb readout
>>>     drm/i915: Nuke ironlake_get_initial_plane_config()
>>>     drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
>>>     drm/i915: Nuke crtc->plane
>>>     drm/i915: Add windowing for primary planes on gen2/3 and chv
>>>
>>>    drivers/gpu/drm/i915/i915_drv.h      |  16 +-
>>>    drivers/gpu/drm/i915/intel_display.c | 500 +++++++++++++++--------------------
>>>    drivers/gpu/drm/i915/intel_drv.h     |   8 +-
>>>    drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
>>>    drivers/gpu/drm/i915/intel_pm.c      |  36 +--
>>>    drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
>>>    6 files changed, 299 insertions(+), 331 deletions(-)
>>>
>> Sorry if this sounds like a newbie question, but what kernel version should these two patches be applied against? Can they be applied on top of 4.13.5?
> Not sure they apply cleanly to something so old. In general we develop
> everything on top of 'git://anongit.freedesktop.org/drm-tip drm-tip' so
> that's where they would at least apply. But in that case it's actually
> easier to just grab my plane_sanitation_2 branch directly since it's
> sitting on top of the latest drm-tip.
>
> Hmm. Looks like only trivial conflicts when cherry-picking the first
> two patches onto 4.13.5. I pushed the result to here:
> git://github.com/vsyrjala/linux.git plane_sanitation_2_v4.13
> but note that I only compile tested it so it's still possible it won't
> actually work.
>

The plane_sanitation_2 branch fails to module_install on my Acer Aspire One. It complains at the DEPMOD stage that there is a circular dependency between drm and drm_kms_helper. I compiled using the configuration file from 4.13.5 and running "make 
oldconfig" prior to building. Therefore I am unable to check whether the patchset fixes the situation in my machine. What is needed to track and possibly fix this situation?


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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Alex Villacis Lasso]

El 13/10/17 a las 11:28, Alex Villacís Lasso escribió:
> El 11/10/17 a las 11:38, Ville Syrjälä escribió:
>> On Wed, Oct 11, 2017 at 04:21:58PM +0000, Alex Villacis Lasso wrote:
>>> El 11/10/17 a las 11:04, Ville Syrjala escribió:
>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>
>>>> This series aims to clean up some of the plane state readout and
>>>> sanitation, and clean up the enum plane mess a bit by renaming it
>>>> to enum old_plane_id.
>>>>
>>>> The one actual bugfix here is the plane<->crtc sanitation
>>>> change. Previously we tried to shut down the entire pipe when
>>>> the plane mapping wasn't what we want, now we just shut down the
>>>> plane, which is easier.
>>>>
>>>> Most of the other stuff is just polish, but I also decided to
>>>> throw the gen2/3 and chv primary plane windowing support on on top
>>>> just because it's been bugging me for years, and I was already
>>>> in the neighbourhood.
>>>>
>>>> Series available here:
>>>> git://github.com/vsyrjala/linux.git plane_sanitation_2
>>>>
>>>> Cc: Thierry Reding <thierry.reding@gmail.com>
>>>> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
>>>>
>>>> Ville Syrjälä (9):
>>>>     drm/i915: Add .get_hw_state() method for planes
>>>>     drm/i915: Redo plane sanitation during readout
>>>>     drm/i915: s/enum plane/enum old_plane_id/
>>>>     drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
>>>>     drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in 
>>>> initial
>>>>       fb readout
>>>>     drm/i915: Nuke ironlake_get_initial_plane_config()
>>>>     drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
>>>>     drm/i915: Nuke crtc->plane
>>>>     drm/i915: Add windowing for primary planes on gen2/3 and chv
>>>>
>>>>    drivers/gpu/drm/i915/i915_drv.h      |  16 +-
>>>>    drivers/gpu/drm/i915/intel_display.c | 500 
>>>> +++++++++++++++--------------------
>>>>    drivers/gpu/drm/i915/intel_drv.h     |   8 +-
>>>>    drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
>>>>    drivers/gpu/drm/i915/intel_pm.c      |  36 +--
>>>>    drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
>>>>    6 files changed, 299 insertions(+), 331 deletions(-)
>>>>
>>> Sorry if this sounds like a newbie question, but what kernel version 
>>> should these two patches be applied against? Can they be applied on 
>>> top of 4.13.5?
>> Not sure they apply cleanly to something so old. In general we develop
>> everything on top of 'git://anongit.freedesktop.org/drm-tip drm-tip' so
>> that's where they would at least apply. But in that case it's actually
>> easier to just grab my plane_sanitation_2 branch directly since it's
>> sitting on top of the latest drm-tip.
>>
>> Hmm. Looks like only trivial conflicts when cherry-picking the first
>> two patches onto 4.13.5. I pushed the result to here:
>> git://github.com/vsyrjala/linux.git plane_sanitation_2_v4.13
>> but note that I only compile tested it so it's still possible it won't
>> actually work.
>>
>
> The plane_sanitation_2 branch fails to module_install on my Acer 
> Aspire One. It complains at the DEPMOD stage that there is a circular 
> dependency between drm and drm_kms_helper. I compiled using the 
> configuration file from 4.13.5 and running "make oldconfig" prior to 
> building. Therefore I am unable to check whether the patchset fixes 
> the situation in my machine. What is needed to track and possibly fix 
> this situation?
>
>
More specifically:

   INSTALL sound/usb/misc/snd-ua101.ko
   INSTALL sound/usb/snd-usb-audio.ko
   INSTALL sound/usb/snd-usbmidi-lib.ko
   INSTALL sound/usb/usx2y/snd-usb-us122l.ko
   INSTALL sound/usb/usx2y/snd-usb-usx2y.ko
   INSTALL sound/x86/snd-hdmi-lpe-audio.ko
   INSTALL virt/lib/irqbypass.ko
   DEPMOD  4.14.0-rc4
depmod: ERROR: Cycle detected: drm_kms_helper -> drm -> drm_kms_helper
depmod: ERROR: Found 2 modules in dependency cycles!
make: *** [Makefile:1244: _modinst_post] Error 1

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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Jani Nikula]

On Sat, 14 Oct 2017, Alex Villacis Lasso <alexvillacislasso@hotmail.com> wrote:
> El 13/10/17 a las 11:28, Alex Villacís Lasso escribió:
>> El 11/10/17 a las 11:38, Ville Syrjälä escribió:
>>> On Wed, Oct 11, 2017 at 04:21:58PM +0000, Alex Villacis Lasso wrote:
>>>> El 11/10/17 a las 11:04, Ville Syrjala escribió:
>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>>
>>>>> This series aims to clean up some of the plane state readout and
>>>>> sanitation, and clean up the enum plane mess a bit by renaming it
>>>>> to enum old_plane_id.
>>>>>
>>>>> The one actual bugfix here is the plane<->crtc sanitation
>>>>> change. Previously we tried to shut down the entire pipe when
>>>>> the plane mapping wasn't what we want, now we just shut down the
>>>>> plane, which is easier.
>>>>>
>>>>> Most of the other stuff is just polish, but I also decided to
>>>>> throw the gen2/3 and chv primary plane windowing support on on top
>>>>> just because it's been bugging me for years, and I was already
>>>>> in the neighbourhood.
>>>>>
>>>>> Series available here:
>>>>> git://github.com/vsyrjala/linux.git plane_sanitation_2
>>>>>
>>>>> Cc: Thierry Reding <thierry.reding@gmail.com>
>>>>> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
>>>>>
>>>>> Ville Syrjälä (9):
>>>>>     drm/i915: Add .get_hw_state() method for planes
>>>>>     drm/i915: Redo plane sanitation during readout
>>>>>     drm/i915: s/enum plane/enum old_plane_id/
>>>>>     drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
>>>>>     drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in 
>>>>> initial
>>>>>       fb readout
>>>>>     drm/i915: Nuke ironlake_get_initial_plane_config()
>>>>>     drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
>>>>>     drm/i915: Nuke crtc->plane
>>>>>     drm/i915: Add windowing for primary planes on gen2/3 and chv
>>>>>
>>>>>    drivers/gpu/drm/i915/i915_drv.h      |  16 +-
>>>>>    drivers/gpu/drm/i915/intel_display.c | 500 
>>>>> +++++++++++++++--------------------
>>>>>    drivers/gpu/drm/i915/intel_drv.h     |   8 +-
>>>>>    drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
>>>>>    drivers/gpu/drm/i915/intel_pm.c      |  36 +--
>>>>>    drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
>>>>>    6 files changed, 299 insertions(+), 331 deletions(-)
>>>>>
>>>> Sorry if this sounds like a newbie question, but what kernel version 
>>>> should these two patches be applied against? Can they be applied on 
>>>> top of 4.13.5?
>>> Not sure they apply cleanly to something so old. In general we develop
>>> everything on top of 'git://anongit.freedesktop.org/drm-tip drm-tip' so
>>> that's where they would at least apply. But in that case it's actually
>>> easier to just grab my plane_sanitation_2 branch directly since it's
>>> sitting on top of the latest drm-tip.
>>>
>>> Hmm. Looks like only trivial conflicts when cherry-picking the first
>>> two patches onto 4.13.5. I pushed the result to here:
>>> git://github.com/vsyrjala/linux.git plane_sanitation_2_v4.13
>>> but note that I only compile tested it so it's still possible it won't
>>> actually work.
>>>
>>
>> The plane_sanitation_2 branch fails to module_install on my Acer 
>> Aspire One. It complains at the DEPMOD stage that there is a circular 
>> dependency between drm and drm_kms_helper. I compiled using the 
>> configuration file from 4.13.5 and running "make oldconfig" prior to 
>> building. Therefore I am unable to check whether the patchset fixes 
>> the situation in my machine. What is needed to track and possibly fix 
>> this situation?
>>
>>
> More specifically:
>
>    INSTALL sound/usb/misc/snd-ua101.ko
>    INSTALL sound/usb/snd-usb-audio.ko
>    INSTALL sound/usb/snd-usbmidi-lib.ko
>    INSTALL sound/usb/usx2y/snd-usb-us122l.ko
>    INSTALL sound/usb/usx2y/snd-usb-usx2y.ko
>    INSTALL sound/x86/snd-hdmi-lpe-audio.ko
>    INSTALL virt/lib/irqbypass.ko
>    DEPMOD  4.14.0-rc4
> depmod: ERROR: Cycle detected: drm_kms_helper -> drm -> drm_kms_helper
> depmod: ERROR: Found 2 modules in dependency cycles!
> make: *** [Makefile:1244: _modinst_post] Error 1

Will be fixed by commit 512721a14a2a ("drm/drm_of: Move
drm_of_panel_bridge_remove_function into header.") in in pull request
http://mid.mail-archive.com/20171016093547.b2ioiu6fzswt4bbp@phenom.ffwll.local

BR,
Jani.


>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Alex Villacís Lasso]

El 14/10/17 a las 01:45, Alex Villacis Lasso escribió:
> El 13/10/17 a las 11:28, Alex Villacís Lasso escribió:
>> El 11/10/17 a las 11:38, Ville Syrjälä escribió:
>>> On Wed, Oct 11, 2017 at 04:21:58PM +0000, Alex Villacis Lasso wrote:
>>>> El 11/10/17 a las 11:04, Ville Syrjala escribió:
>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>>
>>>>> This series aims to clean up some of the plane state readout and
>>>>> sanitation, and clean up the enum plane mess a bit by renaming it
>>>>> to enum old_plane_id.
>>>>>
>>>>> The one actual bugfix here is the plane<->crtc sanitation
>>>>> change. Previously we tried to shut down the entire pipe when
>>>>> the plane mapping wasn't what we want, now we just shut down the
>>>>> plane, which is easier.
>>>>>
>>>>> Most of the other stuff is just polish, but I also decided to
>>>>> throw the gen2/3 and chv primary plane windowing support on on top
>>>>> just because it's been bugging me for years, and I was already
>>>>> in the neighbourhood.
>>>>>
>>>>> Series available here:
>>>>> git://github.com/vsyrjala/linux.git plane_sanitation_2
>>>>>
>>>>> Cc: Thierry Reding <thierry.reding@gmail.com>
>>>>> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
>>>>>
>>>>> Ville Syrjälä (9):
>>>>>      drm/i915: Add .get_hw_state() method for planes
>>>>>      drm/i915: Redo plane sanitation during readout
>>>>>      drm/i915: s/enum plane/enum old_plane_id/
>>>>>      drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
>>>>>      drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in
>>>>> initial
>>>>>        fb readout
>>>>>      drm/i915: Nuke ironlake_get_initial_plane_config()
>>>>>      drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
>>>>>      drm/i915: Nuke crtc->plane
>>>>>      drm/i915: Add windowing for primary planes on gen2/3 and chv
>>>>>
>>>>>     drivers/gpu/drm/i915/i915_drv.h      |  16 +-
>>>>>     drivers/gpu/drm/i915/intel_display.c | 500
>>>>> +++++++++++++++--------------------
>>>>>     drivers/gpu/drm/i915/intel_drv.h     |   8 +-
>>>>>     drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
>>>>>     drivers/gpu/drm/i915/intel_pm.c      |  36 +--
>>>>>     drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
>>>>>     6 files changed, 299 insertions(+), 331 deletions(-)
>>>>>
>>>> Sorry if this sounds like a newbie question, but what kernel version
>>>> should these two patches be applied against? Can they be applied on
>>>> top of 4.13.5?
>>> Not sure they apply cleanly to something so old. In general we develop
>>> everything on top of 'git://anongit.freedesktop.org/drm-tip drm-tip' so
>>> that's where they would at least apply. But in that case it's actually
>>> easier to just grab my plane_sanitation_2 branch directly since it's
>>> sitting on top of the latest drm-tip.
>>>
>>> Hmm. Looks like only trivial conflicts when cherry-picking the first
>>> two patches onto 4.13.5. I pushed the result to here:
>>> git://github.com/vsyrjala/linux.git plane_sanitation_2_v4.13
>>> but note that I only compile tested it so it's still possible it won't
>>> actually work.
>>>
>> The plane_sanitation_2 branch fails to module_install on my Acer
>> Aspire One. It complains at the DEPMOD stage that there is a circular
>> dependency between drm and drm_kms_helper. I compiled using the
>> configuration file from 4.13.5 and running "make oldconfig" prior to
>> building. Therefore I am unable to check whether the patchset fixes
>> the situation in my machine. What is needed to track and possibly fix
>> this situation?
>>
>>
> More specifically:
>
>     INSTALL sound/usb/misc/snd-ua101.ko
>     INSTALL sound/usb/snd-usb-audio.ko
>     INSTALL sound/usb/snd-usbmidi-lib.ko
>     INSTALL sound/usb/usx2y/snd-usb-us122l.ko
>     INSTALL sound/usb/usx2y/snd-usb-usx2y.ko
>     INSTALL sound/x86/snd-hdmi-lpe-audio.ko
>     INSTALL virt/lib/irqbypass.ko
>     DEPMOD  4.14.0-rc4
> depmod: ERROR: Cycle detected: drm_kms_helper -> drm -> drm_kms_helper
> depmod: ERROR: Found 2 modules in dependency cycles!
> make: *** [Makefile:1244: _modinst_post] Error 1
>
I have just compiled and installed the branch at git://github.com/vsyrjala/linux.git plane_sanitation_2_v4.13 and it not only fixes the screen corruption undre 4.13.5 (https://bugs.freedesktop.org/show_bug.cgi?id=103223), but also an annoying WARN_ON 
backtrace I experiment with the distro kernel (https://bugs.freedesktop.org/show_bug.cgi?id=98930).

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✓ Fi.CI.BAT: success for drm/i915: Plane assert/readout cleanups etc.

[Patchwork]

== Series Details ==

Series: drm/i915: Plane assert/readout cleanups etc.
URL   : https://patchwork.freedesktop.org/series/31758/
State : success

== Summary ==

Series 31758v1 drm/i915: Plane assert/readout cleanups etc.
https://patchwork.freedesktop.org/api/1.0/series/31758/revisions/1/mbox/

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:454s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:467s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:390s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:572s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:286s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:527s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:520s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:533s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:515s
fi-cfl-s         total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  time:558s
fi-cnl-y         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:613s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:429s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:273s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:598s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:445s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:458s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:505s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:479s
fi-kbl-7500u     total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  time:495s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:578s
fi-kbl-7567u     total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  time:491s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:598s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:666s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:474s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:656s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:533s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:510s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:475s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:578s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:437s

8a09bc166a311443214f03b7f5b379fc21783af1 drm-tip: 2017y-10m-11d-16h-00m-59s UTC integration manifest
792c22f3223f drm/i915: Add windowing for primary planes on gen2/3 and chv
df8961c3a4f2 drm/i915: Nuke crtc->plane
dbf3070fd778 drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
b3c8f195fe40 drm/i915: Nuke ironlake_get_initial_plane_config()
d5ee901c6b09 drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial fb readout
23dd92eb8bab drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
22ad8fd53a2c drm/i915: s/enum plane/enum old_plane_id/
c3ed6281fd93 drm/i915: Redo plane sanitation during readout
22ca75ae67fd drm/i915: Add .get_hw_state() method for planes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5997/
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✓ Fi.CI.IGT: success for drm/i915: Plane assert/readout cleanups etc.

[Patchwork]

== Series Details ==

Series: drm/i915: Plane assert/readout cleanups etc.
URL   : https://patchwork.freedesktop.org/series/31758/
State : success

== Summary ==

Test kms_flip:
        Subgroup plain-flip-ts-check:
                pass       -> FAIL       (shard-hsw) fdo#100368

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-hsw        total:2552 pass:1439 dwarn:0   dfail:0   fail:10  skip:1103 time:9644s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5997/shards.html
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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 2119 bytes --]

On Wed, Oct 11, 2017 at 07:04:46PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This series aims to clean up some of the plane state readout and
> sanitation, and clean up the enum plane mess a bit by renaming it
> to enum old_plane_id.
> 
> The one actual bugfix here is the plane<->crtc sanitation
> change. Previously we tried to shut down the entire pipe when
> the plane mapping wasn't what we want, now we just shut down the
> plane, which is easier.
> 
> Most of the other stuff is just polish, but I also decided to
> throw the gen2/3 and chv primary plane windowing support on on top
> just because it's been bugging me for years, and I was already
> in the neighbourhood.
> 
> Series available here:
> git://github.com/vsyrjala/linux.git plane_sanitation_2
> 
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
> 
> Ville Syrjälä (9):
>   drm/i915: Add .get_hw_state() method for planes
>   drm/i915: Redo plane sanitation during readout
>   drm/i915: s/enum plane/enum old_plane_id/
>   drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
>   drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
>     fb readout
>   drm/i915: Nuke ironlake_get_initial_plane_config()
>   drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
>   drm/i915: Nuke crtc->plane
>   drm/i915: Add windowing for primary planes on gen2/3 and chv
> 
>  drivers/gpu/drm/i915/i915_drv.h      |  16 +-
>  drivers/gpu/drm/i915/intel_display.c | 500 +++++++++++++++--------------------
>  drivers/gpu/drm/i915/intel_drv.h     |   8 +-
>  drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
>  drivers/gpu/drm/i915/intel_pm.c      |  36 +--
>  drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
>  6 files changed, 299 insertions(+), 331 deletions(-)

I take it that this is the same as the plane_sanitation branch that I
tested on yesterday, and it fixes both issues I had seen, so for the
whole series:

Tested-by: Thierry Reding <thierry.reding@gmail.com>

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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Ville Syrjälä]

On Thu, Oct 12, 2017 at 01:35:20PM +0200, Thierry Reding wrote:
> On Wed, Oct 11, 2017 at 07:04:46PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > This series aims to clean up some of the plane state readout and
> > sanitation, and clean up the enum plane mess a bit by renaming it
> > to enum old_plane_id.
> > 
> > The one actual bugfix here is the plane<->crtc sanitation
> > change. Previously we tried to shut down the entire pipe when
> > the plane mapping wasn't what we want, now we just shut down the
> > plane, which is easier.
> > 
> > Most of the other stuff is just polish, but I also decided to
> > throw the gen2/3 and chv primary plane windowing support on on top
> > just because it's been bugging me for years, and I was already
> > in the neighbourhood.
> > 
> > Series available here:
> > git://github.com/vsyrjala/linux.git plane_sanitation_2
> > 
> > Cc: Thierry Reding <thierry.reding@gmail.com>
> > Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
> > 
> > Ville Syrjälä (9):
> >   drm/i915: Add .get_hw_state() method for planes
> >   drm/i915: Redo plane sanitation during readout
> >   drm/i915: s/enum plane/enum old_plane_id/
> >   drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
> >   drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
> >     fb readout
> >   drm/i915: Nuke ironlake_get_initial_plane_config()
> >   drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
> >   drm/i915: Nuke crtc->plane
> >   drm/i915: Add windowing for primary planes on gen2/3 and chv
> > 
> >  drivers/gpu/drm/i915/i915_drv.h      |  16 +-
> >  drivers/gpu/drm/i915/intel_display.c | 500 +++++++++++++++--------------------
> >  drivers/gpu/drm/i915/intel_drv.h     |   8 +-
> >  drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
> >  drivers/gpu/drm/i915/intel_pm.c      |  36 +--
> >  drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
> >  6 files changed, 299 insertions(+), 331 deletions(-)
> 
> I take it that this is the same as the plane_sanitation branch that I
> tested on yesterday,

Close enough ;)

> and it fixes both issues I had seen,

One was the plane assert. What was the other one?

> so for the
> whole series:
> 
> Tested-by: Thierry Reding <thierry.reding@gmail.com>

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 0/9] drm/i915: Plane assert/readout cleanups etc.

[Thierry Reding]

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On Thu, Oct 12, 2017 at 03:19:53PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 12, 2017 at 01:35:20PM +0200, Thierry Reding wrote:
> > On Wed, Oct 11, 2017 at 07:04:46PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > This series aims to clean up some of the plane state readout and
> > > sanitation, and clean up the enum plane mess a bit by renaming it
> > > to enum old_plane_id.
> > > 
> > > The one actual bugfix here is the plane<->crtc sanitation
> > > change. Previously we tried to shut down the entire pipe when
> > > the plane mapping wasn't what we want, now we just shut down the
> > > plane, which is easier.
> > > 
> > > Most of the other stuff is just polish, but I also decided to
> > > throw the gen2/3 and chv primary plane windowing support on on top
> > > just because it's been bugging me for years, and I was already
> > > in the neighbourhood.
> > > 
> > > Series available here:
> > > git://github.com/vsyrjala/linux.git plane_sanitation_2
> > > 
> > > Cc: Thierry Reding <thierry.reding@gmail.com>
> > > Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
> > > 
> > > Ville Syrjälä (9):
> > >   drm/i915: Add .get_hw_state() method for planes
> > >   drm/i915: Redo plane sanitation during readout
> > >   drm/i915: s/enum plane/enum old_plane_id/
> > >   drm/i915: Use enum old_plane_id for the .get_fifo_size() hooks
> > >   drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial
> > >     fb readout
> > >   drm/i915: Nuke ironlake_get_initial_plane_config()
> > >   drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()
> > >   drm/i915: Nuke crtc->plane
> > >   drm/i915: Add windowing for primary planes on gen2/3 and chv
> > > 
> > >  drivers/gpu/drm/i915/i915_drv.h      |  16 +-
> > >  drivers/gpu/drm/i915/intel_display.c | 500 +++++++++++++++--------------------
> > >  drivers/gpu/drm/i915/intel_drv.h     |   8 +-
> > >  drivers/gpu/drm/i915/intel_fbc.c     |  27 +-
> > >  drivers/gpu/drm/i915/intel_pm.c      |  36 +--
> > >  drivers/gpu/drm/i915/intel_sprite.c  |  43 +++
> > >  6 files changed, 299 insertions(+), 331 deletions(-)
> > 
> > I take it that this is the same as the plane_sanitation branch that I
> > tested on yesterday,
> 
> Close enough ;)
> 
> > and it fixes both issues I had seen,
> 
> One was the plane assert. What was the other one?

Yes, the plane assert is what I think was related to the weird
corruption that I've been seeing since 4.13 (the first two lines in the
framebuffer console stay around, the rest of the screen is offset by
those two lines, so the last two lines aren't visible).

The second issue I was seeing, for much longer than 4.13, I think maybe
as far back as 4.9 or so, was that the display would stay black after
resuming from suspend-to-disk (though suspend-to-RAM worked fine). This
could possibly be related to the plane assert, too, but I was never able
to properly diagnose because the device was unresponsive after the
failing resume.

Both of these are gone with this series applied (or the plane_sanitation
branch merged int next-20171009, rather).

Thanks for fixing it!

Thierry

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