Re: [PATCH 8/8] drm/i915: Adjust system agent voltage on CNL if required by DDI ports

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Runyan, Arthur J" <arthur.j.runyan@intel.com>
Subject: Re: [PATCH 8/8] drm/i915: Adjust system agent voltage on CNL if required by DDI ports
Date: Mon, 23 Oct 2017 14:48:43 +0300	[thread overview]
Message-ID: <20171023114843.GU10981@intel.com> (raw)
In-Reply-To: <20171020203642.u7vgrr7tzmcv6mep@intel.com>

On Fri, Oct 20, 2017 at 01:36:42PM -0700, Rodrigo Vivi wrote:
> On Fri, Oct 20, 2017 at 08:07:07PM +0000, Ville Syrjälä wrote:
> > On Fri, Oct 20, 2017 at 05:48:54PM +0000, Runyan, Arthur J wrote:
> > > Sorry about top reply from corporate email...
> > > If you know in advance that you will just be temporarily disabling the PLL, then your sequence works. 
> > 
> > Actually we would end up using this sequence even if disable the PLL for
> > good.
> > 
> > Eg. if we're just disabling the entire pipe+DPLL, we'd do this (assuming
> > cdclk doesn't need changing, but voltage can be lowered due to the port
> > no longer requiring it):
> > 1. disable DPLL
> > 2. disable DPLL power
> > ...
> > 3. DVFS pre sequence
> > 4. DVFS post sequence
> > 
> > And when starting up a pipe from the cold with a new DPLL we'd conversly
> > do this (again assuming no cdclk change, but voltage would have to be
> > ramped up for the port):
> > 1. DVFS pre sequence
> > 2. DVFS post sequence
> > ...
> > 3. enable DPLL power
> > 4. enable DPLL
> > 
> > It does look a bit strange doing the DVFS sequences on their own like
> > that, but I don't see why that should be problem. From where I'm sitting
> > it doesn't really look any different than the following seqeunces:
> > 
> > Disable with cdclk changing but port clock not having any effect
> > on the voltage:
> > 1. disable DPLL
> > 2. disable DPLL power
> > ...
> > 3. DVFS pre sequence
> > 4. change cdclk
> > 5. DVFS post sequence
> > 
> > Enable with cdclk changing but port clock not having any effect
> > on the voltage:
> > 1. DVFS pre sequence
> > 2. change cdclk
> > 3. DVFS post sequence
> > ...
> > 4. enable DPLL power
> > 5. enable DPLL
> > 
> > So unless something is snooping the actual state of the DPLLs, and based
> > on that second guessing our choice of voltage, I don't really see how
> > these two cases differ at all.
> 
> Well, I admit that I'm kind of lost on the discussion now.
> 
> but spec tells that we need use pre and post DVFS sequence
> always on CDCLK part and on DPLL only "If the frequency will result in a
> change to the voltage requirement,"
> So in the temporary disable-re-enable case we would be safe, because
> there woulnd't be no need to keep tweaking the voltage...
> 
> However on the other case you mentioned for the full pipe disable
> it seems that we have a situation of non optimal power getting
> wasted, right?!

No. The voltage will be reduced, but only after all relevant DPLLs have
been disabled. And conversly the voltage will be increased before any
relevant DPLLs will be enabled. So instead of talking to pcode around
the actual DPLL enable/disable register writes we do it well before/after
we touch the DPLL(s).

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx