From: Rob Herring <robh@kernel.org>
To: Stafford Horne <shorne@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Openrisc <openrisc@lists.librecores.org>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>,
Marc Zyngier <marc.zyngier@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Mark Rutland <mark.rutland@arm.com>,
Jonas Bonn <jonas@southpole.se>,
"David S. Miller" <davem@davemloft.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Randy Dunlap <rdunlap@infradead.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 05/13] irqchip: add initial support for ompic
Date: Thu, 26 Oct 2017 22:19:50 -0500 [thread overview]
Message-ID: <20171027031950.wce52pj3eklsbwyj@rob-hp-laptop> (raw)
In-Reply-To: <20171022031600.29612-6-shorne@gmail.com>
On Sun, Oct 22, 2017 at 12:15:52PM +0900, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> described in the Multi-core support section of the OpenRISC 1.2
> proposed architecture specification:
>
> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing. This IPI device, the
> ompic, is the only external device required for enabling SMP on
> OpenRISC.
>
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>
> Changes since v2
> - Fixed some issues with missing static
> - Fixed spelling issue with multi-core
> - Added back #interrupt-cells
>
> Changes since v1
> - Added openrisc, prefix
> - Clarified 8 bytes per cpu
> - Removed #interrupt-cells as this will not be an irq parent
> - Changed ops to be percpu
> - Added DTS and intialization failure validations
>
>
> .../interrupt-controller/openrisc,ompic.txt | 22 +++
Acked-by: Rob Herring <robh@kernel.org>
> MAINTAINERS | 1 +
> arch/openrisc/Kconfig | 1 +
> drivers/irqchip/Kconfig | 3 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++
> 6 files changed, 233 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> create mode 100644 drivers/irqchip/irq-ompic.c
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Stafford Horne <shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: LKML <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Openrisc
<openrisc-cunTk1MwBs9a3B2Vnqf2dGD2FQJk+8+b@public.gmane.org>,
Stefan Kristiansson
<stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>,
Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Jonas Bonn <jonas-A9uVI2HLR7kOP4wsBPIw7w@public.gmane.org>,
"David S. Miller" <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>,
Greg Kroah-Hartman
<gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>,
Mauro Carvalho Chehab
<mchehab-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v3 05/13] irqchip: add initial support for ompic
Date: Thu, 26 Oct 2017 22:19:50 -0500 [thread overview]
Message-ID: <20171027031950.wce52pj3eklsbwyj@rob-hp-laptop> (raw)
In-Reply-To: <20171022031600.29612-6-shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Sun, Oct 22, 2017 at 12:15:52PM +0900, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>
>
> IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> described in the Multi-core support section of the OpenRISC 1.2
> proposed architecture specification:
>
> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing. This IPI device, the
> ompic, is the only external device required for enabling SMP on
> OpenRISC.
>
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA@public.gmane.org>
> [shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>
> Changes since v2
> - Fixed some issues with missing static
> - Fixed spelling issue with multi-core
> - Added back #interrupt-cells
>
> Changes since v1
> - Added openrisc, prefix
> - Clarified 8 bytes per cpu
> - Removed #interrupt-cells as this will not be an irq parent
> - Changed ops to be percpu
> - Added DTS and intialization failure validations
>
>
> .../interrupt-controller/openrisc,ompic.txt | 22 +++
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> MAINTAINERS | 1 +
> arch/openrisc/Kconfig | 1 +
> drivers/irqchip/Kconfig | 3 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++
> 6 files changed, 233 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> create mode 100644 drivers/irqchip/irq-ompic.c
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v3 05/13] irqchip: add initial support for ompic
Date: Thu, 26 Oct 2017 22:19:50 -0500 [thread overview]
Message-ID: <20171027031950.wce52pj3eklsbwyj@rob-hp-laptop> (raw)
In-Reply-To: <20171022031600.29612-6-shorne@gmail.com>
On Sun, Oct 22, 2017 at 12:15:52PM +0900, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> described in the Multi-core support section of the OpenRISC 1.2
> proposed architecture specification:
>
> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing. This IPI device, the
> ompic, is the only external device required for enabling SMP on
> OpenRISC.
>
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne at gmail.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>
> Changes since v2
> - Fixed some issues with missing static
> - Fixed spelling issue with multi-core
> - Added back #interrupt-cells
>
> Changes since v1
> - Added openrisc, prefix
> - Clarified 8 bytes per cpu
> - Removed #interrupt-cells as this will not be an irq parent
> - Changed ops to be percpu
> - Added DTS and intialization failure validations
>
>
> .../interrupt-controller/openrisc,ompic.txt | 22 +++
Acked-by: Rob Herring <robh@kernel.org>
> MAINTAINERS | 1 +
> arch/openrisc/Kconfig | 1 +
> drivers/irqchip/Kconfig | 3 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++
> 6 files changed, 233 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> create mode 100644 drivers/irqchip/irq-ompic.c
next prev parent reply other threads:[~2017-10-27 3:19 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-22 3:15 [PATCH v3 00/13] OpenRISC SMP Support Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 02/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 03/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 04/13] dt-bindings: add openrisc to vendor prefixes list Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 05/13] irqchip: add initial support for ompic Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-23 8:00 ` Marc Zyngier
2017-10-23 8:00 ` [OpenRISC] " Marc Zyngier
2017-10-23 8:00 ` Marc Zyngier
2017-10-23 12:57 ` Stafford Horne
2017-10-23 12:57 ` [OpenRISC] " Stafford Horne
2017-10-27 3:19 ` Rob Herring [this message]
2017-10-27 3:19 ` Rob Herring
2017-10-27 3:19 ` Rob Herring
2017-10-22 3:15 ` [PATCH v3 06/13] openrisc: initial SMP support Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:15 ` [PATCH v3 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-10-22 3:15 ` [OpenRISC] " Stafford Horne
2017-10-22 3:16 ` [PATCH v3 13/13] openrisc: add tick timer multi-core sync logic Stafford Horne
2017-10-22 3:16 ` [OpenRISC] " Stafford Horne
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