* [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK
@ 2017-12-04 4:31 Peng Fan
2017-12-04 4:31 ` [U-Boot] [PATCH V2 01/23] imx: add i.MX8M into Kconfig Peng Fan
` (22 more replies)
0 siblings, 23 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
This patchset is to add i.MX8M and i.MX8MQ-EVK support
V2:
The two patches: "power: pmic.h: include dm/ofnode.h" and
"power: pmic/regulator allow dm be omited by SPL"
are still included in the patchset.
patch 02/23: convert to structure, drop is_boot_from_usb and
disconnect_from_usb
patch 04/23: conver to use structure for the clock driver, removed the
CCM_xxx macros. Add static for local functons.
Add init_usdhc_clk, init_uart_clk and etc to not enable
them all at default.
patch 05/23: Add more commit msg for the sip part.
patch 08/23: Merge the spl boot device with i.MX7
patch 12/23: Typo fix and return error fix from Heiko for the SoC related part
patch 22/23: Use a weak function ddr_init. If patch 23/23 could not be
accepted at current stage, to make others still be could be
compiled.
The patchset depends on
https://patchwork.ozlabs.org/patch/841934/
https://patchwork.ozlabs.org/patch/841958/
to be tested on real hardware.
V1:
patch: "power: pmic.h: include dm/ofnode.h" and
"power: pmic/regulator allow dm be omited by SPL" is previously reviewed
in mailist to not merged. If no issue, you may pick it up.
The board support is a large patch because of the ddr related code.
If it is not good, please first review/pick-up other patches if they
are ok.
Peng Fan (23):
imx: add i.MX8M into Kconfig
imx: mx8m: add register definition header file
imx: mx8m: add pin header file
imx: mx8m: add clock driver
imx: add sip function
imx: boot_mode: add USB_BOOT entry
power: pmic.h: include dm/ofnode.h
imx: cpu: update cpu file to support i.MX8M
imx: spl: implement spl_boot_device for i.MX8M
imx: add i.MX8MQ SoC Revision and is_mx8m helper
imx: add pad settings bit definition for i.MX8M
imx: mx8m: add soc related settings and files
imx: makefile: compile files for i.MX8M
misc: ocotp: add i.MX8M support
mmc: fsl_esdhc: support i.MX8M
imx: lcdif: include i.MX8M
gpio: mxc: add i.MX8M support
net: fec: do not access reserved register for i.MX8M
net: fec: fix build warnings for 64bits support
power: pmic/regulator allow dm be omitted by SPL
imx: imx8mq: add dtsi file
imx: add i.MX8MQ EVK support
Add DDR settings
arch/arm/Kconfig | 8 +
arch/arm/Makefile | 4 +-
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-imx8-ca53.dtsi | 92 ++
arch/arm/dts/fsl-imx8mq-evk.dts | 424 ++++++++
arch/arm/dts/fsl-imx8mq.dtsi | 425 ++++++++
arch/arm/include/asm/arch-imx/cpu.h | 6 +-
arch/arm/include/asm/arch-mx8m/clock.h | 657 +++++++++++
arch/arm/include/asm/arch-mx8m/crm_regs.h | 10 +
arch/arm/include/asm/arch-mx8m/ddr_memory_map.h | 495 +++++++++
arch/arm/include/asm/arch-mx8m/gpio.h | 12 +
arch/arm/include/asm/arch-mx8m/imx-regs.h | 318 ++++++
arch/arm/include/asm/arch-mx8m/mx8mq_pins.h | 623 +++++++++++
arch/arm/include/asm/arch-mx8m/sys_proto.h | 18 +
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
arch/arm/include/asm/mach-imx/iomux-v3.h | 22 +-
arch/arm/include/asm/mach-imx/regs-lcdif.h | 11 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 4 +
arch/arm/mach-imx/Makefile | 14 +-
arch/arm/mach-imx/cpu.c | 11 +-
arch/arm/mach-imx/mx8m/Kconfig | 22 +
arch/arm/mach-imx/mx8m/Makefile | 8 +
arch/arm/mach-imx/mx8m/clock.c | 788 ++++++++++++++
arch/arm/mach-imx/mx8m/clock_slice.c | 742 +++++++++++++
arch/arm/mach-imx/mx8m/lowlevel_init.S | 63 ++
arch/arm/mach-imx/mx8m/soc.c | 539 +++++++++
arch/arm/mach-imx/sip.c | 23 +
arch/arm/mach-imx/spl.c | 10 +-
board/freescale/mx8mq_evk/Kconfig | 12 +
board/freescale/mx8mq_evk/Makefile | 12 +
board/freescale/mx8mq_evk/README | 38 +
board/freescale/mx8mq_evk/ddr/ddr.h | 38 +
board/freescale/mx8mq_evk/ddr/ddr_init.c | 256 +++++
board/freescale/mx8mq_evk/ddr/ddrphy_train.c | 1147 ++++++++++++++++++++
board/freescale/mx8mq_evk/ddr/helper.c | 101 ++
.../mx8mq_evk/ddr/wait_ddrphy_training_complete.c | 97 ++
board/freescale/mx8mq_evk/mx8mq_evk.c | 156 +++
board/freescale/mx8mq_evk/spl.c | 233 ++++
configs/mx8mq_evk_defconfig | 28 +
drivers/gpio/mxc_gpio.c | 22 +-
drivers/misc/mxc_ocotp.c | 7 +
drivers/mmc/fsl_esdhc.c | 12 +-
drivers/net/fec_mxc.c | 78 +-
drivers/power/pmic/Makefile | 4 +-
drivers/power/regulator/Makefile | 2 +-
include/configs/mx8mq_evk.h | 265 +++++
include/dt-bindings/clock/imx8mq-clock.h | 612 +++++++++++
include/dt-bindings/pinctrl/pins-imx8mq.h | 632 +++++++++++
include/imx_sip.h | 14 +
include/power/pmic.h | 1 +
50 files changed, 9058 insertions(+), 61 deletions(-)
create mode 100644 arch/arm/dts/fsl-imx8-ca53.dtsi
create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
create mode 100644 arch/arm/dts/fsl-imx8mq.dtsi
create mode 100644 arch/arm/include/asm/arch-mx8m/clock.h
create mode 100644 arch/arm/include/asm/arch-mx8m/crm_regs.h
create mode 100644 arch/arm/include/asm/arch-mx8m/ddr_memory_map.h
create mode 100644 arch/arm/include/asm/arch-mx8m/gpio.h
create mode 100644 arch/arm/include/asm/arch-mx8m/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
create mode 100644 arch/arm/include/asm/arch-mx8m/sys_proto.h
create mode 100644 arch/arm/mach-imx/mx8m/Kconfig
create mode 100644 arch/arm/mach-imx/mx8m/Makefile
create mode 100644 arch/arm/mach-imx/mx8m/clock.c
create mode 100644 arch/arm/mach-imx/mx8m/clock_slice.c
create mode 100644 arch/arm/mach-imx/mx8m/lowlevel_init.S
create mode 100644 arch/arm/mach-imx/mx8m/soc.c
create mode 100644 arch/arm/mach-imx/sip.c
create mode 100644 board/freescale/mx8mq_evk/Kconfig
create mode 100644 board/freescale/mx8mq_evk/Makefile
create mode 100644 board/freescale/mx8mq_evk/README
create mode 100644 board/freescale/mx8mq_evk/ddr/ddr.h
create mode 100644 board/freescale/mx8mq_evk/ddr/ddr_init.c
create mode 100644 board/freescale/mx8mq_evk/ddr/ddrphy_train.c
create mode 100644 board/freescale/mx8mq_evk/ddr/helper.c
create mode 100644 board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c
create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
create mode 100644 board/freescale/mx8mq_evk/spl.c
create mode 100644 configs/mx8mq_evk_defconfig
create mode 100644 include/configs/mx8mq_evk.h
create mode 100644 include/dt-bindings/clock/imx8mq-clock.h
create mode 100644 include/dt-bindings/pinctrl/pins-imx8mq.h
create mode 100644 include/imx_sip.h
--
2.14.1
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 01/23] imx: add i.MX8M into Kconfig
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:16 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 02/23] imx: mx8m: add register definition header file Peng Fan
` (21 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add i.MX8M into Kconfig, create a new folder mx8m
dedicated for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/Kconfig | 8 ++++++++
arch/arm/Makefile | 4 ++--
arch/arm/mach-imx/mx8m/Kconfig | 10 ++++++++++
3 files changed, 20 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-imx/mx8m/Kconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ca386decfe..3b2adbc1f2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -604,6 +604,12 @@ config ARCH_MESON
targeted at media players and tablet computers. We currently
support the S905 (GXBaby) 64-bit SoC.
+config ARCH_MX8M
+ bool "NXP i.MX8M platform"
+ select ARM64
+ select DM
+ select SUPPORT_SPL
+
config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
@@ -1177,6 +1183,8 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
+source "arch/arm/mach-imx/mx8m/Kconfig"
+
source "arch/arm/mach-imx/mx7ulp/Kconfig"
source "arch/arm/mach-imx/mx7/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5f1caf8f86..4db0398dde 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610))
libs-y += arch/arm/mach-imx/
endif
endif
diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
new file mode 100644
index 0000000000..3a84c2f2b0
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/Kconfig
@@ -0,0 +1,10 @@
+if ARCH_MX8M
+
+config MX8M
+ bool
+ select ROM_UNIFIED_SECTIONS
+
+config SYS_SOC
+ default "mx8m"
+
+endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 02/23] imx: mx8m: add register definition header file
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
2017-12-04 4:31 ` [U-Boot] [PATCH V2 01/23] imx: add i.MX8M into Kconfig Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:17 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 03/23] imx: mx8m: add pin " Peng Fan
` (20 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add register definition header file for i.MX8M
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-mx8m/imx-regs.h | 318 ++++++++++++++++++++++++++++++
1 file changed, 318 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx8m/imx-regs.h
diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-mx8m/imx-regs.h
new file mode 100644
index 0000000000..2fb392d08e
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/imx-regs.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_REGS_H__
+#define __ASM_ARCH_MX8M_REGS_H__
+
+#include <asm/mach-imx/regs-lcdif.h>
+
+#define M4_BOOTROM_BASE_ADDR 0x007E0000
+
+#define SAI1_BASE_ADDR 0x30010000
+#define SAI6_BASE_ADDR 0x30030000
+#define SAI5_BASE_ADDR 0x30040000
+#define SAI4_BASE_ADDR 0x30050000
+#define SPBA2_BASE_ADDR 0x300F0000
+#define AIPS1_BASE_ADDR 0x301F0000
+#define GPIO1_BASE_ADDR 0X30200000
+#define GPIO2_BASE_ADDR 0x30210000
+#define GPIO3_BASE_ADDR 0x30220000
+#define GPIO4_BASE_ADDR 0x30230000
+#define GPIO5_BASE_ADDR 0x30240000
+#define ANA_TSENSOR_BASE_ADDR 0x30260000
+#define ANA_OSC_BASE_ADDR 0x30270000
+#define WDOG1_BASE_ADDR 0x30280000
+#define WDOG2_BASE_ADDR 0x30290000
+#define WDOG3_BASE_ADDR 0x302A0000
+#define SDMA2_BASE_ADDR 0x302C0000
+#define GPT1_BASE_ADDR 0x302D0000
+#define GPT2_BASE_ADDR 0x302E0000
+#define GPT3_BASE_ADDR 0x302F0000
+#define ROMCP_BASE_ADDR 0x30310000
+#define LCDIF_BASE_ADDR 0x30320000
+#define IOMUXC_BASE_ADDR 0x30330000
+#define IOMUXC_GPR_BASE_ADDR 0x30340000
+#define OCOTP_BASE_ADDR 0x30350000
+#define ANA_PLL_BASE_ADDR 0x30360000
+#define SNVS_HP_BASE_ADDR 0x30370000
+#define CCM_BASE_ADDR 0x30380000
+#define SRC_BASE_ADDR 0x30390000
+#define GPC_BASE_ADDR 0x303A0000
+#define SEMAPHORE1_BASE_ADDR 0x303B0000
+#define SEMAPHORE2_BASE_ADDR 0x303C0000
+#define RDC_BASE_ADDR 0x303D0000
+#define CSU_BASE_ADDR 0x303E0000
+
+#define AIPS2_BASE_ADDR 0x305F0000
+#define PWM1_BASE_ADDR 0x30660000
+#define PWM2_BASE_ADDR 0x30670000
+#define PWM3_BASE_ADDR 0x30680000
+#define PWM4_BASE_ADDR 0x30690000
+#define SYSCNT_RD_BASE_ADDR 0x306A0000
+#define SYSCNT_CMP_BASE_ADDR 0x306B0000
+#define SYSCNT_CTRL_BASE_ADDR 0x306C0000
+#define GPT6_BASE_ADDR 0x306E0000
+#define GPT5_BASE_ADDR 0x306F0000
+#define GPT4_BASE_ADDR 0x30700000
+#define PERFMON1_BASE_ADDR 0x307C0000
+#define PERFMON2_BASE_ADDR 0x307D0000
+#define QOSC_BASE_ADDR 0x307F0000
+
+#define SPDIF1_BASE_ADDR 0x30810000
+#define ECSPI1_BASE_ADDR 0x30820000
+#define ECSPI2_BASE_ADDR 0x30830000
+#define ECSPI3_BASE_ADDR 0x30840000
+#define UART1_BASE_ADDR 0x30860000
+#define UART3_BASE_ADDR 0x30880000
+#define UART2_BASE_ADDR 0x30890000
+#define SPDIF2_BASE_ADDR 0x308A0000
+#define SAI2_BASE_ADDR 0x308B0000
+#define SAI3_BASE_ADDR 0x308C0000
+#define SPBA1_BASE_ADDR 0x308F0000
+#define CAAM_BASE_ADDR 0x30900000
+#define AIPS3_BASE_ADDR 0x309F0000
+#define MIPI_PHY_BASE_ADDR 0x30A00000
+#define MIPI_DSI_BASE_ADDR 0x30A10000
+#define I2C1_BASE_ADDR 0x30A20000
+#define I2C2_BASE_ADDR 0x30A30000
+#define I2C3_BASE_ADDR 0x30A40000
+#define I2C4_BASE_ADDR 0x30A50000
+#define UART4_BASE_ADDR 0x30A60000
+#define MIPI_CSI_BASE_ADDR 0x30A70000
+#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000
+#define CSI1_BASE_ADDR 0x30A90000
+#define MU_A_BASE_ADDR 0x30AA0000
+#define MU_B_BASE_ADDR 0x30AB0000
+#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000
+#define USDHC1_BASE_ADDR 0x30B40000
+#define USDHC2_BASE_ADDR 0x30B50000
+#define MIPI_CS2_BASE_ADDR 0x30B60000
+#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000
+#define CSI2_BASE_ADDR 0x30B80000
+#define QSPI0_BASE_ADDR 0x30BB0000
+#define QSPI0_AMBA_BASE 0x08000000
+#define SDMA1_BASE_ADDR 0x30BD0000
+#define ENET1_BASE_ADDR 0x30BE0000
+
+#define HDMI_CTRL_BASE_ADDR 0x32C00000
+#define AIPS4_BASE_ADDR 0x32DF0000
+#define DC1_BASE_ADDR 0x32E00000
+#define DC2_BASE_ADDR 0x32E10000
+#define DC3_BASE_ADDR 0x32E20000
+#define HDMI_SEC_BASE_ADDR 0x32E40000
+#define TZASC_BASE_ADDR 0x32F80000
+#define MTR_BASE_ADDR 0x32FB0000
+#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000
+
+#define MXS_APBH_BASE 0x33000000
+#define MXS_GPMI_BASE 0x33002000
+#define MXS_BCH_BASE 0x33004000
+
+#define USB1_BASE_ADDR 0x38100000
+#define USB2_BASE_ADDR 0x38200000
+#define USB1_PHY_BASE_ADDR 0x381F0000
+#define USB2_PHY_BASE_ADDR 0x382F0000
+
+#define MXS_LCDIF_BASE LCDIF_BASE_ADDR
+
+#define SRC_IPS_BASE_ADDR 0x30390000
+#define SRC_DDRC_RCR_ADDR 0x30391000
+#define SRC_DDRC2_RCR_ADDR 0x30391004
+
+#define DDRC_DDR_SS_GPR0 0x3d000000
+#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
+#define DDR_CSD1_BASE_ADDR 0x40000000
+
+#if !defined(__ASSEMBLY__)
+#include <asm/types.h>
+#include <linux/bitops.h>
+#include <stdbool.h>
+
+#define GPR_TZASC_EN BIT(0)
+#define GPR_TZASC_EN_LOCK BIT(16)
+
+#define SRC_SCR_M4_ENABLE_OFFSET 3
+#define SRC_SCR_M4_ENABLE_MASK BIT(3)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
+#define SRC_DDR1_ENABLE_MASK 0x8F000000UL
+#define SRC_DDR2_ENABLE_MASK 0x8F000000UL
+
+struct iomuxc_gpr_base_regs {
+ u32 gpr[47];
+};
+
+struct ocotp_regs {
+ u32 ctrl;
+ u32 ctrl_set;
+ u32 ctrl_clr;
+ u32 ctrl_tog;
+ u32 timing;
+ u32 rsvd0[3];
+ u32 data;
+ u32 rsvd1[3];
+ u32 read_ctrl;
+ u32 rsvd2[3];
+ u32 read_fuse_data;
+ u32 rsvd3[3];
+ u32 sw_sticky;
+ u32 rsvd4[3];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd5[3];
+ u32 crc_value;
+ u32 rsvd6[3];
+ u32 version;
+ u32 rsvd7[0xdb];
+
+ /* fuse banks */
+ struct fuse_bank {
+ u32 fuse_regs[0x10];
+ } bank[0];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[7];
+};
+
+struct fuse_bank1_regs {
+ u32 tester3;
+ u32 rsvd0[3];
+ u32 tester4;
+ u32 rsvd1[3];
+ u32 tester5;
+ u32 rsvd2[3];
+ u32 cfg0;
+ u32 rsvd3[3];
+};
+
+struct anamix_pll {
+ u32 audio_pll1_cfg0;
+ u32 audio_pll1_cfg1;
+ u32 audio_pll2_cfg0;
+ u32 audio_pll2_cfg1;
+ u32 video_pll_cfg0;
+ u32 video_pll_cfg1;
+ u32 gpu_pll_cfg0;
+ u32 gpu_pll_cfg1;
+ u32 vpu_pll_cfg0;
+ u32 vpu_pll_cfg1;
+ u32 arm_pll_cfg0;
+ u32 arm_pll_cfg1;
+ u32 sys_pll1_cfg0;
+ u32 sys_pll1_cfg1;
+ u32 sys_pll1_cfg2;
+ u32 sys_pll2_cfg0;
+ u32 sys_pll2_cfg1;
+ u32 sys_pll2_cfg2;
+ u32 sys_pll3_cfg0;
+ u32 sys_pll3_cfg1;
+ u32 sys_pll3_cfg2;
+ u32 video_pll2_cfg0;
+ u32 video_pll2_cfg1;
+ u32 video_pll2_cfg2;
+ u32 dram_pll_cfg0;
+ u32 dram_pll_cfg1;
+ u32 dram_pll_cfg2;
+ u32 digprog;
+ u32 osc_misc_cfg;
+ u32 pllout_monitor_cfg;
+ u32 frac_pllout_div_cfg;
+ u32 sscg_pllout_div_cfg;
+};
+
+struct fuse_bank9_regs {
+ u32 mac_addr0;
+ u32 rsvd0[3];
+ u32 mac_addr1;
+ u32 rsvd1[11];
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 a53rcr;
+ u32 a53rcr1;
+ u32 m4rcr;
+ u32 reserved1[4];
+ u32 usbophy1_rcr;
+ u32 usbophy2_rcr;
+ u32 mipiphy_rcr;
+ u32 pciephy_rcr;
+ u32 hdmi_rcr;
+ u32 disp_rcr;
+ u32 reserved2[2];
+ u32 gpu_rcr;
+ u32 vpu_rcr;
+ u32 pcie2_rcr;
+ u32 mipiphy1_rcr;
+ u32 mipiphy2_rcr;
+ u32 reserved3;
+ u32 sbmr1;
+ u32 srsr;
+ u32 reserved4[2];
+ u32 sisr;
+ u32 simr;
+ u32 sbmr2;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 gpr5;
+ u32 gpr6;
+ u32 gpr7;
+ u32 gpr8;
+ u32 gpr9;
+ u32 gpr10;
+ u32 reserved5[985];
+ u32 ddr1_rcr;
+ u32 ddr2_rcr;
+};
+
+#define WDOG_WDT_MASK BIT(3)
+#define WDOG_WDZST_MASK BIT(0)
+struct wdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Miscellaneous Control */
+};
+
+/* Boot device type */
+#define BOOT_TYPE_SD 0x1
+#define BOOT_TYPE_MMC 0x2
+#define BOOT_TYPE_NAND 0x3
+#define BOOT_TYPE_QSPI 0x4
+#define BOOT_TYPE_WEIM 0x5
+#define BOOT_TYPE_SPINOR 0x6
+#define BOOT_TYPE_USB 0xF
+
+#define ROM_SW_INFO_ADDR 0x00000968
+#define ROM_SW_INFO_ADDR_A0 0x000009e8
+
+struct bootrom_sw_info {
+ u8 reserved_1;
+ u8 boot_dev_instance;
+ u8 boot_dev_type;
+ u8 reserved_2;
+ u32 core_freq;
+ u32 axi_freq;
+ u32 ddr_freq;
+ u32 tick_freq;
+ u32 reserved_3[3];
+};
+
+#endif
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 03/23] imx: mx8m: add pin header file
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
2017-12-04 4:31 ` [U-Boot] [PATCH V2 01/23] imx: add i.MX8M into Kconfig Peng Fan
2017-12-04 4:31 ` [U-Boot] [PATCH V2 02/23] imx: mx8m: add register definition header file Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:18 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 04/23] imx: mx8m: add clock driver Peng Fan
` (19 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add pin header file for i.MX8M
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-mx8m/mx8mq_pins.h | 623 ++++++++++++++++++++++++++++
1 file changed, 623 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
new file mode 100644
index 0000000000..062bea7299
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
@@ -0,0 +1,623 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8MQ_PINS_H__
+#define __ASM_ARCH_MX8MQ_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+ IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+
+ IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+ IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+ IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+ IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+ IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+ IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+ IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+ IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+ IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+ IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+ IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+ IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+ IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+ IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+ IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+ IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+ IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+ IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+ IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+ IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+ IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+ IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+ IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+ IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+ IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+ IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+ IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+ IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+ IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+ IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+ IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+ IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+ IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+ IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+ IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
+ IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+ IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+ IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+ IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+ IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+ IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+ IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+ IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+ IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+ IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
+ IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 04/23] imx: mx8m: add clock driver
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (2 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 03/23] imx: mx8m: add pin " Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:33 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 05/23] imx: add sip function Peng Fan
` (18 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add clock driver to support i.MX8M.
There are two kind PLLs, FRAC pll and SSCG pll. ROM already
configured SYS PLL1/2, we only need to configure the output.
ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
enet clock are configured in the code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-mx8m/clock.h | 657 +++++++++++++++++++++++++++
arch/arm/mach-imx/mx8m/Makefile | 7 +
arch/arm/mach-imx/mx8m/clock.c | 788 +++++++++++++++++++++++++++++++++
arch/arm/mach-imx/mx8m/clock_slice.c | 742 +++++++++++++++++++++++++++++++
4 files changed, 2194 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx8m/clock.h
create mode 100644 arch/arm/mach-imx/mx8m/Makefile
create mode 100644 arch/arm/mach-imx/mx8m/clock.c
create mode 100644 arch/arm/mach-imx/mx8m/clock_slice.c
diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-mx8m/clock.h
new file mode 100644
index 0000000000..555512b453
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/clock.h
@@ -0,0 +1,657 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+#include <linux/bitops.h>
+
+enum pll_clocks {
+ ANATOP_ARM_PLL,
+ ANATOP_GPU_PLL,
+ ANATOP_SYSTEM_PLL1,
+ ANATOP_SYSTEM_PLL2,
+ ANATOP_SYSTEM_PLL3,
+ ANATOP_AUDIO_PLL1,
+ ANATOP_AUDIO_PLL2,
+ ANATOP_VIDEO_PLL1,
+ ANATOP_VIDEO_PLL2,
+ ANATOP_DRAM_PLL,
+};
+
+enum clk_slice_type {
+ CORE_CLOCK_SLICE,
+ BUS_CLOCK_SLICE,
+ IP_CLOCK_SLICE,
+ AHB_CLOCK_SLICE,
+ IPG_CLOCK_SLICE,
+ CORE_SEL_CLOCK_SLICE,
+ DRAM_SEL_CLOCK_SLICE,
+};
+
+enum clk_root_index {
+ MXC_ARM_CLK = 0,
+ ARM_A53_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ VPU_A53_CLK_ROOT = 2,
+ GPU_CORE_CLK_ROOT = 3,
+ GPU_SHADER_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ VPU_BUS_CLK_ROOT = 19,
+ DISPLAY_AXI_CLK_ROOT = 20,
+ DISPLAY_APB_CLK_ROOT = 21,
+ DISPLAY_RTRM_CLK_ROOT = 22,
+ USB_BUS_CLK_ROOT = 23,
+ GPU_AXI_CLK_ROOT = 24,
+ GPU_AHB_CLK_ROOT = 25,
+ NOC_CLK_ROOT = 26,
+ NOC_APB_CLK_ROOT = 27,
+ AHB_CLK_ROOT = 32,
+ IPG_CLK_ROOT = 33,
+ MXC_IPG_CLK = 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ MIPI_DSI_ESC_RX_CLK_ROOT = 36,
+ DRAM_SEL_CFG = 48,
+ CORE_SEL_CFG = 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ VPU_G1_CLK_ROOT = 66,
+ VPU_G2_CLK_ROOT = 67,
+ DISPLAY_DTRC_CLK_ROOT = 68,
+ DISPLAY_DC8000_CLK_ROOT = 69,
+ PCIE1_CTRL_CLK_ROOT = 70,
+ PCIE1_PHY_CLK_ROOT = 71,
+ PCIE1_AUX_CLK_ROOT = 72,
+ DC_PIXEL_CLK_ROOT = 73,
+ LCDIF_PIXEL_CLK_ROOT = 74,
+ SAI1_CLK_ROOT = 75,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI4_CLK_ROOT = 78,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ SPDIF2_CLK_ROOT = 82,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT = 87,
+ MXC_ESDHC_CLK = 88,
+ USDHC1_CLK_ROOT = 88,
+ MXC_ESDHC2_CLK = 89,
+ USDHC2_CLK_ROOT = 89,
+ I2C1_CLK_ROOT = 90,
+ MXC_I2C_CLK = 90,
+ I2C2_CLK_ROOT = 91,
+ I2C3_CLK_ROOT = 92,
+ I2C4_CLK_ROOT = 93,
+ UART1_CLK_ROOT = 94,
+ UART2_CLK_ROOT = 95,
+ UART3_CLK_ROOT = 96,
+ UART4_CLK_ROOT = 97,
+ USB_CORE_REF_CLK_ROOT = 98,
+ USB_PHY_REF_CLK_ROOT = 99,
+ GIC_CLK_ROOT = 100,
+ ECSPI1_CLK_ROOT = 101,
+ ECSPI2_CLK_ROOT = 102,
+ PWM1_CLK_ROOT = 103,
+ PWM2_CLK_ROOT = 104,
+ PWM3_CLK_ROOT = 105,
+ PWM4_CLK_ROOT = 106,
+ GPT1_CLK_ROOT = 107,
+ GPT2_CLK_ROOT = 108,
+ GPT3_CLK_ROOT = 109,
+ GPT4_CLK_ROOT = 110,
+ GPT5_CLK_ROOT = 111,
+ GPT6_CLK_ROOT = 112,
+ TRACE_CLK_ROOT = 113,
+ WDOG_CLK_ROOT = 114,
+ WRCLK_CLK_ROOT = 115,
+ IPP_DO_CLKO1 = 116,
+ IPP_DO_CLKO2 = 117,
+ MIPI_DSI_CORE_CLK_ROOT = 118,
+ MIPI_DSI_PHY_REF_CLK_ROOT = 119,
+ MIPI_DSI_DBI_CLK_ROOT = 120,
+ OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
+ MIPI_CSI1_CORE_CLK_ROOT = 122,
+ MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
+ MIPI_CSI1_ESC_CLK_ROOT = 124,
+ MIPI_CSI2_CORE_CLK_ROOT = 125,
+ MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
+ MIPI_CSI2_ESC_CLK_ROOT = 127,
+ PCIE2_CTRL_CLK_ROOT = 128,
+ PCIE2_PHY_CLK_ROOT = 129,
+ PCIE2_AUX_CLK_ROOT = 130,
+ ECSPI3_CLK_ROOT = 131,
+ OLD_MIPI_DSI_ESC_RX_ROOT = 132,
+ DISPLAY_HDMI_CLK_ROOT = 133,
+ CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+ OSC_25M_CLK,
+ ARM_PLL_CLK,
+ DRAM_PLL1_CLK,
+ VIDEO_PLL2_CLK,
+ VPU_PLL_CLK,
+ GPU_PLL_CLK,
+ SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_266M_CLK,
+ SYSTEM_PLL1_200M_CLK,
+ SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK,
+ AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK,
+ OSC_32K_CLK,
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+ OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+ CCGR_DVFS = 0,
+ CCGR_ANAMIX = 1,
+ CCGR_CPU = 2,
+ CCGR_CSU = 4,
+ CCGR_DRAM1 = 5,
+ CCGR_DRAM2_OBSOLETE = 6,
+ CCGR_ECSPI1 = 7,
+ CCGR_ECSPI2 = 8,
+ CCGR_ECSPI3 = 9,
+ CCGR_ENET1 = 10,
+ CCGR_GPIO1 = 11,
+ CCGR_GPIO2 = 12,
+ CCGR_GPIO3 = 13,
+ CCGR_GPIO4 = 14,
+ CCGR_GPIO5 = 15,
+ CCGR_GPT1 = 16,
+ CCGR_GPT2 = 17,
+ CCGR_GPT3 = 18,
+ CCGR_GPT4 = 19,
+ CCGR_GPT5 = 20,
+ CCGR_GPT6 = 21,
+ CCGR_HS = 22,
+ CCGR_I2C1 = 23,
+ CCGR_I2C2 = 24,
+ CCGR_I2C3 = 25,
+ CCGR_I2C4 = 26,
+ CCGR_IOMUX = 27,
+ CCGR_IOMUX1 = 28,
+ CCGR_IOMUX2 = 29,
+ CCGR_IOMUX3 = 30,
+ CCGR_IOMUX4 = 31,
+ CCGR_M4 = 32,
+ CCGR_MU = 33,
+ CCGR_OCOTP = 34,
+ CCGR_OCRAM = 35,
+ CCGR_OCRAM_S = 36,
+ CCGR_PCIE = 37,
+ CCGR_PERFMON1 = 38,
+ CCGR_PERFMON2 = 39,
+ CCGR_PWM1 = 40,
+ CCGR_PWM2 = 41,
+ CCGR_PWM3 = 42,
+ CCGR_PWM4 = 43,
+ CCGR_QOS = 44,
+ CCGR_DISMIX = 45,
+ CCGR_MEGAMIX = 46,
+ CCGR_QSPI = 47,
+ CCGR_RAWNAND = 48,
+ CCGR_RDC = 49,
+ CCGR_ROM = 50,
+ CCGR_SAI1 = 51,
+ CCGR_SAI2 = 52,
+ CCGR_SAI3 = 53,
+ CCGR_SAI4 = 54,
+ CCGR_SAI5 = 55,
+ CCGR_SAI6 = 56,
+ CCGR_SCTR = 57,
+ CCGR_SDMA1 = 58,
+ CCGR_SDMA2 = 59,
+ CCGR_SEC_DEBUG = 60,
+ CCGR_SEMA1 = 61,
+ CCGR_SEMA2 = 62,
+ CCGR_SIM_DISPLAY = 63,
+ CCGR_SIM_ENET = 64,
+ CCGR_SIM_M = 65,
+ CCGR_SIM_MAIN = 66,
+ CCGR_SIM_S = 67,
+ CCGR_SIM_WAKEUP = 68,
+ CCGR_SIM_USB = 69,
+ CCGR_SIM_VPU = 70,
+ CCGR_SNVS = 71,
+ CCGR_TRACE = 72,
+ CCGR_UART1 = 73,
+ CCGR_UART2 = 74,
+ CCGR_UART3 = 75,
+ CCGR_UART4 = 76,
+ CCGR_USB_CTRL1 = 77,
+ CCGR_USB_CTRL2 = 78,
+ CCGR_USB_PHY1 = 79,
+ CCGR_USB_PHY2 = 80,
+ CCGR_USDHC1 = 81,
+ CCGR_USDHC2 = 82,
+ CCGR_WDOG1 = 83,
+ CCGR_WDOG2 = 84,
+ CCGR_WDOG3 = 85,
+ CCGR_VA53 = 86,
+ CCGR_GPU = 87,
+ CCGR_HEVC = 88,
+ CCGR_AVC = 89,
+ CCGR_VP9 = 90,
+ CCGR_HEVC_INTER = 91,
+ CCGR_GIC = 92,
+ CCGR_DISPLAY = 93,
+ CCGR_HDMI = 94,
+ CCGR_HDMI_PHY = 95,
+ CCGR_XTAL = 96,
+ CCGR_PLL = 97,
+ CCGR_TSENSOR = 98,
+ CCGR_VPU_DEC = 99,
+ CCGR_PCIE2 = 100,
+ CCGR_MIPI_CSI1 = 101,
+ CCGR_MIPI_CSI2 = 102,
+ CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+ CLK_SRC_CKIL_SYNC_REQ = 0,
+ CLK_SRC_ARM_PLL_EN = 1,
+ CLK_SRC_GPU_PLL_EN = 2,
+ CLK_SRC_VPU_PLL_EN = 3,
+ CLK_SRC_DRAM_PLL_EN = 4,
+ CLK_SRC_SYSTEM_PLL1_EN = 5,
+ CLK_SRC_SYSTEM_PLL2_EN = 6,
+ CLK_SRC_SYSTEM_PLL3_EN = 7,
+ CLK_SRC_AUDIO_PLL1_EN = 8,
+ CLK_SRC_AUDIO_PLL2_EN = 9,
+ CLK_SRC_VIDEO_PLL1_EN = 10,
+ CLK_SRC_VIDEO_PLL2_EN = 11,
+ CLK_SRC_ARM_PLL = 12,
+ CLK_SRC_GPU_PLL = 13,
+ CLK_SRC_VPU_PLL = 14,
+ CLK_SRC_DRAM_PLL = 15,
+ CLK_SRC_SYSTEM_PLL1_800M = 16,
+ CLK_SRC_SYSTEM_PLL1_400M = 17,
+ CLK_SRC_SYSTEM_PLL1_266M = 18,
+ CLK_SRC_SYSTEM_PLL1_200M = 19,
+ CLK_SRC_SYSTEM_PLL1_160M = 20,
+ CLK_SRC_SYSTEM_PLL1_133M = 21,
+ CLK_SRC_SYSTEM_PLL1_100M = 22,
+ CLK_SRC_SYSTEM_PLL1_80M = 23,
+ CLK_SRC_SYSTEM_PLL1_40M = 24,
+ CLK_SRC_SYSTEM_PLL2_1000M = 25,
+ CLK_SRC_SYSTEM_PLL2_500M = 26,
+ CLK_SRC_SYSTEM_PLL2_333M = 27,
+ CLK_SRC_SYSTEM_PLL2_250M = 28,
+ CLK_SRC_SYSTEM_PLL2_200M = 29,
+ CLK_SRC_SYSTEM_PLL2_166M = 30,
+ CLK_SRC_SYSTEM_PLL2_125M = 31,
+ CLK_SRC_SYSTEM_PLL2_100M = 32,
+ CLK_SRC_SYSTEM_PLL2_50M = 33,
+ CLK_SRC_SYSTEM_PLL3 = 34,
+ CLK_SRC_AUDIO_PLL1 = 35,
+ CLK_SRC_AUDIO_PLL2 = 36,
+ CLK_SRC_VIDEO_PLL1 = 37,
+ CLK_SRC_VIDEO_PLL2 = 38,
+ CLK_SRC_OSC_25M = 39,
+ CLK_SRC_OSC_27M = 40,
+};
+
+enum root_pre_div {
+ CLK_ROOT_PRE_DIV1 = 0,
+ CLK_ROOT_PRE_DIV2,
+ CLK_ROOT_PRE_DIV3,
+ CLK_ROOT_PRE_DIV4,
+ CLK_ROOT_PRE_DIV5,
+ CLK_ROOT_PRE_DIV6,
+ CLK_ROOT_PRE_DIV7,
+ CLK_ROOT_PRE_DIV8,
+};
+
+enum root_post_div {
+ CLK_ROOT_POST_DIV1 = 0,
+ CLK_ROOT_POST_DIV2,
+ CLK_ROOT_POST_DIV3,
+ CLK_ROOT_POST_DIV4,
+ CLK_ROOT_POST_DIV5,
+ CLK_ROOT_POST_DIV6,
+ CLK_ROOT_POST_DIV7,
+ CLK_ROOT_POST_DIV8,
+ CLK_ROOT_POST_DIV9,
+ CLK_ROOT_POST_DIV10,
+ CLK_ROOT_POST_DIV11,
+ CLK_ROOT_POST_DIV12,
+ CLK_ROOT_POST_DIV13,
+ CLK_ROOT_POST_DIV14,
+ CLK_ROOT_POST_DIV15,
+ CLK_ROOT_POST_DIV16,
+ CLK_ROOT_POST_DIV17,
+ CLK_ROOT_POST_DIV18,
+ CLK_ROOT_POST_DIV19,
+ CLK_ROOT_POST_DIV20,
+ CLK_ROOT_POST_DIV21,
+ CLK_ROOT_POST_DIV22,
+ CLK_ROOT_POST_DIV23,
+ CLK_ROOT_POST_DIV24,
+ CLK_ROOT_POST_DIV25,
+ CLK_ROOT_POST_DIV26,
+ CLK_ROOT_POST_DIV27,
+ CLK_ROOT_POST_DIV28,
+ CLK_ROOT_POST_DIV29,
+ CLK_ROOT_POST_DIV30,
+ CLK_ROOT_POST_DIV31,
+ CLK_ROOT_POST_DIV32,
+ CLK_ROOT_POST_DIV33,
+ CLK_ROOT_POST_DIV34,
+ CLK_ROOT_POST_DIV35,
+ CLK_ROOT_POST_DIV36,
+ CLK_ROOT_POST_DIV37,
+ CLK_ROOT_POST_DIV38,
+ CLK_ROOT_POST_DIV39,
+ CLK_ROOT_POST_DIV40,
+ CLK_ROOT_POST_DIV41,
+ CLK_ROOT_POST_DIV42,
+ CLK_ROOT_POST_DIV43,
+ CLK_ROOT_POST_DIV44,
+ CLK_ROOT_POST_DIV45,
+ CLK_ROOT_POST_DIV46,
+ CLK_ROOT_POST_DIV47,
+ CLK_ROOT_POST_DIV48,
+ CLK_ROOT_POST_DIV49,
+ CLK_ROOT_POST_DIV50,
+ CLK_ROOT_POST_DIV51,
+ CLK_ROOT_POST_DIV52,
+ CLK_ROOT_POST_DIV53,
+ CLK_ROOT_POST_DIV54,
+ CLK_ROOT_POST_DIV55,
+ CLK_ROOT_POST_DIV56,
+ CLK_ROOT_POST_DIV57,
+ CLK_ROOT_POST_DIV58,
+ CLK_ROOT_POST_DIV59,
+ CLK_ROOT_POST_DIV60,
+ CLK_ROOT_POST_DIV61,
+ CLK_ROOT_POST_DIV62,
+ CLK_ROOT_POST_DIV63,
+ CLK_ROOT_POST_DIV64,
+};
+
+struct clk_root_map {
+ enum clk_root_index entry;
+ enum clk_slice_type slice_type;
+ u32 slice_index;
+ u8 src_mux[8];
+};
+
+struct ccm_ccgr {
+ u32 ccgr;
+ u32 ccgr_set;
+ u32 ccgr_clr;
+ u32 ccgr_tog;
+};
+
+struct ccm_root {
+ u32 target_root;
+ u32 target_root_set;
+ u32 target_root_clr;
+ u32 target_root_tog;
+ u32 misc;
+ u32 misc_set;
+ u32 misc_clr;
+ u32 misc_tog;
+ u32 nm_post;
+ u32 nm_post_root_set;
+ u32 nm_post_root_clr;
+ u32 nm_post_root_tog;
+ u32 nm_pre;
+ u32 nm_pre_root_set;
+ u32 nm_pre_root_clr;
+ u32 nm_pre_root_tog;
+ u32 db_post;
+ u32 db_post_root_set;
+ u32 db_post_root_clr;
+ u32 db_post_root_tog;
+ u32 db_pre;
+ u32 db_pre_root_set;
+ u32 db_pre_root_clr;
+ u32 db_pre_root_tog;
+ u32 reserved[4];
+ u32 access_ctrl;
+ u32 access_ctrl_root_set;
+ u32 access_ctrl_root_clr;
+ u32 access_ctrl_root_tog;
+};
+
+struct ccm_reg {
+ u32 reserved_0[4096];
+ struct ccm_ccgr ccgr_array[192];
+ u32 reserved_1[3328];
+ struct ccm_root core_root[5];
+ u32 reserved_2[352];
+ struct ccm_root bus_root[12];
+ u32 reserved_3[128];
+ struct ccm_root ahb_ipg_root[4];
+ u32 reserved_4[384];
+ struct ccm_root dram_sel;
+ struct ccm_root core_sel;
+ u32 reserved_5[448];
+ struct ccm_root ip_root[78];
+};
+
+#define CCGR_CLK_ON_MASK 0x03
+#define CLK_SRC_ON_MASK 0x03
+
+#define CLK_ROOT_ON BIT(28)
+#define CLK_ROOT_OFF (0 << 28)
+#define CLK_ROOT_ENABLE_MASK BIT(28)
+#define CLK_ROOT_ENABLE_SHIFT 28
+#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
+
+/* For SEL, only use 1 bit */
+#define CLK_ROOT_SRC_MUX_MASK 0x07000000
+#define CLK_ROOT_SRC_MUX_SHIFT 24
+#define CLK_ROOT_SRC_0 0x00000000
+#define CLK_ROOT_SRC_1 0x01000000
+#define CLK_ROOT_SRC_2 0x02000000
+#define CLK_ROOT_SRC_3 0x03000000
+#define CLK_ROOT_SRC_4 0x04000000
+#define CLK_ROOT_SRC_5 0x05000000
+#define CLK_ROOT_SRC_6 0x06000000
+#define CLK_ROOT_SRC_7 0x07000000
+
+#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
+#define CLK_ROOT_PRE_DIV_SHIFT 16
+#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
+
+#define CLK_ROOT_AUDO_SLOW_EN 0x1000
+
+#define CLK_ROOT_AUDO_DIV_MASK 0x700
+#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
+#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
+
+/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
+#define CLK_ROOT_POST_DIV_MASK 0x3f
+#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
+#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
+#define CLK_ROOT_POST_DIV_SHIFT 0
+#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK BIT(31)
+#define FRAC_PLL_CLKE_MASK BIT(21)
+#define FRAC_PLL_PD_MASK BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
+#define FRAC_PLL_BYPASS_MASK BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
+#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK BIT(31)
+#define SSCG_PLL_CLKE_MASK BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
+#define SSCG_PLL_PD_MASK BIT(7)
+#define SSCG_PLL_BYPASS1_MASK BIT(5)
+#define SSCG_PLL_BYPASS2_MASK BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK 0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define SSCG_PLL_SSDS_MASK BIT(8)
+#define SSCG_PLL_SSMD_MASK (0x7 << 5)
+#define SSCG_PLL_SSMF_MASK (0xf << 1)
+#define SSCG_PLL_SSE_MASK 0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT 25
+#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT 19
+#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
+ SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK 0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
+#define HW_DIGPROG_MINOR_MASK 0xff
+
+#define HW_OSC_27M_CLKE_MASK BIT(4)
+#define HW_OSC_25M_CLKE_MASK BIT(2)
+#define HW_OSC_32K_SEL_MASK 0x1
+#define HW_OSC_32K_SEL_RTC 0x1
+#define HW_OSC_32K_SEL_25M_DIV800 0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
+#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
+#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
+#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
+
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
+#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
+
+enum enet_freq {
+ ENET_25MHZ = 0,
+ ENET_50MHZ,
+ ENET_125MHZ,
+};
+
+enum frac_pll_out_val {
+ FRAC_PLL_OUT_1000M,
+ FRAC_PLL_OUT_1600M,
+};
+
+u32 imx_get_fecclk(void);
+u32 imx_get_uartclk(void);
+int clock_init(void);
+void init_clk_usdhc(u32 index);
+void init_uart_clk(u32 index);
+void init_wdog_clk(void);
+unsigned int mxc_get_clock(enum clk_root_index clk);
+int clock_enable(enum clk_ccgr_index index, bool enable);
+int clock_root_enabled(enum clk_root_index clock_id);
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+ enum root_post_div post_div, enum clk_root_src clock_src);
+int clock_set_target_val(enum clk_root_index clock_id, u32 val);
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
+int clock_get_postdiv(enum clk_root_index clock_id,
+ enum root_post_div *post_div);
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
+int set_clk_qspi(void);
+void enable_ocotp_clk(unsigned char enable);
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+int set_clk_enet(enum enet_freq type);
+#endif
diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile
new file mode 100644
index 0000000000..05f38842f0
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clock.o clock_slice.o
diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/mx8m/clock.c
new file mode 100644
index 0000000000..b132d5ee45
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/clock.c
@@ -0,0 +1,788 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct anamix_pll *ana_pll = (struct anamix_pll *)ANA_PLL_BASE_ADDR;
+
+static u32 decode_frac_pll(enum clk_root_src frac_pll)
+{
+ u32 pll_cfg0, pll_cfg1, pllout;
+ u32 pll_refclk_sel, pll_refclk;
+ u32 divr_val, divq_val, divf_val, divff, divfi;
+ u32 pllout_div_shift, pllout_div_mask, pllout_div;
+
+ switch (frac_pll) {
+ case ARM_PLL_CLK:
+ pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
+ pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
+ pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
+ pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
+ break;
+ default:
+ printf("Not supported\n");
+ return 0;
+ }
+
+ pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
+ pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
+
+ /* Power down */
+ if (pll_cfg0 & FRAC_PLL_PD_MASK)
+ return 0;
+
+ /* output not enabled */
+ if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
+ return 0;
+
+ pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
+
+ if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
+ pll_refclk = 25000000u;
+ else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
+ pll_refclk = 27000000u;
+ else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
+ pll_refclk = 27000000u;
+ else
+ pll_refclk = 0;
+
+ if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
+ return pll_refclk;
+
+ divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
+ FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
+ divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
+
+ divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
+ FRAC_PLL_FRAC_DIV_CTL_SHIFT;
+ divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
+
+ divf_val = 1 + divfi + divff / (1 << 24);
+
+ pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
+ ((divq_val + 1) * 2);
+
+ return pllout / (pllout_div + 1);
+}
+
+static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
+{
+ u32 pll_cfg0, pll_cfg1, pll_cfg2;
+ u32 pll_refclk_sel, pll_refclk;
+ u32 divr1, divr2, divf1, divf2, divq, div;
+ u32 sse;
+ u32 pll_clke;
+ u32 pllout_div_shift, pllout_div_mask, pllout_div;
+ u32 pllout;
+
+ switch (sscg_pll) {
+ case SYSTEM_PLL1_800M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
+ pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
+ pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
+ pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
+ break;
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL2_50M_CLK:
+ pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
+ pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
+ pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
+ pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
+ break;
+ case SYSTEM_PLL3_CLK:
+ pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
+ pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
+ pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
+ pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
+ break;
+ case DRAM_PLL1_CLK:
+ pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
+ pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
+ pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
+ pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
+ break;
+ default:
+ printf("Not supported\n");
+ return 0;
+ }
+
+ switch (sscg_pll) {
+ case DRAM_PLL1_CLK:
+ pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
+ div = 1;
+ break;
+ case SYSTEM_PLL3_CLK:
+ pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
+ div = 1;
+ break;
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL1_800M_CLK:
+ pll_clke = SSCG_PLL_CLKE_MASK;
+ div = 1;
+ break;
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
+ div = 2;
+ break;
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
+ div = 3;
+ break;
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
+ div = 4;
+ break;
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
+ div = 5;
+ break;
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
+ div = 6;
+ break;
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
+ div = 8;
+ break;
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
+ div = 10;
+ break;
+ case SYSTEM_PLL2_50M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
+ div = 20;
+ break;
+ default:
+ printf("Not supported\n");
+ return 0;
+ }
+
+ /* Power down */
+ if (pll_cfg0 & SSCG_PLL_PD_MASK)
+ return 0;
+
+ /* output not enabled */
+ if ((pll_cfg0 & pll_clke) == 0)
+ return 0;
+
+ pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
+ pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
+
+ pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
+
+ if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
+ pll_refclk = 25000000u;
+ else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
+ pll_refclk = 27000000u;
+ else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
+ pll_refclk = 27000000u;
+ else
+ pll_refclk = 0;
+
+ /* We assume bypass1/2 are the same value */
+ if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
+ (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
+ return pll_refclk;
+
+ divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
+ SSCG_PLL_REF_DIVR1_SHIFT;
+ divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
+ SSCG_PLL_REF_DIVR2_SHIFT;
+ divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
+ SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
+ divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
+ SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
+ divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
+ SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
+ sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
+
+ if (sse)
+ sse = 8;
+ else
+ sse = 2;
+
+ pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
+ (divr2 + 1) * (divf2 + 1) / (divq + 1);
+
+ return pllout / (pllout_div + 1) / div;
+}
+
+static u32 get_root_src_clk(enum clk_root_src root_src)
+{
+ switch (root_src) {
+ case OSC_25M_CLK:
+ return 25000000u;
+ case OSC_27M_CLK:
+ return 25000000u;
+ case OSC_32K_CLK:
+ return 32000u;
+ case ARM_PLL_CLK:
+ return decode_frac_pll(root_src);
+ case SYSTEM_PLL1_800M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL2_50M_CLK:
+ case SYSTEM_PLL3_CLK:
+ return decode_sscg_pll(root_src);
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static u32 get_root_clk(enum clk_root_index clock_id)
+{
+ enum clk_root_src root_src;
+ u32 post_podf, pre_podf, root_src_clk;
+
+ if (clock_root_enabled(clock_id) <= 0)
+ return 0;
+
+ if (clock_get_prediv(clock_id, &pre_podf) < 0)
+ return 0;
+
+ if (clock_get_postdiv(clock_id, &post_podf) < 0)
+ return 0;
+
+ if (clock_get_src(clock_id, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ return root_src_clk / (post_podf + 1) / (pre_podf + 1);
+}
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ clock_enable(CCGR_OCOTP, !!enable);
+}
+#endif
+
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+ /* 0 - 3 is valid i2c num */
+ if (i2c_num > 3)
+ return -EINVAL;
+
+ clock_enable(CCGR_I2C1 + i2c_num, !!enable);
+
+ return 0;
+}
+
+unsigned int mxc_get_clock(enum clk_root_index clk)
+{
+ u32 val;
+
+ if (clk >= CLK_ROOT_MAX)
+ return 0;
+
+ if (clk == MXC_ARM_CLK)
+ return get_root_clk(ARM_A53_CLK_ROOT);
+
+ if (clk == MXC_IPG_CLK) {
+ clock_get_target_val(IPG_CLK_ROOT, &val);
+ val = val & 0x3;
+ return get_root_clk(AHB_CLK_ROOT) / (val + 1);
+ }
+
+ return get_root_clk(clk);
+}
+
+u32 imx_get_uartclk(void)
+{
+ return mxc_get_clock(UART1_CLK_ROOT);
+}
+
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
+{
+ /*
+ * LCDIF_PIXEL_CLK: select 800MHz root clock,
+ * select pre divider 8, output is 100 MHz
+ */
+ clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(4) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
+}
+
+void init_wdog_clk(void)
+{
+ clock_enable(CCGR_WDOG1, 0);
+ clock_enable(CCGR_WDOG2, 0);
+ clock_enable(CCGR_WDOG3, 0);
+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_WDOG1, 1);
+ clock_enable(CCGR_WDOG2, 1);
+ clock_enable(CCGR_WDOG3, 1);
+}
+
+void init_usb_clk(void)
+{
+ if (!is_usb_boot()) {
+ clock_enable(CCGR_USB_CTRL1, 0);
+ clock_enable(CCGR_USB_CTRL2, 0);
+ clock_enable(CCGR_USB_PHY1, 0);
+ clock_enable(CCGR_USB_PHY2, 0);
+ /* 500M */
+ clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ /* 100M */
+ clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ /* 100M */
+ clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_USB_CTRL1, 1);
+ clock_enable(CCGR_USB_CTRL2, 1);
+ clock_enable(CCGR_USB_PHY1, 1);
+ clock_enable(CCGR_USB_PHY2, 1);
+ }
+}
+
+void init_uart_clk(u32 index)
+{
+ /* Set uart clock root 25M OSC */
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_UART1, 0);
+ clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_UART2, 0);
+ clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART2, 1);
+ return;
+ case 2:
+ clock_enable(CCGR_UART3, 0);
+ clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART3, 1);
+ return;
+ case 3:
+ clock_enable(CCGR_UART4, 0);
+ clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART4, 1);
+ return;
+ default:
+ printf("Invalid uart index\n");
+ return;
+ }
+}
+
+void init_clk_usdhc(u32 index)
+{
+ /*
+ * set usdhc clock root
+ * sys pll1 400M
+ */
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_USDHC1, 0);
+ clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ clock_enable(CCGR_USDHC1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_USDHC2, 0);
+ clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ clock_enable(CCGR_USDHC2, 1);
+ return;
+ default:
+ printf("Invalid usdhc index\n");
+ return;
+ }
+}
+
+int set_clk_qspi(void)
+{
+ /*
+ * set qspi root
+ * sys pll1 100M
+ */
+ clock_enable(CCGR_QSPI, 0);
+ clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(7));
+ clock_enable(CCGR_QSPI, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ u32 enet1_ref;
+
+ switch (type) {
+ case ENET_125MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_SIM_ENET, 0);
+
+ /* set enet axi clock 266Mhz */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON |
+ ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+ /* enable clock */
+ clock_enable(CCGR_SIM_ENET, 1);
+ clock_enable(CCGR_ENET1, 1);
+
+ return 0;
+}
+#endif
+
+u32 imx_get_fecclk(void)
+{
+ return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(void)
+{
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
+ u32 pwdn_mask = 0;
+ u32 pll_clke = 0;
+ u32 bypass1 = 0;
+ u32 bypass2 = 0;
+
+ setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
+ setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
+
+ pwdn_mask = SSCG_PLL_PD_MASK;
+ pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
+ bypass1 = SSCG_PLL_BYPASS1_MASK;
+ bypass2 = SSCG_PLL_BYPASS2_MASK;
+
+ /* Enable DDR1 and DDR2 domain */
+ writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
+ writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
+
+ /* Clear power down bit */
+ clrbits_le32(pll_control_reg, pwdn_mask);
+ /* Eanble ARM_PLL/SYS_PLL */
+ setbits_le32(pll_control_reg, pll_clke);
+
+ /* Clear bypass */
+ clrbits_le32(pll_control_reg, bypass1);
+ __udelay(100);
+ clrbits_le32(pll_control_reg, bypass2);
+ /* Wait until lock */
+ while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
+ ;
+}
+
+int frac_pll_init(u32 pll, enum frac_pll_out_val val)
+{
+ void __iomem *pll_cfg0, __iomem *pll_cfg1;
+ u32 val_cfg0, val_cfg1;
+
+ switch (pll) {
+ case ANATOP_ARM_PLL:
+ pll_cfg0 = &ana_pll->arm_pll_cfg0;
+ pll_cfg1 = &ana_pll->arm_pll_cfg1;
+
+ if (val == FRAC_PLL_OUT_1000M)
+ val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
+ else
+ val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
+ val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
+ FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
+ FRAC_PLL_REFCLK_DIV_VAL(4) |
+ FRAC_PLL_OUTPUT_DIV_VAL(0);
+ break;
+ default:
+ return -1;
+ }
+
+ /* bypass the clock */
+ setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+ /* Set the value */
+ writel(val_cfg1, pll_cfg1);
+ writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
+ val_cfg0 = readl(pll_cfg0);
+ /* unbypass the clock */
+ clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+ while (!(readl(pll_cfg0) & FRAC_PLL_LOCK_MASK))
+ ;
+ clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
+
+ return 0;
+}
+
+int sscg_pll_init(u32 pll)
+{
+ void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
+ u32 val_cfg0, val_cfg1, val_cfg2;
+ u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
+
+ switch (pll) {
+ case ANATOP_SYSTEM_PLL1:
+ pll_cfg0 = &ana_pll->sys_pll1_cfg0;
+ pll_cfg1 = &ana_pll->sys_pll1_cfg1;
+ pll_cfg2 = &ana_pll->sys_pll1_cfg2;
+ /* 800MHz */
+ val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+ SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+ val_cfg1 = 0;
+ val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+ SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+ SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+ SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+ SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+ SSCG_PLL_REFCLK_SEL_OSC_25M;
+ break;
+ case ANATOP_SYSTEM_PLL2:
+ pll_cfg0 = &ana_pll->sys_pll2_cfg0;
+ pll_cfg1 = &ana_pll->sys_pll2_cfg1;
+ pll_cfg2 = &ana_pll->sys_pll2_cfg2;
+ /* 1000MHz */
+ val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+ SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
+ val_cfg1 = 0;
+ val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+ SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+ SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+ SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+ SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+ SSCG_PLL_REFCLK_SEL_OSC_25M;
+ break;
+ case ANATOP_SYSTEM_PLL3:
+ pll_cfg0 = &ana_pll->sys_pll3_cfg0;
+ pll_cfg1 = &ana_pll->sys_pll3_cfg1;
+ pll_cfg2 = &ana_pll->sys_pll3_cfg2;
+ /* 800MHz */
+ val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+ SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+ val_cfg1 = 0;
+ val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+ SSCG_PLL_REFCLK_SEL_OSC_25M;
+ break;
+ default:
+ return -1;
+ }
+
+ /*bypass*/
+ setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
+ /* set value */
+ writel(val_cfg2, pll_cfg2);
+ writel(val_cfg1, pll_cfg1);
+ /*unbypass1 and wait 70us */
+ writel(val_cfg0 | bypass2_mask, pll_cfg1);
+
+ __udelay(70);
+
+ /* unbypass2 and wait lock */
+ writel(val_cfg0, pll_cfg1);
+ while (!(readl(pll_cfg0) & SSCG_PLL_LOCK_MASK))
+ ;
+
+ return 0;
+}
+
+int clock_init(void)
+{
+ u32 grade;
+
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+
+ /*
+ * 8MQ only supports two grades: consumer and industrial.
+ * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
+ */
+ grade = get_cpu_temp_grade(NULL, NULL);
+ if (!grade) {
+ frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
+ } else {
+ frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ }
+ /*
+ * According to ANAMIX SPEC
+ * sys pll1 fixed at 800MHz
+ * sys pll2 fixed at 1GHz
+ * Here we only enable the outputs.
+ */
+ setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
+ SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
+ SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
+ SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
+ SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
+
+ setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
+ SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
+ SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
+ SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
+ SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
+
+ clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+
+ init_wdog_clk();
+ clock_enable(CCGR_TSENSOR, 1);
+
+ return 0;
+}
+#endif
+
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 freq;
+
+ freq = decode_frac_pll(ARM_PLL_CLK);
+ printf("ARM_PLL %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
+ printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
+ printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
+ printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
+ printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
+ printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
+ printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
+ printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
+ printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
+ printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
+ printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
+ printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
+ printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
+ printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
+ printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
+ printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
+ printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
+ printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
+ printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
+ printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(UART1_CLK_ROOT);
+ printf("UART1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(USDHC1_CLK_ROOT);
+ printf("USDHC1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(QSPI_CLK_ROOT);
+ printf("QSPI %8d MHz\n", freq / 1000000);
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
+ "display clocks",
+ ""
+);
+#endif
diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/mx8m/clock_slice.c
new file mode 100644
index 0000000000..e734498b94
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/clock_slice.c
@@ -0,0 +1,742 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+static struct clk_root_map root_array[] = {
+ {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+ {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+ },
+ {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
+ {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
+ {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
+ },
+ {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+ {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+ {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+ {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+ {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+ },
+ {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
+ {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
+ },
+ {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
+ {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+ {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+ {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+ {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ EXT_CLK_2, EXT_CLK_3}
+ },
+ {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+ {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+ {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+ {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
+ {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
+ {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+ {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
+ {}
+ },
+ {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+ {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
+ },
+ {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
+ {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
+ },
+ {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
+ {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
+ {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
+ {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+ },
+ {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
+ {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+ },
+ {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
+ {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+ },
+ {PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
+ {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+ },
+ {PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ SYSTEM_PLL1_400M_CLK}
+ },
+ {PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+ },
+ {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
+ {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+ {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+ AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
+ },
+ {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
+ },
+ {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
+ },
+ {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
+ {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+ OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
+ },
+ {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+ {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+ },
+ {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+ VIDEO_PLL_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+ {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+ },
+ {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+ {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+ SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+ },
+ {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+ {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+ {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+ {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+ {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+ {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+ {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+ {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+ AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+ },
+ {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
+ {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
+ {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
+ {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
+ {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+ {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+ {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+ EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
+ EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+ },
+ {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+ SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+ },
+ {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+ },
+ {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+ },
+ {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+ SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+ },
+ {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+ {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+ },
+ {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
+ {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
+ },
+ {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+ {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+ },
+ {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+ {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
+ SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+ SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+ },
+ {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+ },
+ {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+ {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+ {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+ {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
+ {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+ {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
+ {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+ {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+ },
+ {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+ },
+ {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
+ {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+ },
+ {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
+ },
+ {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+ },
+ {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+ {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+ },
+ {OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
+ {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+ },
+ {DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
+ {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
+ VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+ },
+ {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
+ {DRAM_PLL1_CLK}
+ },
+ {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+ {DRAM_PLL1_CLK}
+ },
+};
+
+static int select(enum clk_root_index clock_id)
+{
+ int i, size;
+ struct clk_root_map *p = root_array;
+
+ size = ARRAY_SIZE(root_array);
+
+ for (i = 0; i < size; i++, p++) {
+ if (clock_id == p->entry)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
+ u32 slice_index)
+{
+ void __iomem *clk_root_target;
+
+ switch (slice_type) {
+ case CORE_CLOCK_SLICE:
+ clk_root_target =
+ (void __iomem *)&ccm_reg->core_root[slice_index];
+ break;
+ case BUS_CLOCK_SLICE:
+ clk_root_target =
+ (void __iomem *)&ccm_reg->bus_root[slice_index];
+ break;
+ case IP_CLOCK_SLICE:
+ clk_root_target =
+ (void __iomem *)&ccm_reg->ip_root[slice_index];
+ break;
+ case AHB_CLOCK_SLICE:
+ clk_root_target =
+ (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
+ break;
+ case IPG_CLOCK_SLICE:
+ clk_root_target =
+ (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
+ break;
+ case CORE_SEL_CLOCK_SLICE:
+ clk_root_target = (void __iomem *)&ccm_reg->core_sel;
+ break;
+ case DRAM_SEL_CLOCK_SLICE:
+ clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
+ break;
+ default:
+ return NULL;
+ }
+
+ return clk_root_target;
+}
+
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
+{
+ int root_entry;
+ struct clk_root_map *p;
+ void __iomem *clk_root_target;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+ clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+ if (!clk_root_target)
+ return -EINVAL;
+
+ *val = readl(clk_root_target);
+
+ return 0;
+}
+
+int clock_set_target_val(enum clk_root_index clock_id, u32 val)
+{
+ int root_entry;
+ struct clk_root_map *p;
+ void __iomem *clk_root_target;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+ clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+ if (!clk_root_target)
+ return -EINVAL;
+
+ writel(val, clk_root_target);
+
+ return 0;
+}
+
+int clock_root_enabled(enum clk_root_index clock_id)
+{
+ void __iomem *clk_root_target;
+ u32 slice_index, slice_type;
+ u32 val;
+ int root_entry;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ slice_type = root_array[root_entry].slice_type;
+ slice_index = root_array[root_entry].slice_index;
+
+ if ((slice_type == IPG_CLOCK_SLICE) ||
+ (slice_type == DRAM_SEL_CLOCK_SLICE) ||
+ (slice_type == CORE_SEL_CLOCK_SLICE)) {
+ /*
+ * Not supported, from CCM doc
+ * TODO
+ */
+ return 0;
+ }
+
+ clk_root_target = get_clk_root_target(slice_type, slice_index);
+ if (!clk_root_target)
+ return -EINVAL;
+
+ val = readl(clk_root_target);
+
+ return (val & CLK_ROOT_ON) ? 1 : 0;
+}
+
+/* CCGR CLK gate operation */
+int clock_enable(enum clk_ccgr_index index, bool enable)
+{
+ void __iomem *ccgr;
+
+ if (index >= CCGR_MAX)
+ return -EINVAL;
+
+ if (enable)
+ ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
+ else
+ ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
+
+ writel(CCGR_CLK_ON_MASK, ccgr);
+
+ return 0;
+}
+
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+ void __iomem *clk_root_target;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->slice_type == CORE_CLOCK_SLICE) ||
+ (p->slice_type == IPG_CLOCK_SLICE) ||
+ (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
+ (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
+ *pre_div = 0;
+ return 0;
+ }
+
+ clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+ if (!clk_root_target)
+ return -EINVAL;
+
+ val = readl(clk_root_target);
+ val &= CLK_ROOT_PRE_DIV_MASK;
+ val >>= CLK_ROOT_PRE_DIV_SHIFT;
+
+ *pre_div = val;
+
+ return 0;
+}
+
+int clock_get_postdiv(enum clk_root_index clock_id,
+ enum root_post_div *post_div)
+{
+ u32 val, mask;
+ int root_entry;
+ struct clk_root_map *p;
+ void __iomem *clk_root_target;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
+ (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
+ *post_div = 0;
+ return 0;
+ }
+
+ clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+ if (!clk_root_target)
+ return -EINVAL;
+
+ if (p->slice_type == IPG_CLOCK_SLICE)
+ mask = CLK_ROOT_IPG_POST_DIV_MASK;
+ else if (p->slice_type == CORE_CLOCK_SLICE)
+ mask = CLK_ROOT_CORE_POST_DIV_MASK;
+ else
+ mask = CLK_ROOT_POST_DIV_MASK;
+
+ val = readl(clk_root_target);
+ val &= mask;
+ val >>= CLK_ROOT_POST_DIV_SHIFT;
+
+ *post_div = val;
+
+ return 0;
+}
+
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+ void __iomem *clk_root_target;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+ if (!clk_root_target)
+ return -EINVAL;
+
+ val = readl(clk_root_target);
+ val &= CLK_ROOT_SRC_MUX_MASK;
+ val >>= CLK_ROOT_SRC_MUX_SHIFT;
+
+ *p_clock_src = p->src_mux[val];
+
+ return 0;
+}
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 05/23] imx: add sip function
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (3 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 04/23] imx: mx8m: add clock driver Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:35 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 06/23] imx: boot_mode: add USB_BOOT entry Peng Fan
` (17 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add SiP (Silicon Provider) services function to issue
SMC call to Arm Trusted Firmware.
More SiP information could be found in
https://github.com/ARM-software/arm-trusted-firmware/blob/master/
docs/arm-sip-service.rst
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/sys_proto.h | 3 +++
arch/arm/mach-imx/Makefile | 2 ++
arch/arm/mach-imx/sip.c | 23 +++++++++++++++++++++++
include/imx_sip.h | 14 ++++++++++++++
4 files changed, 42 insertions(+)
create mode 100644 arch/arm/mach-imx/sip.c
create mode 100644 include/imx_sip.h
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index a80a392a73..2d8afed406 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -122,4 +122,7 @@ void lcdif_power_down(void);
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+ unsigned long reg1, unsigned long reg2);
#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d77c10e176..c807174363 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -121,6 +121,8 @@ spl/u-boot-nand-spl.imx: SPL FORCE
targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
+obj-$(CONFIG_ARM64) += sip.o
+
obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c
new file mode 100644
index 0000000000..b724330d35
--- /dev/null
+++ b/arch/arm/mach-imx/sip.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+ unsigned long reg1, unsigned long reg2)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = id;
+ regs.regs[1] = reg0;
+ regs.regs[2] = reg1;
+ regs.regs[3] = reg2;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
diff --git a/include/imx_sip.h b/include/imx_sip.h
new file mode 100644
index 0000000000..48ab878749
--- /dev/null
+++ b/include/imx_sip.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IMX_SIP_H__
+#define _IMX_SIP_H_
+
+#define IMX_SIP_SRC 0xC2000005
+#define IMX_SIP_SRC_M4_START 0x00
+#define IMX_SIP_SRC_M4_STARTED 0x01
+
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 06/23] imx: boot_mode: add USB_BOOT entry
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (4 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 05/23] imx: add sip function Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:35 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h Peng Fan
` (16 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add USB_BOOT entry.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h
index a8239f2f7a..e3ed046b25 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -26,6 +26,7 @@ enum boot_device {
MMC4_BOOT,
NAND_BOOT,
QSPI_BOOT,
+ USB_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
};
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (5 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 06/23] imx: boot_mode: add USB_BOOT entry Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:35 ` Fabio Estevam
2017-12-17 10:32 ` Stefano Babic
2017-12-04 4:31 ` [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M Peng Fan
` (15 subsequent siblings)
22 siblings, 2 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Include dm/ofnode.h.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
---
include/power/pmic.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/power/pmic.h b/include/power/pmic.h
index 4b34316427..f2fe537fb7 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -11,6 +11,7 @@
#ifndef __CORE_PMIC_H_
#define __CORE_PMIC_H_
+#include <dm/ofnode.h>
#include <i2c.h>
#include <linux/list.h>
#include <power/power_chrg.h>
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (6 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-07 8:40 ` Stefano Babic
2017-12-16 17:36 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 09/23] imx: spl: implement spl_boot_device for i.MX8M Peng Fan
` (14 subsequent siblings)
22 siblings, 2 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Update get_reset_cause to reflect i.MX8M
Compile out get_ahb_clk and set_chipselect_size for i.MX8M
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/cpu.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 18205dc984..c811252733 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -62,6 +62,11 @@ static char *get_reset_cause(void)
return "WDOG4";
case 0x00200:
return "TEMPSENSE";
+#elif defined(CONFIG_MX8M)
+ case 0x00100:
+ return "WDOG2";
+ case 0x00200:
+ return "TEMPSENSE";
#else
case 0x00100:
return "TEMPSENSE";
@@ -137,6 +142,8 @@ unsigned imx_ddr_size(void)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_MX8MQ:
+ return "8MQ"; /* Quad-core version of the mx8m */
case MXC_CPU_MX7S:
return "7S"; /* Single-core version of the mx7 */
case MXC_CPU_MX7D:
@@ -259,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
-#ifndef CONFIG_MX7
+#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -293,6 +300,7 @@ void arch_preboot_os(void)
#endif
}
+#ifndef CONFIG_MX8M
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
@@ -323,3 +331,4 @@ void set_chipselect_size(int const cs_size)
writel(reg, &iomuxc_regs->gpr[1]);
}
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 09/23] imx: spl: implement spl_boot_device for i.MX8M
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (7 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:36 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 10/23] imx: add i.MX8MQ SoC Revision and is_mx8m helper Peng Fan
` (13 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Implement spl_boot_device for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/spl.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index d0d1b73aa6..58ec202d4f 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -97,8 +97,8 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
-#elif defined(CONFIG_MX7)
-/* Translate iMX7 boot device to the SPL boot device enumeration */
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
u32 spl_boot_device(void)
{
enum boot_device boot_device_spl = get_boot_device();
@@ -112,11 +112,15 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_MMC2;
case SPI_NOR_BOOT:
return BOOT_DEVICE_SPI;
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
+ case USB_BOOT:
+ return BOOT_DEVICE_USB;
default:
return BOOT_DEVICE_NONE;
}
}
-#endif /* CONFIG_MX6 || CONFIG_MX7 */
+#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 10/23] imx: add i.MX8MQ SoC Revision and is_mx8m helper
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (8 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 09/23] imx: spl: implement spl_boot_device for i.MX8M Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:37 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 11/23] imx: add pad settings bit definition for i.MX8M Peng Fan
` (12 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add i.MX8MQ SoC Revision
Add is_mx8m helper
The 7ULP is a dummy number, so use 0xEx.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx/cpu.h | 6 ++++--
arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index ec5b419e47..470961c6f7 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -25,12 +25,14 @@
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
-#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */
+#define MXC_CPU_MX8MQ 0x82
+#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
-#define MXC_SOC_MX7ULP 0x80 /* dummy */
+#define MXC_SOC_MX8M 0x80
+#define MXC_SOC_MX7ULP 0xE0 /* dummy */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 2d8afed406..5e9218ffc7 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -27,6 +27,7 @@
#define is_mx6() (is_soc_type(MXC_SOC_MX6))
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 11/23] imx: add pad settings bit definition for i.MX8M
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (9 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 10/23] imx: add i.MX8MQ SoC Revision and is_mx8m helper Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:38 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 12/23] imx: mx8m: add soc related settings and files Peng Fan
` (11 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add pad settings bit definition for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/iomux-v3.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index ad35e0109e..ade2105cca 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -87,7 +87,27 @@ typedef u64 iomux_v3_cfg_t;
#define IOMUX_CONFIG_LPSR 0x20
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
-#ifdef CONFIG_MX7
+#ifdef CONFIG_MX8M
+#define PAD_CTL_DSE0 (0x0 << 0)
+#define PAD_CTL_DSE1 (0x1 << 0)
+#define PAD_CTL_DSE2 (0x2 << 0)
+#define PAD_CTL_DSE3 (0x3 << 0)
+#define PAD_CTL_DSE4 (0x4 << 0)
+#define PAD_CTL_DSE5 (0x5 << 0)
+#define PAD_CTL_DSE6 (0x6 << 0)
+#define PAD_CTL_DSE7 (0x7 << 0)
+
+#define PAD_CTL_FSEL0 (0x0 << 3)
+#define PAD_CTL_FSEL1 (0x1 << 3)
+#define PAD_CTL_FSEL2 (0x2 << 3)
+#define PAD_CTL_FSEL3 (0x3 << 3)
+
+#define PAD_CTL_ODE (0x1 << 5)
+#define PAD_CTL_PUE (0x1 << 6)
+#define PAD_CTL_HYS (0x1 << 7)
+#define PAD_CTL_LVTTL (0x1 << 8)
+
+#elif defined CONFIG_MX7
#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 12/23] imx: mx8m: add soc related settings and files
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (10 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 11/23] imx: add pad settings bit definition for i.MX8M Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-07 8:39 ` Stefano Babic
2017-12-04 4:31 ` [U-Boot] [PATCH V2 13/23] imx: makefile: compile files for i.MX8M Peng Fan
` (10 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add SoC level initialization code
- arch_cpu_init
- mmu table
- detect cpu revision
- reset cpu and wdog settings
- M4 boot
- timer init
- wdog settings
- lowlevel init to save/restore registers
- a few dummy header file to avoid build failure
- ft_system_setup and ft_add_optee_node
- mmc env related
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-mx8m/crm_regs.h | 10 +
arch/arm/include/asm/arch-mx8m/gpio.h | 12 +
arch/arm/include/asm/arch-mx8m/sys_proto.h | 18 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/mx8m/Makefile | 3 +-
arch/arm/mach-imx/mx8m/lowlevel_init.S | 63 ++++
arch/arm/mach-imx/mx8m/soc.c | 539 +++++++++++++++++++++++++++++
7 files changed, 645 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-mx8m/crm_regs.h
create mode 100644 arch/arm/include/asm/arch-mx8m/gpio.h
create mode 100644 arch/arm/include/asm/arch-mx8m/sys_proto.h
create mode 100644 arch/arm/mach-imx/mx8m/lowlevel_init.S
create mode 100644 arch/arm/mach-imx/mx8m/soc.c
diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-mx8m/crm_regs.h
new file mode 100644
index 0000000000..6582318983
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/crm_regs.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
+#define _ASM_ARCH_MX8M_CRM_REGS_H
+/* Dummy header, some imx-common code needs this file */
+#endif
diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-mx8m/gpio.h
new file mode 100644
index 0000000000..b666d37700
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/gpio.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_GPIO_H
+#define __ASM_ARCH_MX8M_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-mx8m/sys_proto.h
new file mode 100644
index 0000000000..8bf9ac6697
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/sys_proto.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_MX8M_SYS_PROTO_H
+#define __ARCH_MX8M_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+void set_wdog_reset(struct wdog_regs *wdog);
+void enable_tzc380(void);
+void restore_boot_params(void);
+extern unsigned long rom_pointer[];
+enum boot_device get_boot_device(void);
+bool is_usb_boot(void);
+#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c807174363..27c154b8b3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -127,4 +127,5 @@ obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
+obj-$(CONFIG_MX8M) += mx8m/
diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile
index 05f38842f0..b1c5d74aab 100644
--- a/arch/arm/mach-imx/mx8m/Makefile
+++ b/arch/arm/mach-imx/mx8m/Makefile
@@ -4,4 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock.o clock_slice.o
+obj-y += lowlevel_init.o
+obj-y += clock.o clock_slice.o soc.o
diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/mx8m/lowlevel_init.S
new file mode 100644
index 0000000000..d388f3ba95
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/lowlevel_init.S
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+ .space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+ adr x0, rom_pointer
+ stp x1, x2, [x0], #16
+ stp x3, x4, [x0], #16
+ stp x5, x6, [x0], #16
+ stp x7, x8, [x0], #16
+ stp x9, x10, [x0], #16
+ stp x11, x12, [x0], #16
+ stp x13, x14, [x0], #16
+ stp x15, x16, [x0], #16
+ stp x17, x18, [x0], #16
+ stp x19, x20, [x0], #16
+ stp x21, x22, [x0], #16
+ stp x23, x24, [x0], #16
+ stp x25, x26, [x0], #16
+ stp x27, x28, [x0], #16
+ stp x29, x30, [x0], #16
+ mov x30, sp
+ str x30, [x0], #8
+
+ /* Returns */
+ b save_boot_params_ret
+
+.global restore_boot_params
+restore_boot_params:
+ adr x0, rom_pointer
+ ldp x1, x2, [x0], #16
+ ldp x3, x4, [x0], #16
+ ldp x5, x6, [x0], #16
+ ldp x7, x8, [x0], #16
+ ldp x9, x10, [x0], #16
+ ldp x11, x12, [x0], #16
+ ldp x13, x14, [x0], #16
+ ldp x15, x16, [x0], #16
+ ldp x17, x18, [x0], #16
+ ldp x19, x20, [x0], #16
+ ldp x21, x22, [x0], #16
+ ldp x23, x24, [x0], #16
+ ldp x25, x26, [x0], #16
+ ldp x27, x28, [x0], #16
+ ldp x29, x30, [x0], #16
+ ldr x0, [x0]
+ mov sp, x0
+ ret
diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/mx8m/soc.c
new file mode 100644
index 0000000000..740e84caa4
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/soc.c
@@ -0,0 +1,539 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/armv8/mmu.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <fsl_wdog.h>
+#include <imx_sip.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+ .bank = 1,
+ .word = 3,
+};
+#endif
+
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT 8
+#define OCOTP_TESTER3_SPEED_800MHZ 0
+#define OCOTP_TESTER3_SPEED_1GHZ 1
+#define OCOTP_TESTER3_SPEED_1300MHZ 2
+#define OCOTP_TESTER3_SPEED_1500MHZ 3
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ u32 val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_SPEED_SHIFT;
+ val &= 0x3;
+
+ switch (val) {
+ case OCOTP_TESTER3_SPEED_800MHZ:
+ return 800000000;
+ case OCOTP_TESTER3_SPEED_1GHZ:
+ return 1000000000;
+ case OCOTP_TESTER3_SPEED_1300MHZ:
+ return 1300000000;
+ case OCOTP_TESTER3_SPEED_1500MHZ:
+ return 1500000000;
+ }
+ return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT 6
+
+/* CPU Temperature Grades */
+#define TEMP_COMMERCIAL 0
+#define TEMP_EXTCOMMERCIAL 1
+#define TEMP_INDUSTRIAL 2
+#define TEMP_AUTOMOTIVE 3
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ u32 val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ unsigned long freq = readl(&sctr->cntfid0);
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+ clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+void enable_tzc380(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Enable TZASC and lock setting */
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
+}
+
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+ /*
+ * Output WDOG_B signal to reset external pmic or POR_B decided by
+ * the board desgin. Without external reset, the peripherals/DDR/
+ * PMIC are not reset, that may cause system working abnormal.
+ * WDZST bit is write-once only bit. Align this bit in kernel,
+ * otherwise kernel code will have no chance to set this bit.
+ */
+ setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
+}
+
+static struct mm_region imx8m_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x100000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ .virt = 0x100000UL,
+ .phys = 0x100000UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x7C0000UL,
+ .phys = 0x7C0000UL,
+ .size = 0x80000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x900000UL,
+ .phys = 0x900000UL,
+ .size = 0x200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ .virt = 0xB00000UL,
+ .phys = 0xB00000UL,
+ .size = 0x3f500000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0xC0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0x040000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = imx8m_mem_map;
+
+u32 get_cpu_rev(void)
+{
+ struct anamix_pll *ana_pll = (struct anamix_pll *)ANA_PLL_BASE_ADDR;
+ u32 reg = readl(&ana_pll->digprog);
+ u32 type = (reg >> 16) & 0xff;
+ u32 rom_version;
+
+ reg &= 0xff;
+
+ if (reg == 0x10) {
+ /*
+ * For B0 chip, the DIGPROG is not updated, still TO1.0.
+ * we have to check ROM version further
+ */
+ rom_version = readl((void __iomem *)0x800);
+ if (rom_version != 0x10) {
+ rom_version = readl((void __iomem *)0x83c);
+ if (rom_version >= 0x20)
+ reg = 0x20;
+ }
+ }
+
+ return (type << 12) | reg;
+}
+
+static void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+ struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+ writew(enable, &wdog3->wmcr);
+}
+
+int arch_cpu_init(void)
+{
+ /*
+ * Init timer at very early state, because sscg pll setting
+ * will use it
+ */
+ timer_init();
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ clock_init();
+ imx_set_wdog_powerdown(false);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[9];
+ struct fuse_bank9_regs *fuse =
+ (struct fuse_bank9_regs *)bank->fuse_regs;
+ u32 value = readl(&fuse->mac_addr1);
+
+ mac[0] = (value >> 8);
+ mac[1] = value;
+
+ value = readl(&fuse->mac_addr0);
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
+}
+#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+ u32 stack, pc;
+
+ if (!boot_private_data)
+ return -EINVAL;
+
+ stack = *(u32 *)boot_private_data;
+ pc = *(u32 *)(boot_private_data + 4);
+
+ /* Set the stack and pc to M4 bootROM */
+ writel(stack, M4_BOOTROM_BASE_ADDR);
+ writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+ /* Enable M4 */
+ call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
+
+ return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
+}
+#endif
+
+enum boot_device get_boot_device(void)
+{
+ struct bootrom_sw_info **p =
+ is_soc_rev(CHIP_REV_1_0) ?
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+
+ enum boot_device boot_dev = SD1_BOOT;
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 boot_instance = (*p)->boot_dev_instance;
+
+ switch (boot_type) {
+ case BOOT_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BOOT_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BOOT_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BOOT_TYPE_QSPI:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BOOT_TYPE_WEIM:
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case BOOT_TYPE_SPINOR:
+ boot_dev = SPI_NOR_BOOT;
+ break;
+ case BOOT_TYPE_USB:
+ boot_dev = USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+
+bool is_usb_boot(void)
+{
+ return get_boot_device() == USB_BOOT;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ struct bootrom_sw_info **p =
+ is_soc_rev(CHIP_REV_1_0) ?
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+ int devno = (*p)->boot_dev_instance;
+ u8 boot_type = (*p)->boot_dev_type;
+
+ /* If not boot from sd/mmc, use default value */
+ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ return board_mmc_get_env_dev(devno);
+}
+#endif
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+static int ft_add_optee_node(void *fdt, bd_t *bd)
+{
+ const char *path, *subpath;
+ int offs;
+
+ /*
+ * No TEE space allocated indicating no TEE running, so no
+ * need to add optee node in dts
+ */
+ if (!rom_pointer[1])
+ return 0;
+
+ offs = fdt_increase_size(fdt, 512);
+ if (offs) {
+ printf("No Space for dtb\n");
+ return offs;
+ }
+
+ path = "/firmware";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ path = "/";
+ offs = fdt_path_offset(fdt, path);
+
+ if (offs < 0) {
+ printf("Could not find root node.\n");
+ return offs;
+ }
+
+ subpath = "firmware";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return offs;
+ }
+ }
+
+ subpath = "optee";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return offs;
+ }
+
+ fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
+ fdt_setprop_string(fdt, offs, "method", "smc");
+
+ return 0;
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+ static const char * const status = "disabled";
+ static const char * const usb_dwc3_path = "/usb at 38100000/dwc3";
+ static const char * const speed = "high-speed";
+ int i = 0;
+ int rc;
+ int nodeoff;
+
+ if (get_boot_device() == USB_BOOT) {
+ static const char * const nodes_path[] = {
+ "/dcss at 32e00000",
+ "/hdmi at 32c00000",
+ "/hdmi_cec at 32c33800",
+ "/hdmi_drm@32c00000",
+ "/display-subsystem",
+ "/sound-hdmi"
+ };
+
+ for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
+ nodeoff = fdt_path_offset(blob, nodes_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ printf("Found %s node\n", nodes_path[i]);
+
+add_status:
+ rc = fdt_setprop(blob, nodeoff, "status", status,
+ strlen(status) + 1);
+ if (rc) {
+ if (rc == -FDT_ERR_NOSPACE) {
+ rc = fdt_increase_size(blob, 512);
+ if (!rc)
+ goto add_status;
+ }
+ printf("Unable to update property %s:%s, err=%s\n",
+ nodes_path[i], "status",
+ fdt_strerror(rc));
+ return rc;
+ }
+
+ printf("Modify %s:%s disabled\n",
+ nodes_path[i], "status");
+ }
+
+ nodeoff = fdt_path_offset(blob, usb_dwc3_path);
+ if (nodeoff >= 0) {
+ printf("Found %s node\n", usb_dwc3_path);
+
+usb_modify_speed:
+
+ rc = fdt_setprop(blob, nodeoff, "maximum-speed",
+ speed, strlen(speed) + 1);
+ if (rc) {
+ if (rc == -FDT_ERR_NOSPACE) {
+ rc = fdt_increase_size(blob, 512);
+ if (!rc)
+ goto usb_modify_speed;
+ }
+ printf("Unable to set property %s:%s, err=%s\n",
+ usb_dwc3_path, "maximum-speed",
+ fdt_strerror(rc));
+ return rc;
+ }
+
+ printf("Modify %s:%s = %s\n",
+ usb_dwc3_path, "maximum-speed", speed);
+ } else {
+ printf("Can't found %s node\n", usb_dwc3_path);
+ }
+ }
+
+ /* Disable the CPU idle for A0 chip since the HW does not support it */
+ if (is_soc_rev(CHIP_REV_1_0)) {
+ static const char * const nodes_path[] = {
+ "/cpus/cpu at 0",
+ "/cpus/cpu at 1",
+ "/cpus/cpu at 2",
+ "/cpus/cpu at 3",
+ };
+
+ for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
+ nodeoff = fdt_path_offset(blob, nodes_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ printf("Found %s node\n", nodes_path[i]);
+
+ rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
+ if (rc) {
+ printf("Unable to update property %s:%s, err=%s\n",
+ nodes_path[i], "status", fdt_strerror(rc));
+ return rc;
+ }
+
+ printf("Remove %s:%s\n", nodes_path[i],
+ "cpu-idle-states");
+ }
+ }
+
+ return ft_add_optee_node(blob, bd);
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ /* Clear WDA to trigger WDOG_B immediately */
+ writew((WCR_WDE | WCR_SRS), &wdog->wcr);
+
+ while (1) {
+ /*
+ * spin for .5 seconds before reset
+ */
+ }
+}
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 13/23] imx: makefile: compile files for i.MX8M
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (11 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 12/23] imx: mx8m: add soc related settings and files Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:39 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support Peng Fan
` (9 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Compile files for i.MX8M
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/Makefile | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 27c154b8b3..de91c137a9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -7,14 +7,21 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
obj-y = iomux-v3.o
endif
+
+ifeq ($(SOC),$(filter $(SOC),mx8m))
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-y += cpu.o
+endif
+
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += timer.o cpu.o speed.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (12 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 13/23] imx: makefile: compile files for i.MX8M Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:40 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M Peng Fan
` (8 subsequent siblings)
22 siblings, 2 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
i.MX8M OCOTP follow same flow as i.MX6Q, but it has 64 banks
and each bank 4 words.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/misc/mxc_ocotp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 8986bb4ad0..0cf24a4c88 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -35,6 +35,8 @@
#define BM_OUT_STATUS_DED 0x00000400
#define BM_OUT_STATUS_LOCKED 0x00000800
#define BM_OUT_STATUS_PROGFAIL 0x00001000
+#elif defined(CONFIG_MX8M)
+#define BM_CTRL_ADDR 0x000000ff
#else
#define BM_CTRL_ADDR 0x0000007f
#endif
@@ -79,6 +81,9 @@
#elif defined(CONFIG_MX7ULP)
#define FUSE_BANK_SIZE 0x80
#define FUSE_BANKS 31
+#elif defined(CONFIG_MX8M)
+#define FUSE_BANK_SIZE 0x40
+#define FUSE_BANKS 64
#else
#error "Unsupported architecture\n"
#endif
@@ -294,6 +299,8 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
#ifdef CONFIG_MX7
u32 addr = bank;
+#elif defined CONFIG_MX8M
+ u32 addr = bank << 2 | word;
#else
u32 addr;
/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (13 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:40 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M Peng Fan
` (7 subsequent siblings)
22 siblings, 2 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Support i.MX8M in fsl esdhc driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mmc/fsl_esdhc.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 499d622c6d..3a56f7c2bc 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -228,7 +228,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
dma_addr_t addr;
#endif
uint wml_value;
@@ -241,7 +242,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -270,7 +272,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -335,7 +338,8 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (14 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:41 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 17/23] gpio: mxc: add i.MX8M support Peng Fan
` (6 subsequent siblings)
22 siblings, 2 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Include i.MX8M in lcdif register layout map.
Also included i.MX7ULP in this patch, since share same with i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/regs-lcdif.h | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index 4de401bd22..57e6357608 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -20,7 +20,9 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6SLL) || defined(CONFIG_MX7ULP) || \
+ defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -56,7 +58,9 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6SLL) || defined(CONFIG_MX7ULP) || \
+ defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -65,7 +69,8 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+ defined(CONFIG_MX7ULP) || defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 17/23] gpio: mxc: add i.MX8M support
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (15 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:41 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M Peng Fan
` (5 subsequent siblings)
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add i.MX8M GPIO support.
There are 4 GPIO banks on i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/gpio/mxc_gpio.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index c480eba940..1e9188af63 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -41,13 +41,13 @@ static unsigned long gpio_ports[] = {
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX7)
+ defined(CONFIG_MX7) || defined(CONFIG_MX8M)
[3] = GPIO4_BASE_ADDR,
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX7)
+ defined(CONFIG_MX7) || defined(CONFIG_MX8M)
[4] = GPIO5_BASE_ADDR,
-#ifndef CONFIG_MX6UL
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX8M))
[5] = GPIO6_BASE_ADDR,
#endif
#endif
@@ -349,13 +349,17 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
- defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX8M)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX8M)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
+#ifndef CONFIG_MX8M
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
#endif
+#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
#endif
@@ -366,13 +370,17 @@ U_BOOT_DEVICES(mxc_gpios) = {
{ "gpio_mxc", &mxc_plat[1] },
{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
- defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX8M)
{ "gpio_mxc", &mxc_plat[3] },
#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX8M)
{ "gpio_mxc", &mxc_plat[4] },
+#ifndef CONFIG_MX8M
{ "gpio_mxc", &mxc_plat[5] },
#endif
+#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
{ "gpio_mxc", &mxc_plat[6] },
#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (16 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 17/23] gpio: mxc: add i.MX8M support Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
[not found] ` <CANr=Z=Z6ekzYT3+YG7nXWKedQc_3tS42_BAbkqnP8A8Qpij5Pg@mail.gmail.com>
` (2 more replies)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support Peng Fan
` (4 subsequent siblings)
22 siblings, 3 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
The MIB RAM and FIFO receive start register does not exist on
i.MX8M. Accessing these register will cause system hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
---
drivers/net/fec_mxc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 433e19f0f8..4cbc8cbbfd 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -562,8 +562,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel(0x00000000, &fec->eth->gaddr1);
writel(0x00000000, &fec->eth->gaddr2);
- /* Do not access reserved register for i.MX6UL */
- if (!is_mx6ul() && !is_mx6ull()) {
+ /* Do not access reserved register */
+ if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (17 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-05 20:37 ` Joe Hershberger
` (2 more replies)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL Peng Fan
` (3 subsequent siblings)
22 siblings, 3 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
When building for 64bits system, we get some warnings about type
cast between pointer and integer. This patch eliminates the warnings
by using ulong/long type which is 32bits on 32bits system or 64bits on
64bits system.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
---
drivers/net/fec_mxc.c | 74 ++++++++++++++++++++++++++++++---------------------
1 file changed, 43 insertions(+), 31 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4cbc8cbbfd..ff7ad91116 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -284,7 +284,7 @@ static int fec_tx_task_disable(struct fec_priv *fec)
static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
{
uint32_t size;
- uint8_t *data;
+ ulong data;
int i;
/*
@@ -293,9 +293,9 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
*/
size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
- data = (uint8_t *)fec->rbd_base[i].data_pointer;
- memset(data, 0, dsize);
- flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+ data = fec->rbd_base[i].data_pointer;
+ memset((void *)data, 0, dsize);
+ flush_dcache_range(data, data + size);
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
@@ -305,8 +305,8 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
- flush_dcache_range((unsigned)fec->rbd_base,
- (unsigned)fec->rbd_base + size);
+ flush_dcache_range((ulong)fec->rbd_base,
+ (ulong)fec->rbd_base + size);
}
/**
@@ -323,7 +323,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
*/
static void fec_tbd_init(struct fec_priv *fec)
{
- unsigned addr = (unsigned)fec->tbd_base;
+ ulong addr = (ulong)fec->tbd_base;
unsigned size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
@@ -423,7 +423,7 @@ static int fec_open(struct eth_device *edev)
struct fec_priv *fec = (struct fec_priv *)edev->priv;
#endif
int speed;
- uint32_t addr, size;
+ ulong addr, size;
int i;
debug("fec_open: fec_open(dev)\n");
@@ -439,7 +439,7 @@ static int fec_open(struct eth_device *edev)
/* Flush the descriptors into RAM */
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
- addr = (uint32_t)fec->rbd_base;
+ addr = (ulong)fec->rbd_base;
flush_dcache_range(addr, addr + size);
#ifdef FEC_QUIRK_ENET_MAC
@@ -533,8 +533,9 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
#else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
#endif
- uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
- int i;
+ u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
+ u8 *i;
+ ulong addr;
/* Initialize MAC address */
#ifdef CONFIG_DM_ETH
@@ -574,8 +575,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
- writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
- writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
+
+ addr = (ulong)fec->tbd_base;
+ writel((uint32_t)addr, &fec->eth->etdsr);
+
+ addr = (ulong)fec->rbd_base;
+ writel((uint32_t)addr, &fec->eth->erdsr);
#ifndef CONFIG_PHYLIB
if (fec->xcv_type != SEVENWIRE)
@@ -640,8 +645,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
#endif
{
unsigned int status;
- uint32_t size, end;
- uint32_t addr;
+ u32 size;
+ ulong addr, end;
int timeout = FEC_XFER_TIMEOUT;
int ret = 0;
@@ -672,13 +677,13 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
swap_packet((uint32_t *)packet, length);
#endif
- addr = (uint32_t)packet;
+ addr = (ulong)packet;
end = roundup(addr + length, ARCH_DMA_MINALIGN);
addr &= ~(ARCH_DMA_MINALIGN - 1);
flush_dcache_range(addr, end);
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
- writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
+ writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
/*
* update BD's status now
@@ -698,7 +703,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
* can start DMA.
*/
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
- addr = (uint32_t)fec->tbd_base;
+ addr = (ulong)fec->tbd_base;
flush_dcache_range(addr, addr + size);
/*
@@ -799,7 +804,7 @@ static int fec_recv(struct eth_device *dev)
unsigned long ievent;
int frame_length, len = 0;
uint16_t bd_status;
- uint32_t addr, size, end;
+ ulong addr, size, end;
int i;
ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
@@ -854,7 +859,7 @@ static int fec_recv(struct eth_device *dev)
* the descriptor. The solution is to mark the whole cache line when all
* descriptors in the cache line are processed.
*/
- addr = (uint32_t)rbd;
+ addr = (ulong)rbd;
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
invalidate_dcache_range(addr, addr + size);
@@ -882,8 +887,8 @@ static int fec_recv(struct eth_device *dev)
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR)
- debug("error frame: 0x%08x 0x%08x\n",
- addr, bd_status);
+ debug("error frame: 0x%08lx 0x%08x\n",
+ addr, bd_status);
}
/*
@@ -895,7 +900,7 @@ static int fec_recv(struct eth_device *dev)
size = RXDESC_PER_CACHELINE - 1;
if ((fec->rbd_index & size) == size) {
i = fec->rbd_index - size;
- addr = (uint32_t)&fec->rbd_base[i];
+ addr = (ulong)&fec->rbd_base[i];
for (; i <= fec->rbd_index ; i++) {
fec_rbd_clean(i == (FEC_RBD_NUM - 1),
&fec->rbd_base[i]);
@@ -922,6 +927,7 @@ static int fec_alloc_descs(struct fec_priv *fec)
unsigned int size;
int i;
uint8_t *data;
+ ulong addr;
/* Allocate TX descriptors. */
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
@@ -950,11 +956,12 @@ static int fec_alloc_descs(struct fec_priv *fec)
memset(data, 0, size);
- fec->rbd_base[i].data_pointer = (uint32_t)data;
+ addr = (ulong)data;
+ fec->rbd_base[i].data_pointer = (uint32_t)addr;
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
/* Flush the buffer to memory. */
- flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+ flush_dcache_range(addr, addr + size);
}
/* Mark the last RBD to close the ring. */
@@ -966,8 +973,10 @@ static int fec_alloc_descs(struct fec_priv *fec)
return 0;
err_ring:
- for (; i >= 0; i--)
- free((void *)fec->rbd_base[i].data_pointer);
+ for (; i >= 0; i--) {
+ addr = fec->rbd_base[i].data_pointer;
+ free((void *)addr);
+ }
free(fec->rbd_base);
err_rx:
free(fec->tbd_base);
@@ -978,9 +987,12 @@ err_tx:
static void fec_free_descs(struct fec_priv *fec)
{
int i;
+ ulong addr;
- for (i = 0; i < FEC_RBD_NUM; i++)
- free((void *)fec->rbd_base[i].data_pointer);
+ for (i = 0; i < FEC_RBD_NUM; i++) {
+ addr = fec->rbd_base[i].data_pointer;
+ free((void *)addr);
+ }
free(fec->rbd_base);
free(fec->tbd_base);
}
@@ -995,7 +1007,7 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
struct fec_priv *priv = dev_get_priv(dev);
struct ethernet_regs *eth = priv->eth;
#else
- struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
+ struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr;
#endif
struct mii_dev *bus;
int ret;
@@ -1065,7 +1077,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
edev->halt = fec_halt;
edev->write_hwaddr = fec_set_hwaddr;
- fec->eth = (struct ethernet_regs *)base_addr;
+ fec->eth = (struct ethernet_regs *)(ulong)base_addr;
fec->bd = bd;
fec->xcv_type = CONFIG_FEC_XCV_TYPE;
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (18 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-07 8:43 ` Stefano Babic
` (2 more replies)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 21/23] imx: imx8mq: add dtsi file Peng Fan
` (2 subsequent siblings)
22 siblings, 3 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Allow the dm driver be omitted by SPL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/power/pmic/Makefile | 4 ++--
drivers/power/regulator/Makefile | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f7bdfa5609..4abdaf6668 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -5,10 +5,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
+obj-$(CONFIG_$(SPL_)DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
-obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 6c149a9263..9809f7c845 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
-obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 21/23] imx: imx8mq: add dtsi file
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (19 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-16 17:44 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support Peng Fan
2017-12-04 4:31 ` [U-Boot] [PATCH V2 23/23] Add DDR settings Peng Fan
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add dtsi file for i.MX8MQ.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/dts/fsl-imx8-ca53.dtsi | 92 +++++
arch/arm/dts/fsl-imx8mq.dtsi | 425 ++++++++++++++++++++
include/dt-bindings/clock/imx8mq-clock.h | 612 +++++++++++++++++++++++++++++
include/dt-bindings/pinctrl/pins-imx8mq.h | 632 ++++++++++++++++++++++++++++++
4 files changed, 1761 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8-ca53.dtsi
create mode 100644 arch/arm/dts/fsl-imx8mq.dtsi
create mode 100644 include/dt-bindings/clock/imx8mq-clock.h
create mode 100644 include/dt-bindings/pinctrl/pins-imx8mq.h
diff --git a/arch/arm/dts/fsl-imx8-ca53.dtsi b/arch/arm/dts/fsl-imx8-ca53.dtsi
new file mode 100644
index 0000000000..6a2292a51e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8-ca53.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/{
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0000000>;
+ entry-latency-us = <700>;
+ exit-latency-us = <250>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER_SLEEP: cluster-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1000000>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
+ /* We have 1 clusters having 4 Cortex-A53 cores */
+ A53_0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0xc4000002>;
+ cpu_on = <0xc4000003>;
+ };
+};
diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi
new file mode 100644
index 0000000000..049c92fd5c
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq.dtsi
@@ -0,0 +1,425 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8-ca53.dtsi"
+#include <dt-bindings/clock/imx8mq-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pins-imx8mq.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "fsl,imx8mq";
+ interrupt-parent = <&gpc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000 0 0xc0000000>;
+ };
+
+ gic: interrupt-controller at 38800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
+ IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
+ IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
+ IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
+ IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ clock-frequency = <8333333>;
+ interrupt-parent = <&gic>;
+ };
+
+ power: power-controller {
+ compatible = "fsl,imx8mq-pm-domain";
+ num-domains = <11>;
+ #power-domain-cells = <1>;
+ };
+
+ pwm2: pwm at 30670000 {
+ compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+ reg = <0x0 0x30670000 0x0 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
+ <&clk IMX8MQ_CLK_PWM2_ROOT>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio at 30200000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30200000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 30210000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30210000 0x0 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 30220000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30220000 0x0 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 30230000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30230000 0x0 0x10000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio at 30240000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x30240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ tmu: tmu at 30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x0 0x30260000 0x0 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ u-boot,dm-pre-reloc;
+ fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
+ fsl,tmu-calibration = <0x00000000 0x00000020
+ 0x00000001 0x00000028
+ 0x00000002 0x00000030
+ 0x00000003 0x00000038
+ 0x00000004 0x00000040
+ 0x00000005 0x00000048
+ 0x00000006 0x00000050
+ 0x00000007 0x00000058
+ 0x00000008 0x00000060
+ 0x00000009 0x00000068
+ 0x0000000a 0x00000070
+ 0x0000000b 0x00000077
+
+ 0x00010000 0x00000057
+ 0x00010001 0x0000005b
+ 0x00010002 0x0000005f
+ 0x00010003 0x00000063
+ 0x00010004 0x00000067
+ 0x00010005 0x0000006b
+ 0x00010006 0x0000006f
+ 0x00010007 0x00000073
+ 0x00010008 0x00000077
+ 0x00010009 0x0000007b
+ 0x0001000a 0x0000007f
+
+ 0x00020000 0x00000002
+ 0x00020001 0x0000000e
+ 0x00020002 0x0000001a
+ 0x00020003 0x00000026
+ 0x00020004 0x00000032
+ 0x00020005 0x0000003e
+ 0x00020006 0x0000004a
+ 0x00020007 0x00000056
+ 0x00020008 0x00000062
+
+ 0x00030000 0x00000000
+ 0x00030001 0x00000008
+ 0x00030002 0x00000010
+ 0x00030003 0x00000018
+ 0x00030004 0x00000020
+ 0x00030005 0x00000028
+ 0x00030006 0x00000030
+ 0x00030007 0x00000038>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ /* cpu thermal */
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu>;
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ lcdif: lcdif at 30320000 {
+ compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
+ reg = <0x0 0x30320000 0x0 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
+ <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "pix", "axi", "disp_axi";
+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
+ assigned-clock-rate = <594000000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc at 30330000 {
+ compatible = "fsl,imx8mq-iomuxc";
+ reg = <0x0 0x30330000 0x0 0x10000>;
+ };
+
+ gpr: iomuxc-gpr at 30340000 {
+ compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
+ reg = <0x0 0x30340000 0x0 0x10000>;
+ };
+
+ ocotp: ocotp-ctrl at 30350000 {
+ compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
+ reg = <0x0 0x30350000 0x0 0x10000>;
+ };
+
+ anatop: anatop at 30360000 {
+ compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x0 0x30360000 0x0 0x10000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clk: ccm at 30380000 {
+ compatible = "fsl,imx8mq-ccm";
+ reg = <0x0 0x30380000 0x0 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+
+ gpc: gpc at 303a0000 {
+ compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
+ reg = <0x0 0x303a0000 0x0 0x10000>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
+
+ usdhc1: usdhc at 30b40000 {
+ compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x0 0x30b40000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_USDHC1_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
+ assigned-clock-rates = <400000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc at 30b50000 {
+ compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+ reg = <0x0 0x30b50000 0x0 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_USDHC2_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ fec1: ethernet at 30be0000 {
+ compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
+ reg = <0x0 0x30be0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
+ <&clk IMX8MQ_CLK_ENET1_ROOT>,
+ <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
+ <&clk IMX8MQ_CLK_ENET_REF_DIV>,
+ <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
+ <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
+ <&clk IMX8MQ_CLK_ENET_REF_SRC>,
+ <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS2_PLL_125M>;
+ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+ stop-mode = <&gpr 0x10 3>;
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ fsl,wakeup_irq = <2>;
+ status = "disabled";
+ };
+
+ imx_ion {
+ compatible = "fsl,mxc-ion";
+ fsl,heap-id = <0>;
+ };
+
+ i2c1: i2c at 30a20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx21-i2c";
+ reg = <0x0 0x30a20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 30a30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx21-i2c";
+ reg = <0x0 0x30a30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 30a40000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx21-i2c";
+ reg = <0x0 0x30a40000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at 30a50000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx21-i2c";
+ reg = <0x0 0x30a50000 0x0 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
+ status = "disabled";
+ };
+
+ wdog1: wdog at 30280000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0 0x30280000 0 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
+ status = "disabled";
+ };
+
+ wdog2: wdog at 30290000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0 0x30290000 0 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
+ status = "disabled";
+ };
+
+ wdog3: wdog at 302a0000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0 0x302a0000 0 0x10000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
+ status = "disabled";
+ };
+
+ dma_cap: dma_cap {
+ compatible = "dma-capability";
+ only-dma-mask32 = <1>;
+ };
+
+ qspi: qspi at 30bb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-qspi";
+ reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
+ <&clk IMX8MQ_CLK_QSPI_ROOT>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+};
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
new file mode 100644
index 0000000000..11dcafcfde
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -0,0 +1,612 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
+#define __DT_BINDINGS_CLOCK_IMX8MQ_H
+
+#define IMX8MQ_CLK_DUMMY 0
+#define IMX8MQ_CLK_32K 1
+#define IMX8MQ_CLK_25M 2
+#define IMX8MQ_CLK_27M 3
+#define IMX8MQ_CLK_EXT1 4
+#define IMX8MQ_CLK_EXT2 5
+#define IMX8MQ_CLK_EXT3 6
+#define IMX8MQ_CLK_EXT4 7
+
+/* ANAMIX PLL clocks */
+/* FRAC PLLs */
+/* ARM PLL */
+#define IMX8MQ_ARM_PLL_REF_SEL 8
+#define IMX8MQ_ARM_PLL_REF_DIV 9
+#define IMX8MQ_ARM_PLL 10
+#define IMX8MQ_ARM_PLL_BYPASS 11
+#define IMX8MQ_ARM_PLL_OUT 12
+
+/* GPU PLL */
+#define IMX8MQ_GPU_PLL_REF_SEL 13
+#define IMX8MQ_GPU_PLL_REF_DIV 14
+#define IMX8MQ_GPU_PLL 15
+#define IMX8MQ_GPU_PLL_BYPASS 16
+#define IMX8MQ_GPU_PLL_OUT 17
+
+/* VPU PLL */
+#define IMX8MQ_VPU_PLL_REF_SEL 18
+#define IMX8MQ_VPU_PLL_REF_DIV 19
+#define IMX8MQ_VPU_PLL 20
+#define IMX8MQ_VPU_PLL_BYPASS 21
+#define IMX8MQ_VPU_PLL_OUT 22
+
+/* AUDIO PLL1 */
+#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
+#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
+#define IMX8MQ_AUDIO_PLL1 25
+#define IMX8MQ_AUDIO_PLL1_BYPASS 26
+#define IMX8MQ_AUDIO_PLL1_OUT 27
+
+/* AUDIO PLL2 */
+#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
+#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
+#define IMX8MQ_AUDIO_PLL2 30
+#define IMX8MQ_AUDIO_PLL2_BYPASS 31
+#define IMX8MQ_AUDIO_PLL2_OUT 32
+
+/* VIDEO PLL1 */
+#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
+#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
+#define IMX8MQ_VIDEO_PLL1 35
+#define IMX8MQ_VIDEO_PLL1_BYPASS 36
+#define IMX8MQ_VIDEO_PLL1_OUT 37
+
+/* SYS1 PLL */
+#define IMX8MQ_SYS1_PLL1_REF_SEL 38
+#define IMX8MQ_SYS1_PLL1_REF_DIV 39
+#define IMX8MQ_SYS1_PLL1 40
+#define IMX8MQ_SYS1_PLL1_OUT 41
+#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
+#define IMX8MQ_SYS1_PLL2 43
+#define IMX8MQ_SYS1_PLL2_DIV 44
+#define IMX8MQ_SYS1_PLL2_OUT 45
+
+/* SYS2 PLL */
+#define IMX8MQ_SYS2_PLL1_REF_SEL 46
+#define IMX8MQ_SYS2_PLL1_REF_DIV 47
+#define IMX8MQ_SYS2_PLL1 48
+#define IMX8MQ_SYS2_PLL1_OUT 49
+#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
+#define IMX8MQ_SYS2_PLL2 51
+#define IMX8MQ_SYS2_PLL2_DIV 52
+#define IMX8MQ_SYS2_PLL2_OUT 53
+
+/* SYS3 PLL */
+#define IMX8MQ_SYS3_PLL1_REF_SEL 54
+#define IMX8MQ_SYS3_PLL1_REF_DIV 55
+#define IMX8MQ_SYS3_PLL1 56
+#define IMX8MQ_SYS3_PLL1_OUT 57
+#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
+#define IMX8MQ_SYS3_PLL2 59
+#define IMX8MQ_SYS3_PLL2_DIV 60
+#define IMX8MQ_SYS3_PLL2_OUT 61
+
+/* DRAM PLL */
+#define IMX8MQ_DRAM_PLL1_REF_SEL 62
+#define IMX8MQ_DRAM_PLL1_REF_DIV 63
+#define IMX8MQ_DRAM_PLL1 64
+#define IMX8MQ_DRAM_PLL1_OUT 65
+#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
+#define IMX8MQ_DRAM_PLL2 67
+#define IMX8MQ_DRAM_PLL2_DIV 68
+#define IMX8MQ_DRAM_PLL2_OUT 69
+
+/* SYS PLL DIV */
+#define IMX8MQ_SYS1_PLL_40M 70
+#define IMX8MQ_SYS1_PLL_80M 71
+#define IMX8MQ_SYS1_PLL_100M 72
+#define IMX8MQ_SYS1_PLL_133M 73
+#define IMX8MQ_SYS1_PLL_160M 74
+#define IMX8MQ_SYS1_PLL_200M 75
+#define IMX8MQ_SYS1_PLL_266M 76
+#define IMX8MQ_SYS1_PLL_400M 77
+#define IMX8MQ_SYS1_PLL_800M 78
+
+#define IMX8MQ_SYS2_PLL_50M 79
+#define IMX8MQ_SYS2_PLL_100M 80
+#define IMX8MQ_SYS2_PLL_125M 81
+#define IMX8MQ_SYS2_PLL_166M 82
+#define IMX8MQ_SYS2_PLL_200M 83
+#define IMX8MQ_SYS2_PLL_250M 84
+#define IMX8MQ_SYS2_PLL_333M 85
+#define IMX8MQ_SYS2_PLL_500M 86
+#define IMX8MQ_SYS2_PLL_1000M 87
+
+/* CCM ROOT clocks */
+/* A53 */
+#define IMX8MQ_CLK_A53_SRC 88
+#define IMX8MQ_CLK_A53_CG 89
+#define IMX8MQ_CLK_A53_DIV 90
+/* M4 */
+#define IMX8MQ_CLK_M4_SRC 91
+#define IMX8MQ_CLK_M4_CG 92
+#define IMX8MQ_CLK_M4_DIV 93
+/* VPU */
+#define IMX8MQ_CLK_VPU_SRC 94
+#define IMX8MQ_CLK_VPU_CG 95
+#define IMX8MQ_CLK_VPU_DIV 96
+/* GPU CORE */
+#define IMX8MQ_CLK_GPU_CORE_SRC 97
+#define IMX8MQ_CLK_GPU_CORE_CG 98
+#define IMX8MQ_CLK_GPU_CORE_DIV 99
+/* GPU SHADER */
+#define IMX8MQ_CLK_GPU_SHADER_SRC 100
+#define IMX8MQ_CLK_GPU_SHADER_CG 101
+#define IMX8MQ_CLK_GPU_SHADER_DIV 102
+
+/* BUS TYPE */
+/* MAIN AXI */
+#define IMX8MQ_CLK_MAIN_AXI_SRC 103
+#define IMX8MQ_CLK_MAIN_AXI_CG 104
+#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
+#define IMX8MQ_CLK_MAIN_AXI_DIV 106
+/* ENET AXI */
+#define IMX8MQ_CLK_ENET_AXI_SRC 107
+#define IMX8MQ_CLK_ENET_AXI_CG 108
+#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
+#define IMX8MQ_CLK_ENET_AXI_DIV 110
+/* NAND_USDHC_BUS */
+#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
+#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
+#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
+#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
+/* VPU BUS */
+#define IMX8MQ_CLK_VPU_BUS_SRC 115
+#define IMX8MQ_CLK_VPU_BUS_CG 116
+#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
+#define IMX8MQ_CLK_VPU_BUS_DIV 118
+/* DISP_AXI */
+#define IMX8MQ_CLK_DISP_AXI_SRC 119
+#define IMX8MQ_CLK_DISP_AXI_CG 120
+#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
+#define IMX8MQ_CLK_DISP_AXI_DIV 122
+/* DISP APB */
+#define IMX8MQ_CLK_DISP_APB_SRC 123
+#define IMX8MQ_CLK_DISP_APB_CG 124
+#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
+#define IMX8MQ_CLK_DISP_APB_DIV 126
+/* DISP RTRM */
+#define IMX8MQ_CLK_DISP_RTRM_SRC 127
+#define IMX8MQ_CLK_DISP_RTRM_CG 128
+#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
+#define IMX8MQ_CLK_DISP_RTRM_DIV 130
+/* USB_BUS */
+#define IMX8MQ_CLK_USB_BUS_SRC 131
+#define IMX8MQ_CLK_USB_BUS_CG 132
+#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
+#define IMX8MQ_CLK_USB_BUS_DIV 134
+/* GPU_AXI */
+#define IMX8MQ_CLK_GPU_AXI_SRC 135
+#define IMX8MQ_CLK_GPU_AXI_CG 136
+#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
+#define IMX8MQ_CLK_GPU_AXI_DIV 138
+/* GPU_AHB */
+#define IMX8MQ_CLK_GPU_AHB_SRC 139
+#define IMX8MQ_CLK_GPU_AHB_CG 140
+#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
+#define IMX8MQ_CLK_GPU_AHB_DIV 142
+/* NOC */
+#define IMX8MQ_CLK_NOC_SRC 143
+#define IMX8MQ_CLK_NOC_CG 144
+#define IMX8MQ_CLK_NOC_PRE_DIV 145
+#define IMX8MQ_CLK_NOC_DIV 146
+/* NOC_APB */
+#define IMX8MQ_CLK_NOC_APB_SRC 147
+#define IMX8MQ_CLK_NOC_APB_CG 148
+#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
+#define IMX8MQ_CLK_NOC_APB_DIV 150
+
+/* AHB */
+#define IMX8MQ_CLK_AHB_SRC 151
+#define IMX8MQ_CLK_AHB_CG 152
+#define IMX8MQ_CLK_AHB_PRE_DIV 153
+#define IMX8MQ_CLK_AHB_DIV 154
+/* AUDIO AHB */
+#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
+#define IMX8MQ_CLK_AUDIO_AHB_CG 156
+#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
+#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
+
+/* DRAM_ALT */
+#define IMX8MQ_CLK_DRAM_ALT_SRC 159
+#define IMX8MQ_CLK_DRAM_ALT_CG 160
+#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
+#define IMX8MQ_CLK_DRAM_ALT_DIV 162
+/* DRAM APB */
+#define IMX8MQ_CLK_DRAM_APB_SRC 163
+#define IMX8MQ_CLK_DRAM_APB_CG 164
+#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
+#define IMX8MQ_CLK_DRAM_APB_DIV 166
+/* VPU_G1 */
+#define IMX8MQ_CLK_VPU_G1_SRC 167
+#define IMX8MQ_CLK_VPU_G1_CG 168
+#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
+#define IMX8MQ_CLK_VPU_G1_DIV 170
+/* VPU_G2 */
+#define IMX8MQ_CLK_VPU_G2_SRC 171
+#define IMX8MQ_CLK_VPU_G2_CG 172
+#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
+#define IMX8MQ_CLK_VPU_G2_DIV 174
+/* DISP_DTRC */
+#define IMX8MQ_CLK_DISP_DTRC_SRC 175
+#define IMX8MQ_CLK_DISP_DTRC_CG 176
+#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
+#define IMX8MQ_CLK_DISP_DTRC_DIV 178
+/* DISP_DC8000 */
+#define IMX8MQ_CLK_DISP_DC8000_SRC 179
+#define IMX8MQ_CLK_DISP_DC8000_CG 180
+#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
+#define IMX8MQ_CLK_DISP_DC8000_DIV 182
+/* PCIE_CTRL */
+#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
+#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
+#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
+#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
+/* PCIE_PHY */
+#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
+#define IMX8MQ_CLK_PCIE1_PHY_CG 188
+#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
+#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
+/* PCIE_AUX */
+#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
+#define IMX8MQ_CLK_PCIE1_AUX_CG 192
+#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
+#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
+/* DC_PIXEL */
+#define IMX8MQ_CLK_DC_PIXEL_SRC 195
+#define IMX8MQ_CLK_DC_PIXEL_CG 196
+#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
+#define IMX8MQ_CLK_DC_PIXEL_DIV 198
+/* LCDIF_PIXEL */
+#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
+#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
+#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
+#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
+/* SAI1~6 */
+#define IMX8MQ_CLK_SAI1_SRC 203
+#define IMX8MQ_CLK_SAI1_CG 204
+#define IMX8MQ_CLK_SAI1_PRE_DIV 205
+#define IMX8MQ_CLK_SAI1_DIV 206
+
+#define IMX8MQ_CLK_SAI2_SRC 207
+#define IMX8MQ_CLK_SAI2_CG 208
+#define IMX8MQ_CLK_SAI2_PRE_DIV 209
+#define IMX8MQ_CLK_SAI2_DIV 210
+
+#define IMX8MQ_CLK_SAI3_SRC 211
+#define IMX8MQ_CLK_SAI3_CG 212
+#define IMX8MQ_CLK_SAI3_PRE_DIV 213
+#define IMX8MQ_CLK_SAI3_DIV 214
+
+#define IMX8MQ_CLK_SAI4_SRC 215
+#define IMX8MQ_CLK_SAI4_CG 216
+#define IMX8MQ_CLK_SAI4_PRE_DIV 217
+#define IMX8MQ_CLK_SAI4_DIV 218
+
+#define IMX8MQ_CLK_SAI5_SRC 219
+#define IMX8MQ_CLK_SAI5_CG 220
+#define IMX8MQ_CLK_SAI5_PRE_DIV 221
+#define IMX8MQ_CLK_SAI5_DIV 222
+
+#define IMX8MQ_CLK_SAI6_SRC 223
+#define IMX8MQ_CLK_SAI6_CG 224
+#define IMX8MQ_CLK_SAI6_PRE_DIV 225
+#define IMX8MQ_CLK_SAI6_DIV 226
+/* SPDIF1 */
+#define IMX8MQ_CLK_SPDIF1_SRC 227
+#define IMX8MQ_CLK_SPDIF1_CG 228
+#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
+#define IMX8MQ_CLK_SPDIF1_DIV 230
+/* SPDIF2 */
+#define IMX8MQ_CLK_SPDIF2_SRC 231
+#define IMX8MQ_CLK_SPDIF2_CG 232
+#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
+#define IMX8MQ_CLK_SPDIF2_DIV 234
+/* ENET_REF */
+#define IMX8MQ_CLK_ENET_REF_SRC 235
+#define IMX8MQ_CLK_ENET_REF_CG 236
+#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
+#define IMX8MQ_CLK_ENET_REF_DIV 238
+/* ENET_TIMER */
+#define IMX8MQ_CLK_ENET_TIMER_SRC 239
+#define IMX8MQ_CLK_ENET_TIMER_CG 240
+#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
+#define IMX8MQ_CLK_ENET_TIMER_DIV 242
+/* ENET_PHY */
+#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
+#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
+#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
+#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
+/* NAND */
+#define IMX8MQ_CLK_NAND_SRC 247
+#define IMX8MQ_CLK_NAND_CG 248
+#define IMX8MQ_CLK_NAND_PRE_DIV 249
+#define IMX8MQ_CLK_NAND_DIV 250
+/* QSPI */
+#define IMX8MQ_CLK_QSPI_SRC 251
+#define IMX8MQ_CLK_QSPI_CG 252
+#define IMX8MQ_CLK_QSPI_PRE_DIV 253
+#define IMX8MQ_CLK_QSPI_DIV 254
+/* USDHC1 */
+#define IMX8MQ_CLK_USDHC1_SRC 255
+#define IMX8MQ_CLK_USDHC1_CG 256
+#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
+#define IMX8MQ_CLK_USDHC1_DIV 258
+/* USDHC2 */
+#define IMX8MQ_CLK_USDHC2_SRC 259
+#define IMX8MQ_CLK_USDHC2_CG 260
+#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
+#define IMX8MQ_CLK_USDHC2_DIV 262
+/* I2C1 */
+#define IMX8MQ_CLK_I2C1_SRC 263
+#define IMX8MQ_CLK_I2C1_CG 264
+#define IMX8MQ_CLK_I2C1_PRE_DIV 265
+#define IMX8MQ_CLK_I2C1_DIV 266
+/* I2C2 */
+#define IMX8MQ_CLK_I2C2_SRC 267
+#define IMX8MQ_CLK_I2C2_CG 268
+#define IMX8MQ_CLK_I2C2_PRE_DIV 269
+#define IMX8MQ_CLK_I2C2_DIV 270
+/* I2C3 */
+#define IMX8MQ_CLK_I2C3_SRC 271
+#define IMX8MQ_CLK_I2C3_CG 272
+#define IMX8MQ_CLK_I2C3_PRE_DIV 273
+#define IMX8MQ_CLK_I2C3_DIV 274
+/* I2C4 */
+#define IMX8MQ_CLK_I2C4_SRC 275
+#define IMX8MQ_CLK_I2C4_CG 276
+#define IMX8MQ_CLK_I2C4_PRE_DIV 277
+#define IMX8MQ_CLK_I2C4_DIV 278
+/* UART1 */
+#define IMX8MQ_CLK_UART1_SRC 279
+#define IMX8MQ_CLK_UART1_CG 280
+#define IMX8MQ_CLK_UART1_PRE_DIV 281
+#define IMX8MQ_CLK_UART1_DIV 282
+/* UART2 */
+#define IMX8MQ_CLK_UART2_SRC 283
+#define IMX8MQ_CLK_UART2_CG 284
+#define IMX8MQ_CLK_UART2_PRE_DIV 285
+#define IMX8MQ_CLK_UART2_DIV 286
+/* UART3 */
+#define IMX8MQ_CLK_UART3_SRC 287
+#define IMX8MQ_CLK_UART3_CG 288
+#define IMX8MQ_CLK_UART3_PRE_DIV 289
+#define IMX8MQ_CLK_UART3_DIV 290
+/* UART4 */
+#define IMX8MQ_CLK_UART4_SRC 291
+#define IMX8MQ_CLK_UART4_CG 292
+#define IMX8MQ_CLK_UART4_PRE_DIV 293
+#define IMX8MQ_CLK_UART4_DIV 294
+/* USB_CORE_REF */
+#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
+#define IMX8MQ_CLK_USB_CORE_REF_CG 296
+#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
+#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
+/* USB_PHY_REF */
+#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
+#define IMX8MQ_CLK_USB_PHY_REF_CG 300
+#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
+#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
+/* ECSPI1 */
+#define IMX8MQ_CLK_ECSPI1_SRC 303
+#define IMX8MQ_CLK_ECSPI1_CG 304
+#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
+#define IMX8MQ_CLK_ECSPI1_DIV 306
+/* ECSPI2 */
+#define IMX8MQ_CLK_ECSPI2_SRC 307
+#define IMX8MQ_CLK_ECSPI2_CG 308
+#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
+#define IMX8MQ_CLK_ECSPI2_DIV 310
+/* PWM1 */
+#define IMX8MQ_CLK_PWM1_SRC 311
+#define IMX8MQ_CLK_PWM1_CG 312
+#define IMX8MQ_CLK_PWM1_PRE_DIV 313
+#define IMX8MQ_CLK_PWM1_DIV 314
+/* PWM2 */
+#define IMX8MQ_CLK_PWM2_SRC 315
+#define IMX8MQ_CLK_PWM2_CG 316
+#define IMX8MQ_CLK_PWM2_PRE_DIV 317
+#define IMX8MQ_CLK_PWM2_DIV 318
+/* PWM3 */
+#define IMX8MQ_CLK_PWM3_SRC 319
+#define IMX8MQ_CLK_PWM3_CG 320
+#define IMX8MQ_CLK_PWM3_PRE_DIV 321
+#define IMX8MQ_CLK_PWM3_DIV 322
+/* PWM4 */
+#define IMX8MQ_CLK_PWM4_SRC 323
+#define IMX8MQ_CLK_PWM4_CG 324
+#define IMX8MQ_CLK_PWM4_PRE_DIV 325
+#define IMX8MQ_CLK_PWM4_DIV 326
+/* GPT1 */
+#define IMX8MQ_CLK_GPT1_SRC 327
+#define IMX8MQ_CLK_GPT1_CG 328
+#define IMX8MQ_CLK_GPT1_PRE_DIV 329
+#define IMX8MQ_CLK_GPT1_DIV 330
+/* WDOG */
+#define IMX8MQ_CLK_WDOG_SRC 331
+#define IMX8MQ_CLK_WDOG_CG 332
+#define IMX8MQ_CLK_WDOG_PRE_DIV 333
+#define IMX8MQ_CLK_WDOG_DIV 334
+/* WRCLK */
+#define IMX8MQ_CLK_WRCLK_SRC 335
+#define IMX8MQ_CLK_WRCLK_CG 336
+#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
+#define IMX8MQ_CLK_WRCLK_DIV 338
+/* DSI_CORE */
+#define IMX8MQ_CLK_DSI_CORE_SRC 339
+#define IMX8MQ_CLK_DSI_CORE_CG 340
+#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
+#define IMX8MQ_CLK_DSI_CORE_DIV 342
+/* DSI_PHY */
+#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
+#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
+#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
+#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
+/* DSI_DBI */
+#define IMX8MQ_CLK_DSI_DBI_SRC 347
+#define IMX8MQ_CLK_DSI_DBI_CG 348
+#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
+#define IMX8MQ_CLK_DSI_DBI_DIV 350
+/*DSI_ESC */
+#define IMX8MQ_CLK_DSI_ESC_SRC 351
+#define IMX8MQ_CLK_DSI_ESC_CG 352
+#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
+#define IMX8MQ_CLK_DSI_ESC_DIV 354
+/* CSI1_CORE */
+#define IMX8MQ_CLK_CSI1_CORE_SRC 355
+#define IMX8MQ_CLK_CSI1_CORE_CG 356
+#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
+#define IMX8MQ_CLK_CSI1_CORE_DIV 358
+/* CSI1_PHY */
+#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
+#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
+#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
+#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
+/* CSI_ESC */
+#define IMX8MQ_CLK_CSI1_ESC_SRC 363
+#define IMX8MQ_CLK_CSI1_ESC_CG 364
+#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
+#define IMX8MQ_CLK_CSI1_ESC_DIV 366
+/* CSI2_CORE */
+#define IMX8MQ_CLK_CSI2_CORE_SRC 367
+#define IMX8MQ_CLK_CSI2_CORE_CG 368
+#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
+#define IMX8MQ_CLK_CSI2_CORE_DIV 370
+/* CSI2_PHY */
+#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
+#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
+#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
+#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
+/* CSI2_ESC */
+#define IMX8MQ_CLK_CSI2_ESC_SRC 375
+#define IMX8MQ_CLK_CSI2_ESC_CG 376
+#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
+#define IMX8MQ_CLK_CSI2_ESC_DIV 378
+/* PCIE2_CTRL */
+#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
+#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
+#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
+#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
+/* PCIE2_PHY */
+#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
+#define IMX8MQ_CLK_PCIE2_PHY_CG 384
+#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
+#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
+/* PCIE2_AUX */
+#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
+#define IMX8MQ_CLK_PCIE2_AUX_CG 388
+#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
+#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
+/* ECSPI3 */
+#define IMX8MQ_CLK_ECSPI3_SRC 391
+#define IMX8MQ_CLK_ECSPI3_CG 392
+#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
+#define IMX8MQ_CLK_ECSPI3_DIV 394
+
+/* CCGR clocks */
+#define IMX8MQ_CLK_A53_ROOT 395
+#define IMX8MQ_CLK_DRAM_ROOT 396
+#define IMX8MQ_CLK_ECSPI1_ROOT 397
+#define IMX8MQ_CLK_ECSPI2_ROOT 398
+#define IMX8MQ_CLK_ECSPI3_ROOT 399
+#define IMX8MQ_CLK_ENET1_ROOT 400
+#define IMX8MQ_CLK_GPT1_ROOT 401
+#define IMX8MQ_CLK_I2C1_ROOT 402
+#define IMX8MQ_CLK_I2C2_ROOT 403
+#define IMX8MQ_CLK_I2C3_ROOT 404
+#define IMX8MQ_CLK_I2C4_ROOT 405
+#define IMX8MQ_CLK_M4_ROOT 406
+#define IMX8MQ_CLK_PCIE1_ROOT 407
+#define IMX8MQ_CLK_PCIE2_ROOT 408
+#define IMX8MQ_CLK_PWM1_ROOT 409
+#define IMX8MQ_CLK_PWM2_ROOT 410
+#define IMX8MQ_CLK_PWM3_ROOT 411
+#define IMX8MQ_CLK_PWM4_ROOT 412
+#define IMX8MQ_CLK_QSPI_ROOT 413
+#define IMX8MQ_CLK_SAI1_ROOT 414
+#define IMX8MQ_CLK_SAI2_ROOT 415
+#define IMX8MQ_CLK_SAI3_ROOT 416
+#define IMX8MQ_CLK_SAI4_ROOT 417
+#define IMX8MQ_CLK_SAI5_ROOT 418
+#define IMX8MQ_CLK_SAI6_ROOT 419
+#define IMX8MQ_CLK_UART1_ROOT 420
+#define IMX8MQ_CLK_UART2_ROOT 421
+#define IMX8MQ_CLK_UART3_ROOT 422
+#define IMX8MQ_CLK_UART4_ROOT 423
+#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
+#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
+#define IMX8MQ_CLK_USB1_PHY_ROOT 426
+#define IMX8MQ_CLK_USB2_PHY_ROOT 427
+#define IMX8MQ_CLK_USDHC1_ROOT 428
+#define IMX8MQ_CLK_USDHC2_ROOT 429
+#define IMX8MQ_CLK_WDOG1_ROOT 430
+#define IMX8MQ_CLK_WDOG2_ROOT 431
+#define IMX8MQ_CLK_WDOG3_ROOT 432
+#define IMX8MQ_CLK_GPU_ROOT 433
+#define IMX8MQ_CLK_HEVC_ROOT 434
+#define IMX8MQ_CLK_AVC_ROOT 435
+#define IMX8MQ_CLK_VP9_ROOT 436
+#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
+#define IMX8MQ_CLK_DISP_ROOT 438
+#define IMX8MQ_CLK_HDMI_ROOT 439
+#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
+#define IMX8MQ_CLK_VPU_DEC_ROOT 441
+#define IMX8MQ_CLK_CSI1_ROOT 442
+#define IMX8MQ_CLK_CSI2_ROOT 443
+#define IMX8MQ_CLK_RAWNAND_ROOT 444
+#define IMX8MQ_CLK_SDMA1_ROOT 445
+#define IMX8MQ_CLK_SDMA2_ROOT 446
+#define IMX8MQ_CLK_VPU_G1_ROOT 447
+#define IMX8MQ_CLK_VPU_G2_ROOT 448
+
+/* SCCG PLL GATE */
+#define IMX8MQ_SYS1_PLL_OUT 449
+#define IMX8MQ_SYS2_PLL_OUT 450
+#define IMX8MQ_SYS3_PLL_OUT 451
+#define IMX8MQ_DRAM_PLL_OUT 452
+
+#define IMX8MQ_GPT_3M_CLK 453
+
+#define IMX8MQ_CLK_IPG_ROOT 454
+#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
+#define IMX8MQ_CLK_SAI1_IPG 456
+#define IMX8MQ_CLK_SAI2_IPG 457
+#define IMX8MQ_CLK_SAI3_IPG 458
+#define IMX8MQ_CLK_SAI4_IPG 459
+#define IMX8MQ_CLK_SAI5_IPG 460
+#define IMX8MQ_CLK_SAI6_IPG 461
+
+/* DSI AHB/IPG clocks */
+/* rxesc clock */
+#define IMX8MQ_CLK_DSI_AHB_SRC 462
+#define IMX8MQ_CLK_DSI_AHB_CG 463
+#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
+#define IMX8MQ_CLK_DSI_AHB_DIV 465
+/* txesc clock */
+#define IMX8MQ_CLK_DSI_IPG_DIV 466
+
+/* VIDEO2 PLL */
+#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
+#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
+#define IMX8MQ_VIDEO2_PLL1 469
+#define IMX8MQ_VIDEO2_PLL1_OUT 470
+#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
+#define IMX8MQ_VIDEO2_PLL2 472
+#define IMX8MQ_VIDEO2_PLL2_DIV 473
+#define IMX8MQ_VIDEO2_PLL2_OUT 474
+#define IMX8MQ_CLK_TMU_ROOT 475
+
+#define IMX8MQ_CLK_END 476
+#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/pinctrl/pins-imx8mq.h b/include/dt-bindings/pinctrl/pins-imx8mq.h
new file mode 100644
index 0000000000..0e1d67d414
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pins-imx8mq.h
@@ -0,0 +1,632 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_IMX8MQ_PINFUNC_H
+#define __DTS_IMX8MQ_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
+#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
+
+#endif /* __DTS_IMX8MQ_PINFUNC_H */
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (20 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 21/23] imx: imx8mq: add dtsi file Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-07 8:52 ` Stefano Babic
2017-12-16 17:51 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 23/23] Add DDR settings Peng Fan
22 siblings, 2 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.
The boot log:
"
U-Boot SPL 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31)
PMIC: PFUZE100 ID=0x10
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
PLL bypass to 100MTS setting done
Training PASS
PLL bypass to 400MTS setting done
Training PASS
Training PASS
check ddr4_pmu_train_imem code
check ddr4_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr4_pmu_train_dmem code pass
Training PASS
Normal Boot
Trying to boot from MMC2
U-Boot 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31 +0800)
CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM: 3 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Using default environment
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-imx8mq-evk.dts | 424 ++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/mx8m/Kconfig | 12 +
board/freescale/mx8mq_evk/Kconfig | 12 +
board/freescale/mx8mq_evk/Makefile | 11 +
board/freescale/mx8mq_evk/README | 38 +++
board/freescale/mx8mq_evk/mx8mq_evk.c | 156 +++++++++++++
board/freescale/mx8mq_evk/spl.c | 233 +++++++++++++++++++
configs/mx8mq_evk_defconfig | 28 +++
include/configs/mx8mq_evk.h | 265 +++++++++++++++++++++
10 files changed, 1181 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
create mode 100644 board/freescale/mx8mq_evk/Kconfig
create mode 100644 board/freescale/mx8mq_evk/Makefile
create mode 100644 board/freescale/mx8mq_evk/README
create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
create mode 100644 board/freescale/mx8mq_evk/spl.c
create mode 100644 configs/mx8mq_evk_defconfig
create mode 100644 include/configs/mx8mq_evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd540e99ea..d459755904 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -381,6 +381,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb
+
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
new file mode 100644
index 0000000000..f0aa3485e6
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -0,0 +1,424 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+ model = "Freescale i.MX8MQ EVK";
+ compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+ chosen {
+ bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+
+ ledpwm2 {
+ label = "PWM2";
+ pwms = <&pwm2 0 50000>;
+ max-brightness = <255>;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ imx8mq-evk {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
+ MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ at803x,led-act-blind-workaround;
+ at803x,eee-disabled;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pfuze100 at 08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3ab {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+ disp-dev = "mipi_dsi_northwest";
+ display = <&display0>;
+
+ display0: display at 0 {
+ bits-per-pixel = <24>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <9200000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <8>;
+ hback-porch = <4>;
+ hsync-len = <41>;
+ vback-porch = <2>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash0: n25q256a at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a";
+ spi-max-frequency = <29000000>;
+ spi-nor,ddr-quad-read-dummy = <6>;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
index 3a84c2f2b0..e3b57b7915 100644
--- a/arch/arm/mach-imx/mx8m/Kconfig
+++ b/arch/arm/mach-imx/mx8m/Kconfig
@@ -7,4 +7,16 @@ config MX8M
config SYS_SOC
default "mx8m"
+choice
+ prompt "NXP i.MX8M board select"
+ optional
+
+config TARGET_MX8MQ_EVK
+ bool "mx8mq_evk"
+ select MX8M
+
+endchoice
+
+source "board/freescale/mx8mq_evk/Kconfig"
+
endif
diff --git a/board/freescale/mx8mq_evk/Kconfig b/board/freescale/mx8mq_evk/Kconfig
new file mode 100644
index 0000000000..4e23002803
--- /dev/null
+++ b/board/freescale/mx8mq_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX8MQ_EVK
+
+config SYS_BOARD
+ default "mx8mq_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx8mq_evk"
+
+endif
diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile
new file mode 100644
index 0000000000..60c99d4194
--- /dev/null
+++ b/board/freescale/mx8mq_evk/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mx8mq_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README
new file mode 100644
index 0000000000..6be5f51a22
--- /dev/null
+++ b/board/freescale/mx8mq_evk/README
@@ -0,0 +1,38 @@
+U-Boot for the NXP i.MX8MQ EVK board
+
+Quick Start
+====================
+- Build the ARM Trusted firmware binary
+- Build U-Boot
+- Generate flash.bin using imx-mkimage
+- Boot
+
+Build the ARM Trusted firmware
+====================
+$ make PLAT=imx8mq bl31
+
+Build U-Boot
+====================
+$ export ARCH=arm64
+$ export CROSS_COMPILE=aarch64-poky-linux-
+$ make mx8mq_evk_defconfig
+$ make
+
+Generate flash.bin using imx-mkimage
+====================
+Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to
+ imx-mkimage/iMX8M
+Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin
+ lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to
+ imx-mkimage/iMX8M
+If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M
+
+make SOC=iMX8M flash_spl_uboot or make SOC=iMX8M flash_hdmi_spl_uboot to
+generate flash.bin.
+
+Burn the flash.bin to MicroSD card offset 33KB
+$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+====================
+Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
diff --git a/board/freescale/mx8mq_evk/mx8mq_evk.c b/board/freescale/mx8mq_evk/mx8mq_evk.c
new file mode 100644
index 0000000000..e31678efb7
--- /dev/null
+++ b/board/freescale/mx8mq_evk/mx8mq_evk.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/mx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const qspi_pads[] = {
+ IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+ IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+ imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
+
+ set_clk_qspi();
+
+ return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+ else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+ ARRAY_SIZE(fec1_rst_pads));
+
+ gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
+ gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+ udelay(500);
+ gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_fec();
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ board_qspi_init();
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "EVK");
+ env_set("board_rev", "iMX8MQ");
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/mx8mq_evk/spl.c b/board/freescale/mx8mq_evk/spl.c
new file mode 100644
index 0000000000..522d076124
--- /dev/null
+++ b/board/freescale/mx8mq_evk/spl.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/mx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak void ddr_init(void)
+{
+};
+
+void spl_dram_init(void)
+{
+ /* ddr init */
+ ddr_init();
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = 1;
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ return ret;
+ }
+
+ return 1;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_FSEL2)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 8},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ init_clk_usdhc(0);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ break;
+ case 1:
+ init_clk_usdhc(1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return -ENODEV;
+
+ p = pmic_get("PFUZE100");
+ ret = pmic_probe(p);
+ if (ret)
+ return -ENODEV;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
+ if ((reg & 0x3f) != 0x18) {
+ reg &= ~0x3f;
+ reg |= 0x18;
+ pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
+ }
+
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+ enable_tzc380();
+
+ /* Adjust pmic voltage to 1.0V for 800M */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Serial download mode */
+ if (is_usb_boot()) {
+ puts("Back to ROM, SDP\n");
+ restore_boot_params();
+ }
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+
+ init_uart_clk(0);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/mx8mq_evk_defconfig b/configs/mx8mq_evk_defconfig
new file mode 100644
index 0000000000..cee339d496
--- /dev/null
+++ b/configs/mx8mq_evk_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX8M=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX8MQ_EVK=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_THERMAL=y
+CONFIG_FS_FAT=y
diff --git a/include/configs/mx8mq_evk.h b/include/configs/mx8mq_evk.h
new file mode 100644
index 0000000000..0a70733560
--- /dev/null
+++ b/include/configs/mx8mq_evk.h
@@ -0,0 +1,265 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX8M_EVK_H
+#define __IMX8M_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x7E1000
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR 0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00182000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE 0x30BE0000
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+ "rdinit=/linuxrc " \
+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+ "g_mass_storage.iSerialNumber=\"\" "\
+ "clk_ignore_unused "\
+ "\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffff\0" \
+ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=fsl-imx8mq-evk.dtb\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "echo wait for boot; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "booti; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_TEXT_BASE 0x40200000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "u-boot=> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+
+#define FSL_QSPI_FLASH_SIZE (SZ_32M)
+#define FSL_QSPI_FLASH_NUM 1
+#endif
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 23/23] Add DDR settings
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
` (21 preceding siblings ...)
2017-12-04 4:31 ` [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support Peng Fan
@ 2017-12-04 4:31 ` Peng Fan
2017-12-04 17:48 ` Dr. Philipp Tomsich
22 siblings, 1 reply; 65+ messages in thread
From: Peng Fan @ 2017-12-04 4:31 UTC (permalink / raw)
To: u-boot
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-mx8m/ddr_memory_map.h | 495 +++++++++
board/freescale/mx8mq_evk/Makefile | 1 +
board/freescale/mx8mq_evk/ddr/ddr.h | 38 +
board/freescale/mx8mq_evk/ddr/ddr_init.c | 256 +++++
board/freescale/mx8mq_evk/ddr/ddrphy_train.c | 1147 ++++++++++++++++++++
board/freescale/mx8mq_evk/ddr/helper.c | 101 ++
.../mx8mq_evk/ddr/wait_ddrphy_training_complete.c | 97 ++
7 files changed, 2135 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx8m/ddr_memory_map.h
create mode 100644 board/freescale/mx8mq_evk/ddr/ddr.h
create mode 100644 board/freescale/mx8mq_evk/ddr/ddr_init.c
create mode 100644 board/freescale/mx8mq_evk/ddr/ddrphy_train.c
create mode 100644 board/freescale/mx8mq_evk/ddr/helper.c
create mode 100644 board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c
diff --git a/arch/arm/include/asm/arch-mx8m/ddr_memory_map.h b/arch/arm/include/asm/arch-mx8m/ddr_memory_map.h
new file mode 100644
index 0000000000..e0e5c30301
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/ddr_memory_map.h
@@ -0,0 +1,495 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_DDR_H
+#define __ASM_ARCH_MX8M_DDR_H
+
+#define DDRC_DDR_SS_GPR0 0x3d000000
+
+#define DDRC_IPS_BASE_ADDR_0 0x3f400000
+
+#define DDRC_MSTR_0 0x3d400000
+#define DDRC_STAT_0 0x3d400004
+#define DDRC_MSTR1_0 0x3d400008
+#define DDRC_MRCTRL0_0 0x3d400010
+#define DDRC_MRCTRL1_0 0x3d400014
+#define DDRC_MRSTAT_0 0x3d400018
+#define DDRC_MRCTRL2_0 0x3d40001c
+#define DDRC_DERATEEN_0 0x3d400020
+#define DDRC_DERATEINT_0 0x3d400024
+#define DDRC_MSTR2_0 0x3d400028
+#define DDRC_PWRCTL_0 0x3d400030
+#define DDRC_PWRTMG_0 0x3d400034
+#define DDRC_HWLPCTL_0 0x3d400038
+#define DDRC_HWFFCCTL_0 0x3d40003c
+#define DDRC_HWFFCSTAT_0 0x3d400040
+#define DDRC_RFSHCTL0_0 0x3d400050
+#define DDRC_RFSHCTL1_0 0x3d400054
+#define DDRC_RFSHCTL2_0 0x3d400058
+#define DDRC_RFSHCTL3_0 0x3d400060
+#define DDRC_RFSHTMG_0 0x3d400064
+#define DDRC_ECCCFG0_0 0x3d400070
+#define DDRC_ECCCFG1_0 0x3d400074
+#define DDRC_ECCSTAT_0 0x3d400078
+#define DDRC_ECCCLR_0 0x3d40007c
+#define DDRC_ECCERRCNT_0 0x3d400080
+#define DDRC_ECCCADDR0_0 0x3d400084
+#define DDRC_ECCCADDR1_0 0x3d400088
+#define DDRC_ECCCSYN0_0 0x3d40008c
+#define DDRC_ECCCSYN1_0 0x3d400090
+#define DDRC_ECCCSYN2_0 0x3d400094
+#define DDRC_ECCBITMASK0_0 0x3d400098
+#define DDRC_ECCBITMASK1_0 0x3d40009c
+#define DDRC_ECCBITMASK2_0 0x3d4000a0
+#define DDRC_ECCUADDR0_0 0x3d4000a4
+#define DDRC_ECCUADDR1_0 0x3d4000a8
+#define DDRC_ECCUSYN0_0 0x3d4000ac
+#define DDRC_ECCUSYN1_0 0x3d4000b0
+#define DDRC_ECCUSYN2_0 0x3d4000b4
+#define DDRC_ECCPOISONADDR0_0 0x3d4000b8
+#define DDRC_ECCPOISONADDR1_0 0x3d4000bc
+#define DDRC_CRCPARCTL0_0 0x3d4000c0
+#define DDRC_CRCPARCTL1_0 0x3d4000c4
+#define DDRC_CRCPARCTL2_0 0x3d4000c8
+#define DDRC_CRCPARSTAT_0 0x3d4000cc
+#define DDRC_INIT0_0 0x3d4000d0
+#define DDRC_INIT1_0 0x3d4000d4
+#define DDRC_INIT2_0 0x3d4000d8
+#define DDRC_INIT3_0 0x3d4000dc
+#define DDRC_INIT4_0 0x3d4000e0
+#define DDRC_INIT5_0 0x3d4000e4
+#define DDRC_INIT6_0 0x3d4000e8
+#define DDRC_INIT7_0 0x3d4000ec
+#define DDRC_DIMMCTL_0 0x3d4000f0
+#define DDRC_RANKCTL_0 0x3d4000f4
+#define DDRC_DRAMTMG0_0 0x3d400100
+#define DDRC_DRAMTMG1_0 0x3d400104
+#define DDRC_DRAMTMG2_0 0x3d400108
+#define DDRC_DRAMTMG3_0 0x3d40010c
+#define DDRC_DRAMTMG4_0 0x3d400110
+#define DDRC_DRAMTMG5_0 0x3d400114
+#define DDRC_DRAMTMG6_0 0x3d400118
+#define DDRC_DRAMTMG7_0 0x3d40011c
+#define DDRC_DRAMTMG8_0 0x3d400120
+#define DDRC_DRAMTMG9_0 0x3d400124
+#define DDRC_DRAMTMG10_0 0x3d400128
+#define DDRC_DRAMTMG11_0 0x3d40012c
+#define DDRC_DRAMTMG12_0 0x3d400130
+#define DDRC_DRAMTMG13_0 0x3d400134
+#define DDRC_DRAMTMG14_0 0x3d400138
+#define DDRC_DRAMTMG15_0 0x3d40013C
+#define DDRC_DRAMTMG16_0 0x3d400140
+#define DDRC_DRAMTMG17_0 0x3d400144
+
+#define DDRC_ZQCTL0_0 0x3d400180
+#define DDRC_ZQCTL1_0 0x3d400184
+#define DDRC_ZQCTL2_0 0x3d400188
+#define DDRC_ZQSTAT_0 0x3d40018c
+#define DDRC_DFITMG0_0 0x3d400190
+#define DDRC_DFITMG1_0 0x3d400194
+#define DDRC_DFILPCFG0_0 0x3d400198
+#define DDRC_DFILPCFG1_0 0x3d40019c
+#define DDRC_DFIUPD0_0 0x3d4001a0
+#define DDRC_DFIUPD1_0 0x3d4001a4
+#define DDRC_DFIUPD2_0 0x3d4001a8
+
+#define DDRC_DFIMISC_0 0x3d4001b0
+#define DDRC_DFITMG2_0 0x3d4001b4
+#define DDRC_DFITMG3_0 0x3d4001b8
+#define DDRC_DFISTAT_0 0x3d4001bc
+
+#define DDRC_DBICTL_0 0x3d4001c0
+#define DDRC_DFIPHYMSTR_0 0x3d4001c4
+#define DDRC_TRAINCTL0_0 0x3d4001d0
+#define DDRC_TRAINCTL1_0 0x3d4001d4
+#define DDRC_TRAINCTL2_0 0x3d4001d8
+#define DDRC_TRAINSTAT_0 0x3d4001dc
+#define DDRC_ADDRMAP0_0 0x3d400200
+#define DDRC_ADDRMAP1_0 0x3d400204
+#define DDRC_ADDRMAP2_0 0x3d400208
+#define DDRC_ADDRMAP3_0 0x3d40020c
+#define DDRC_ADDRMAP4_0 0x3d400210
+#define DDRC_ADDRMAP5_0 0x3d400214
+#define DDRC_ADDRMAP6_0 0x3d400218
+#define DDRC_ADDRMAP7_0 0x3d40021c
+#define DDRC_ADDRMAP8_0 0x3d400220
+#define DDRC_ADDRMAP9_0 0x3d400224
+#define DDRC_ADDRMAP10_0 0x3d400228
+#define DDRC_ADDRMAP11_0 0x3d40022c
+
+#define DDRC_ODTCFG_0 0x3d400240
+#define DDRC_ODTMAP_0 0x3d400244
+#define DDRC_SCHED_0 0x3d400250
+#define DDRC_SCHED1_0 0x3d400254
+#define DDRC_PERFHPR1_0 0x3d40025c
+#define DDRC_PERFLPR1_0 0x3d400264
+#define DDRC_PERFWR1_0 0x3d40026c
+#define DDRC_PERFVPR1_0 0x3d400274
+
+#define DDRC_PERFVPW1_0 0x3d400278
+
+#define DDRC_DQMAP0_0 0x3d400280
+#define DDRC_DQMAP1_0 0x3d400284
+#define DDRC_DQMAP2_0 0x3d400288
+#define DDRC_DQMAP3_0 0x3d40028c
+#define DDRC_DQMAP4_0 0x3d400290
+#define DDRC_DQMAP5_0 0x3d400294
+#define DDRC_DBG0_0 0x3d400300
+#define DDRC_DBG1_0 0x3d400304
+#define DDRC_DBGCAM_0 0x3d400308
+#define DDRC_DBGCMD_0 0x3d40030c
+#define DDRC_DBGSTAT_0 0x3d400310
+
+#define DDRC_SWCTL_0 0x3d400320
+#define DDRC_SWSTAT_0 0x3d400324
+#define DDRC_OCPARCFG0_0 0x3d400330
+#define DDRC_OCPARCFG1_0 0x3d400334
+#define DDRC_OCPARCFG2_0 0x3d400338
+#define DDRC_OCPARCFG3_0 0x3d40033c
+#define DDRC_OCPARSTAT0_0 0x3d400340
+#define DDRC_OCPARSTAT1_0 0x3d400344
+#define DDRC_OCPARWLOG0_0 0x3d400348
+#define DDRC_OCPARWLOG1_0 0x3d40034c
+#define DDRC_OCPARWLOG2_0 0x3d400350
+#define DDRC_OCPARAWLOG0_0 0x3d400354
+#define DDRC_OCPARAWLOG1_0 0x3d400358
+#define DDRC_OCPARRLOG0_0 0x3d40035c
+#define DDRC_OCPARRLOG1_0 0x3d400360
+#define DDRC_OCPARARLOG0_0 0x3d400364
+#define DDRC_OCPARARLOG1_0 0x3d400368
+#define DDRC_POISONCFG_0 0x3d40036C
+#define DDRC_POISONSTAT_0 0x3d400370
+#define DDRC_ADVECCINDEX_0 0x3d400003
+#define DDRC_ADVECCSTAT_0 0x3d400003
+#define DDRC_ECCPOISONPAT0_0 0x3d400003
+#define DDRC_ECCPOISONPAT1_0 0x3d400003
+#define DDRC_ECCPOISONPAT2_0 0x3d400003
+#define DDRC_HIFCTL_0 0x3d400003
+
+#define DDRC_PSTAT_0 0x3d4003fc
+#define DDRC_PCCFG_0 0x3d400400
+#define DDRC_PCFGR_0_0 0x3d400404
+#define DDRC_PCFGR_1_0 0x3d4004b4
+#define DDRC_PCFGR_2_0 0x3d400564
+#define DDRC_PCFGR_3_0 0x3d400614
+#define DDRC_PCFGW_0_0 0x3d400408
+#define DDRC_PCFGW_1_0 0x3d400408
+#define DDRC_PCFGW_2_0 0x3d400568
+#define DDRC_PCFGW_3_0 0x3d400618
+#define DDRC_PCFGC_0_0 0x3d40040c
+#define DDRC_PCFGIDMASKCH_0 0x3d400410
+#define DDRC_PCFGIDVALUECH_0 0x3d400414
+#define DDRC_PCTRL_0_0 0x3d400490
+#define DDRC_PCTRL_1_0 0x3d400540
+#define DDRC_PCTRL_2_0 0x3d4005f0
+#define DDRC_PCTRL_3_0 0x3d4006a0
+#define DDRC_PCFGQOS0_0_0 0x3d400494
+#define DDRC_PCFGQOS1_0_0 0x3d400498
+#define DDRC_PCFGWQOS0_0_0 0x3d40049c
+#define DDRC_PCFGWQOS1_0_0 0x3d4004a0
+#define DDRC_SARBASE0_0 0x3d400f04
+#define DDRC_SARSIZE0_0 0x3d400f08
+#define DDRC_SBRCTL_0 0x3d400f24
+#define DDRC_SBRSTAT_0 0x3d400f28
+#define DDRC_SBRWDATA0_0 0x3d400f2c
+#define DDRC_SBRWDATA1_0 0x3d400f30
+#define DDRC_PDCH_0 0x3d400f34
+
+#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
+#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
+#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
+#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
+#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
+#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
+#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
+#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
+#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
+#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
+#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
+#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
+#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
+#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
+#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
+#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
+#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
+#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
+#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
+#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
+#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
+#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
+#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
+#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
+#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
+#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
+#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
+#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
+#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
+#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
+#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
+#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
+#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
+#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
+#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
+#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
+#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
+#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
+#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
+#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
+#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
+#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
+#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
+#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
+#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
+#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
+#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
+#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
+#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
+#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
+#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
+#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
+#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
+#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
+#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
+#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
+#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
+#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
+#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
+#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
+#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
+#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
+#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
+#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
+#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
+#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
+#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
+#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
+#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
+#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
+#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
+#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
+
+#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
+#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
+#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
+#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
+#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
+#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
+#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
+#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
+#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
+#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
+#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
+
+#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
+#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
+#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
+#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
+
+#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
+#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
+#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
+#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
+#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
+#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
+#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
+#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
+#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
+#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
+#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
+#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
+#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
+#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
+#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
+#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
+#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
+#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
+
+#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
+#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
+#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
+#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
+#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
+#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
+#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
+#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
+
+#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
+
+#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
+#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
+#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
+#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
+#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
+#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
+#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
+#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
+#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
+#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
+#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
+
+#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
+#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
+#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
+#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
+#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
+#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
+#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
+#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
+#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
+#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
+#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
+#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
+#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
+#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
+#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
+#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
+#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
+#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
+#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
+#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+
+#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
+#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
+#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
+#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
+#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
+#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
+#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
+#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
+#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
+#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
+#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
+#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
+#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
+#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
+#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
+#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
+#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
+#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
+#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
+#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
+#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
+#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
+#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
+#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
+#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
+#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
+#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
+#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
+
+#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
+#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
+#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
+#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
+#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
+#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
+#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
+#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
+#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
+#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
+#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
+#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
+#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
+#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
+#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
+#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
+#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
+#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
+#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
+#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
+#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
+#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
+#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
+#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
+#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
+#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
+#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
+#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
+#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
+#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
+#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
+#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
+#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
+#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
+#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
+#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
+#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
+#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
+#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
+#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
+#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
+#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
+#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
+#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
+#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
+#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
+#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
+#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
+#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
+#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
+#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
+#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
+#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
+#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
+#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
+#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
+#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
+#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
+#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
+
+#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
+#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
+#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
+#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
+#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
+#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
+#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
+#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
+#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
+#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
+#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
+#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
+#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
+#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
+#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
+#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
+#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
+#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
+#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
+#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
+#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
+#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
+#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
+#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
+#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+
+#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
+#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
+#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
+#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
+#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
+#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
+#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
+#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
+
+#endif
diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile
index 60c99d4194..286396ee96 100644
--- a/board/freescale/mx8mq_evk/Makefile
+++ b/board/freescale/mx8mq_evk/Makefile
@@ -8,4 +8,5 @@ obj-y += mx8mq_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
+obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
endif
diff --git a/board/freescale/mx8mq_evk/ddr/ddr.h b/board/freescale/mx8mq_evk/ddr/ddr.h
new file mode 100644
index 0000000000..bf5aeae801
--- /dev/null
+++ b/board/freescale/mx8mq_evk/ddr/ddr.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ddr_memory_map.h>
+
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+void ddr_init(void);
+void ddr_load_train_code(enum fw_type type);
+void lpddr4_800M_cfg_phy(void);
+void dram_pll_init(void);
+void wait_ddrphy_training_complete(void);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline uint32_t reg32_read(unsigned long addr)
+{
+ return readl(addr);
+}
+
+static inline void dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+ setbits_le32(addr, (1 << bit));
+}
diff --git a/board/freescale/mx8mq_evk/ddr/ddr_init.c b/board/freescale/mx8mq_evk/ddr/ddr_init.c
new file mode 100644
index 0000000000..6a31d1be60
--- /dev/null
+++ b/board/freescale/mx8mq_evk/ddr/ddr_init.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include "ddr.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "wait_ddrphy_training_complete.c"
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR ((SRC_IPS_BASE_ADDR) + 0x1000)
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+#define SILICON_TRAIN
+
+volatile unsigned int tmp, tmp_t, i;
+void lpddr4_800mhz_cfg_umctl2(void)
+{
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000304, 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000030, 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000000, 0x83080020);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000064, 0x006180e0);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d0, 0xc003061B);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d4, 0x009D0000);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d8, 0x0000fe05);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000dc, 0x00d4002d);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e0, 0x00310008);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e4, 0x00040009);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e8, 0x0046004d);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000ec, 0x0005004d);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000f4, 0x00000979);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000100, 0x1a203522);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000104, 0x00060630);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000108, 0x070e1214);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000010c, 0x00b0c006);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000110, 0x0f04080f);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000114, 0x0d0d0c0c);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000118, 0x01010007);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000011c, 0x0000060a);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000120, 0x01010101);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000124, 0x40000008);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000128, 0x00050d01);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000012c, 0x01010008);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000130, 0x00020000);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000134, 0x18100002);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000138, 0x00000dc2);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000013c, 0x80000000);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000144, 0x00a00050);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000180, 0x53200018);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000184, 0x02800070);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000188, 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000190, 0x0397820a);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00002190, 0x0397820a);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00003190, 0x0397820a);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000194, 0x00020103);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a0, 0xe0400018);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a4, 0x00df00e4);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a8, 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b0, 0x00000011);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b4, 0x0000170a);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c0, 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c4, 0x00000000);
+ /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+ dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
+ dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
+ /* bank interleave */
+ dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808);
+ dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
+ dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000240, 0x020f0c54);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000244, 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000490, 0x00000001);
+
+ /* performance setting */
+ dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
+ dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
+ dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
+ dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
+ dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x900093e7);
+ dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
+ dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
+ dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
+ dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
+ dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
+ dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
+ dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
+ dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
+ dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
+ dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
+}
+
+void lpddr4_100mhz_cfg_umctl2(void)
+{
+ reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
+ reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
+ reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
+ reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
+ reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
+ reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
+ reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
+ reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
+ reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
+ reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
+ reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
+ reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
+ reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
+ reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
+ reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
+ reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
+ reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
+ reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
+ reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
+ reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
+ reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
+}
+
+void lpddr4_25mhz_cfg_umctl2(void)
+{
+ reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
+ reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
+ reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
+ reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
+ reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
+ reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
+ reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
+ reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
+ reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
+ reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
+ reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
+ reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
+ reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
+ reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
+ reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
+ reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
+ reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
+ reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
+ reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
+ reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
+ reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
+}
+
+static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+void ddr_init(void)
+{
+ /* change the clock source of dram_apb_clk_root */
+ writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
+ writel((0x4 << 24) | (0x3 << 16), &ccm_reg->ip_root[1].target_root_set);
+
+ /* disable the clock gating */
+ reg32_write(0x303A00EC, 0x0000ffff);
+ reg32setbit(0x303A00F8, 5);
+ reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+
+ dram_pll_init();
+
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+ /* Configure uMCTL2's registers */
+ lpddr4_800mhz_cfg_umctl2();
+
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+ reg32_write(DDRC_DBG1(0), 0x00000000);
+ tmp = reg32_read(DDRC_PWRCTL(0));
+ reg32_write(DDRC_PWRCTL(0), 0x000000a8);
+ /* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */
+ reg32_write(DDRC_SWCTL(0), 0x00000000);
+ reg32_write(DDRC_DDR_SS_GPR0, 0x01);
+ reg32_write(DDRC_DFIMISC(0), 0x00000010);
+
+ /* Configure LPDDR4 PHY's registers */
+ lpddr4_800M_cfg_phy();
+
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+ /*
+ * ------------------- 9 -------------------
+ * Set DFIMISC.dfi_init_start to 1
+ * -----------------------------------------
+ */
+ reg32_write(DDRC_DFIMISC(0), 0x00000030);
+ reg32_write(DDRC_SWCTL(0), 0x0001);
+
+ /* wait DFISTAT.dfi_init_complete to 1 */
+ tmp_t = 0;
+ while (tmp_t == 0) {
+ tmp = reg32_read(DDRC_DFISTAT(0));
+ tmp_t = tmp & 0x01;
+ tmp = reg32_read(DDRC_MRSTAT(0));
+ }
+
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+
+ /* clear DFIMISC.dfi_init_complete_en */
+ reg32_write(DDRC_DFIMISC(0), 0x00000010);
+ reg32_write(DDRC_DFIMISC(0), 0x00000011);
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+ /*
+ * set SWCTL.sw_done to enable quasi-dynamic register
+ * programming outside reset.
+ */
+ reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+ /* wait SWSTAT.sw_done_ack to 1 */
+ while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+ ;
+
+ /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+ while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
+ ;
+
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+ /* reg32_write(DDRC_PWRCTL(0), 0x018a); */
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+ /* enable port 0 */
+ reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+
+ reg32_write(DDRC_SWCTL(0), 0x0);
+ lpddr4_100mhz_cfg_umctl2();
+ lpddr4_25mhz_cfg_umctl2();
+ reg32_write(DDRC_SWCTL(0), 0x1);
+
+ /* wait SWSTAT.sw_done_ack to 1 */
+ while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+ ;
+
+ reg32_write(DDRC_SWCTL(0), 0x0);
+}
diff --git a/board/freescale/mx8mq_evk/ddr/ddrphy_train.c b/board/freescale/mx8mq_evk/ddr/ddrphy_train.c
new file mode 100644
index 0000000000..1bf88a8837
--- /dev/null
+++ b/board/freescale/mx8mq_evk/ddr/ddrphy_train.c
@@ -0,0 +1,1147 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include "ddr.h"
+
+static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+void ddr_pll_bypass_100mts(void)
+{
+ /* change the clock source of dram_alt_clk_root to source 2 --100MHZ */
+ writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[0].target_root_clr);
+ writel((0x2 << 24), &ccm_reg->ip_root[0].target_root_set);
+
+ /* change the clock source of dram_apb_clk_root to source 2 --40MHZ */
+ writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
+ writel((0x2 << 24) | (0x1 << 16), &ccm_reg->ip_root[1].target_root_set);
+
+ /* disable the clock gating */
+ reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
+ reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
+
+ /* configure pll bypass mode */
+ reg32_write(0x30389804, 1 << 24);
+
+ printf("PLL bypass to 100MTS setting done\n");
+}
+
+void ddr_pll_bypass_400mts(void)
+{
+ /* change the clock source of dram_alt_clk_root to source 2 --400MHZ */
+ writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[0].target_root_clr);
+ writel((0x5 << 24), &ccm_reg->ip_root[0].target_root_set);
+
+ /* change the clock source of dram_apb_clk_root to source 2 --40MHZ/2 */
+ writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
+ writel((0x2 << 24) | (0x1 << 16), &ccm_reg->ip_root[1].target_root_set);
+
+ /* disable the clock gating */
+ reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
+ reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
+
+ /* configure pll bypass mode */
+ reg32_write(0x30389804, 1 << 24);
+
+ printf("PLL bypass to 400MTS setting done\n");
+}
+
+void dwc_ddrphy_phyinit_usercustom_e_setdficlk(int pstate)
+{
+ if (pstate == 2) {
+ ddr_pll_bypass_100mts();
+ } else if (pstate == 1) {
+ ddr_pll_bypass_400mts();
+ } else {
+ writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
+ writel((0x4 << 24) | (0x3 << 16), &ccm_reg->ip_root[1].target_root_set);
+ reg32_write(0x30389808, 1 << 24);
+ }
+}
+
+void lpddr4_800M_cfg_phy(void)
+{
+ unsigned int tmp, tmp_t;
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xab);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xab);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xab);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xe38);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x21);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0x64);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x19c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x19c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x19c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x660);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5555);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x65);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0xd);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0xfb);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ /* load the 1D training image */
+ ddr_load_train_code(FW_1D_IMAGE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* set the PHY input clock to the desired frequency for pstate 2 */
+ dwc_ddrphy_phyinit_usercustom_e_setdficlk(2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x102);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x64);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x3100);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x3100);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ wait_ddrphy_training_complete();
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* set the PHY input clock to the desired frequency for pstate 1 */
+ dwc_ddrphy_phyinit_usercustom_e_setdficlk(1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x190);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x3100);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x3100);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ wait_ddrphy_training_complete();
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* set the PHY input clock to the desired frequency for pstate 0 */
+ dwc_ddrphy_phyinit_usercustom_e_setdficlk(0);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ wait_ddrphy_training_complete();
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ /* load the 2D training image */
+ ddr_load_train_code(FW_2D_IMAGE);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x61);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x100);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x100);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x1f7f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x084d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x084d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ /* Execute the Training Firmware */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ /* wait for 2D training complete */
+ wait_ddrphy_training_complete();
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* (I) Load PHY Init Engine Image */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4016);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4004);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x11a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x2a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7b2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x2a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x370);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x3c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x199);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x11a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x199);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x8568);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x1d8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x70);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x788);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x1ff8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x85a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x1e8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x50);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x798);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x7a0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x8310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0xa310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x6e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x8310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0xa310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x1ff8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x85a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x1e8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0x798);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x78);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x7a0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x8b10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0xab10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x58);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x8b10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0xab10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x1d8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x6a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x1e9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x8080);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x8080);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x6a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8568);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0xb7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x1d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x3c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x370);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x20);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x2aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x10e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x8140);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0x8138);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0x47);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0x618);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0x8140);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x000d0000, 0x0);
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x6a);
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x1);
+ /*
+ * CalBusy.0 =1, indicates the calibrator is actively calibrating.
+ * Wait Calibrating done.
+ */
+ tmp_t = 1;
+ while (tmp_t) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097);
+ tmp_t = tmp & 0x01;
+ }
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
+}
diff --git a/board/freescale/mx8mq_evk/ddr/helper.c b/board/freescale/mx8mq_evk/ddr/helper.c
new file mode 100644
index 0000000000..b58e47be89
--- /dev/null
+++ b/board/freescale/mx8mq_evk/ddr/helper.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768
+#define DMEM_LEN 16384
+#define IMEM_2D_OFFSET 49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_code(enum fw_type type)
+{
+ u32 tmp32, i;
+ u32 error = 0;
+ unsigned long pr_to32, pr_from32;
+ unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+ unsigned long imem_start = (unsigned long)&_end + fw_offset;
+ unsigned long dmem_start = imem_start + IMEM_LEN;
+
+ pr_from32 = imem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ for (i = 0x0; i < IMEM_LEN; ) {
+ tmp32 = readl(pr_from32);
+ writew(tmp32 & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ pr_from32 += 4;
+ i += 4;
+ }
+
+ pr_from32 = dmem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ for (i = 0x0; i < DMEM_LEN;) {
+ tmp32 = readl(pr_from32);
+ writew(tmp32 & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ pr_from32 += 4;
+ i += 4;
+ }
+
+ printf("check ddr4_pmu_train_imem code\n");
+ pr_from32 = imem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ for (i = 0x0; i < IMEM_LEN;) {
+ tmp32 = (readw(pr_to32) & 0x0000ffff);
+ pr_to32 += 4;
+ tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+ if (tmp32 != readl(pr_from32)) {
+ printf("%lx %lx\n", pr_from32, pr_to32);
+ error++;
+ }
+ pr_from32 += 4;
+ pr_to32 += 4;
+ i += 4;
+ }
+ if (error)
+ printf("check ddr4_pmu_train_imem code fail=%d\n", error);
+ else
+ printf("check ddr4_pmu_train_imem code pass\n");
+
+ printf("check ddr4_pmu_train_dmem code\n");
+ pr_from32 = dmem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ for (i = 0x0; i < DMEM_LEN;) {
+ tmp32 = (readw(pr_to32) & 0x0000ffff);
+ pr_to32 += 4;
+ tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+ if (tmp32 != readl(pr_from32)) {
+ printf("%lx %lx\n", pr_from32, pr_to32);
+ error++;
+ }
+ pr_from32 += 4;
+ pr_to32 += 4;
+ i += 4;
+ }
+
+ if (error)
+ printf("check ddr4_pmu_train_dmem code fail=%d", error);
+ else
+ printf("check ddr4_pmu_train_dmem code pass\n");
+}
diff --git a/board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c b/board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c
new file mode 100644
index 0000000000..a4eabf0b90
--- /dev/null
+++ b/board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+static inline void poll_pmu_message_ready(void)
+{
+ unsigned int reg;
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
+ } while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_receive(void)
+{
+ unsigned int reg;
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
+ } while (!(reg & 0x1));
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+ unsigned int reg;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
+
+ ack_pmu_message_receive();
+
+ return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+ unsigned int reg, reg2;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
+
+ reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
+
+ reg2 = (reg2 << 16) | reg;
+
+ ack_pmu_message_receive();
+
+ return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+ ddr_printf("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+ unsigned int string_index, arg __maybe_unused;
+ int i = 0;
+
+ string_index = get_stream_message();
+ ddr_printf(" PMU String index = 0x%08x\n", string_index);
+ while (i < (string_index & 0xffff)) {
+ arg = get_stream_message();
+ ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
+ i++;
+ }
+
+ ddr_printf("\n");
+}
+
+void wait_ddrphy_training_complete(void)
+{
+ unsigned int mail;
+
+ while (1) {
+ mail = get_mail();
+ decode_major_message(mail);
+ if (mail == 0x08) {
+ decode_streaming_message();
+ } else if (mail == 0x07) {
+ printf("Training PASS\n");
+ break;
+ } else if (mail == 0xff) {
+ printf("Training FAILED\n");
+ break;
+ }
+ }
+}
--
2.14.1
^ permalink raw reply related [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 23/23] Add DDR settings
2017-12-04 4:31 ` [U-Boot] [PATCH V2 23/23] Add DDR settings Peng Fan
@ 2017-12-04 17:48 ` Dr. Philipp Tomsich
2017-12-07 7:31 ` Peng Fan
0 siblings, 1 reply; 65+ messages in thread
From: Dr. Philipp Tomsich @ 2017-12-04 17:48 UTC (permalink / raw)
To: u-boot
> On 4 Dec 2017, at 05:31, Peng Fan <peng.fan@nxp.com> wrote:
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/include/asm/arch-mx8m/ddr_memory_map.h | 495 +++++++++
> board/freescale/mx8mq_evk/Makefile | 1 +
> board/freescale/mx8mq_evk/ddr/ddr.h | 38 +
> board/freescale/mx8mq_evk/ddr/ddr_init.c | 256 +++++
> board/freescale/mx8mq_evk/ddr/ddrphy_train.c | 1147 ++++++++++++++++++++
> board/freescale/mx8mq_evk/ddr/helper.c | 101 ++
> .../mx8mq_evk/ddr/wait_ddrphy_training_complete.c | 97 ++
> 7 files changed, 2135 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-mx8m/ddr_memory_map.h
> create mode 100644 board/freescale/mx8mq_evk/ddr/ddr.h
> create mode 100644 board/freescale/mx8mq_evk/ddr/ddr_init.c
> create mode 100644 board/freescale/mx8mq_evk/ddr/ddrphy_train.c
> create mode 100644 board/freescale/mx8mq_evk/ddr/helper.c
> create mode 100644 board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c
>
> diff --git a/arch/arm/include/asm/arch-mx8m/ddr_memory_map.h b/arch/arm/include/asm/arch-mx8m/ddr_memory_map.h
> new file mode 100644
> index 0000000000..e0e5c30301
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx8m/ddr_memory_map.h
> @@ -0,0 +1,495 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_MX8M_DDR_H
> +#define __ASM_ARCH_MX8M_DDR_H
> +
> +#define DDRC_DDR_SS_GPR0 0x3d000000
> +
> +#define DDRC_IPS_BASE_ADDR_0 0x3f400000
> +
> +#define DDRC_MSTR_0 0x3d400000
> +#define DDRC_STAT_0 0x3d400004
> +#define DDRC_MSTR1_0 0x3d400008
> +#define DDRC_MRCTRL0_0 0x3d400010
> +#define DDRC_MRCTRL1_0 0x3d400014
> +#define DDRC_MRSTAT_0 0x3d400018
> +#define DDRC_MRCTRL2_0 0x3d40001c
> +#define DDRC_DERATEEN_0 0x3d400020
> +#define DDRC_DERATEINT_0 0x3d400024
> +#define DDRC_MSTR2_0 0x3d400028
> +#define DDRC_PWRCTL_0 0x3d400030
> +#define DDRC_PWRTMG_0 0x3d400034
> +#define DDRC_HWLPCTL_0 0x3d400038
> +#define DDRC_HWFFCCTL_0 0x3d40003c
> +#define DDRC_HWFFCSTAT_0 0x3d400040
> +#define DDRC_RFSHCTL0_0 0x3d400050
> +#define DDRC_RFSHCTL1_0 0x3d400054
> +#define DDRC_RFSHCTL2_0 0x3d400058
> +#define DDRC_RFSHCTL3_0 0x3d400060
> +#define DDRC_RFSHTMG_0 0x3d400064
> +#define DDRC_ECCCFG0_0 0x3d400070
> +#define DDRC_ECCCFG1_0 0x3d400074
> +#define DDRC_ECCSTAT_0 0x3d400078
> +#define DDRC_ECCCLR_0 0x3d40007c
> +#define DDRC_ECCERRCNT_0 0x3d400080
> +#define DDRC_ECCCADDR0_0 0x3d400084
> +#define DDRC_ECCCADDR1_0 0x3d400088
> +#define DDRC_ECCCSYN0_0 0x3d40008c
> +#define DDRC_ECCCSYN1_0 0x3d400090
> +#define DDRC_ECCCSYN2_0 0x3d400094
> +#define DDRC_ECCBITMASK0_0 0x3d400098
> +#define DDRC_ECCBITMASK1_0 0x3d40009c
> +#define DDRC_ECCBITMASK2_0 0x3d4000a0
> +#define DDRC_ECCUADDR0_0 0x3d4000a4
> +#define DDRC_ECCUADDR1_0 0x3d4000a8
> +#define DDRC_ECCUSYN0_0 0x3d4000ac
> +#define DDRC_ECCUSYN1_0 0x3d4000b0
> +#define DDRC_ECCUSYN2_0 0x3d4000b4
> +#define DDRC_ECCPOISONADDR0_0 0x3d4000b8
> +#define DDRC_ECCPOISONADDR1_0 0x3d4000bc
> +#define DDRC_CRCPARCTL0_0 0x3d4000c0
> +#define DDRC_CRCPARCTL1_0 0x3d4000c4
> +#define DDRC_CRCPARCTL2_0 0x3d4000c8
> +#define DDRC_CRCPARSTAT_0 0x3d4000cc
> +#define DDRC_INIT0_0 0x3d4000d0
> +#define DDRC_INIT1_0 0x3d4000d4
> +#define DDRC_INIT2_0 0x3d4000d8
> +#define DDRC_INIT3_0 0x3d4000dc
> +#define DDRC_INIT4_0 0x3d4000e0
> +#define DDRC_INIT5_0 0x3d4000e4
> +#define DDRC_INIT6_0 0x3d4000e8
> +#define DDRC_INIT7_0 0x3d4000ec
> +#define DDRC_DIMMCTL_0 0x3d4000f0
> +#define DDRC_RANKCTL_0 0x3d4000f4
> +#define DDRC_DRAMTMG0_0 0x3d400100
> +#define DDRC_DRAMTMG1_0 0x3d400104
> +#define DDRC_DRAMTMG2_0 0x3d400108
> +#define DDRC_DRAMTMG3_0 0x3d40010c
> +#define DDRC_DRAMTMG4_0 0x3d400110
> +#define DDRC_DRAMTMG5_0 0x3d400114
> +#define DDRC_DRAMTMG6_0 0x3d400118
> +#define DDRC_DRAMTMG7_0 0x3d40011c
> +#define DDRC_DRAMTMG8_0 0x3d400120
> +#define DDRC_DRAMTMG9_0 0x3d400124
> +#define DDRC_DRAMTMG10_0 0x3d400128
> +#define DDRC_DRAMTMG11_0 0x3d40012c
> +#define DDRC_DRAMTMG12_0 0x3d400130
> +#define DDRC_DRAMTMG13_0 0x3d400134
> +#define DDRC_DRAMTMG14_0 0x3d400138
> +#define DDRC_DRAMTMG15_0 0x3d40013C
> +#define DDRC_DRAMTMG16_0 0x3d400140
> +#define DDRC_DRAMTMG17_0 0x3d400144
> +
> +#define DDRC_ZQCTL0_0 0x3d400180
> +#define DDRC_ZQCTL1_0 0x3d400184
> +#define DDRC_ZQCTL2_0 0x3d400188
> +#define DDRC_ZQSTAT_0 0x3d40018c
> +#define DDRC_DFITMG0_0 0x3d400190
> +#define DDRC_DFITMG1_0 0x3d400194
> +#define DDRC_DFILPCFG0_0 0x3d400198
> +#define DDRC_DFILPCFG1_0 0x3d40019c
> +#define DDRC_DFIUPD0_0 0x3d4001a0
> +#define DDRC_DFIUPD1_0 0x3d4001a4
> +#define DDRC_DFIUPD2_0 0x3d4001a8
> +
> +#define DDRC_DFIMISC_0 0x3d4001b0
> +#define DDRC_DFITMG2_0 0x3d4001b4
> +#define DDRC_DFITMG3_0 0x3d4001b8
> +#define DDRC_DFISTAT_0 0x3d4001bc
> +
> +#define DDRC_DBICTL_0 0x3d4001c0
> +#define DDRC_DFIPHYMSTR_0 0x3d4001c4
> +#define DDRC_TRAINCTL0_0 0x3d4001d0
> +#define DDRC_TRAINCTL1_0 0x3d4001d4
> +#define DDRC_TRAINCTL2_0 0x3d4001d8
> +#define DDRC_TRAINSTAT_0 0x3d4001dc
> +#define DDRC_ADDRMAP0_0 0x3d400200
> +#define DDRC_ADDRMAP1_0 0x3d400204
> +#define DDRC_ADDRMAP2_0 0x3d400208
> +#define DDRC_ADDRMAP3_0 0x3d40020c
> +#define DDRC_ADDRMAP4_0 0x3d400210
> +#define DDRC_ADDRMAP5_0 0x3d400214
> +#define DDRC_ADDRMAP6_0 0x3d400218
> +#define DDRC_ADDRMAP7_0 0x3d40021c
> +#define DDRC_ADDRMAP8_0 0x3d400220
> +#define DDRC_ADDRMAP9_0 0x3d400224
> +#define DDRC_ADDRMAP10_0 0x3d400228
> +#define DDRC_ADDRMAP11_0 0x3d40022c
> +
> +#define DDRC_ODTCFG_0 0x3d400240
> +#define DDRC_ODTMAP_0 0x3d400244
> +#define DDRC_SCHED_0 0x3d400250
> +#define DDRC_SCHED1_0 0x3d400254
> +#define DDRC_PERFHPR1_0 0x3d40025c
> +#define DDRC_PERFLPR1_0 0x3d400264
> +#define DDRC_PERFWR1_0 0x3d40026c
> +#define DDRC_PERFVPR1_0 0x3d400274
> +
> +#define DDRC_PERFVPW1_0 0x3d400278
> +
> +#define DDRC_DQMAP0_0 0x3d400280
> +#define DDRC_DQMAP1_0 0x3d400284
> +#define DDRC_DQMAP2_0 0x3d400288
> +#define DDRC_DQMAP3_0 0x3d40028c
> +#define DDRC_DQMAP4_0 0x3d400290
> +#define DDRC_DQMAP5_0 0x3d400294
> +#define DDRC_DBG0_0 0x3d400300
> +#define DDRC_DBG1_0 0x3d400304
> +#define DDRC_DBGCAM_0 0x3d400308
> +#define DDRC_DBGCMD_0 0x3d40030c
> +#define DDRC_DBGSTAT_0 0x3d400310
> +
> +#define DDRC_SWCTL_0 0x3d400320
> +#define DDRC_SWSTAT_0 0x3d400324
> +#define DDRC_OCPARCFG0_0 0x3d400330
> +#define DDRC_OCPARCFG1_0 0x3d400334
> +#define DDRC_OCPARCFG2_0 0x3d400338
> +#define DDRC_OCPARCFG3_0 0x3d40033c
> +#define DDRC_OCPARSTAT0_0 0x3d400340
> +#define DDRC_OCPARSTAT1_0 0x3d400344
> +#define DDRC_OCPARWLOG0_0 0x3d400348
> +#define DDRC_OCPARWLOG1_0 0x3d40034c
> +#define DDRC_OCPARWLOG2_0 0x3d400350
> +#define DDRC_OCPARAWLOG0_0 0x3d400354
> +#define DDRC_OCPARAWLOG1_0 0x3d400358
> +#define DDRC_OCPARRLOG0_0 0x3d40035c
> +#define DDRC_OCPARRLOG1_0 0x3d400360
> +#define DDRC_OCPARARLOG0_0 0x3d400364
> +#define DDRC_OCPARARLOG1_0 0x3d400368
> +#define DDRC_POISONCFG_0 0x3d40036C
> +#define DDRC_POISONSTAT_0 0x3d400370
> +#define DDRC_ADVECCINDEX_0 0x3d400003
> +#define DDRC_ADVECCSTAT_0 0x3d400003
> +#define DDRC_ECCPOISONPAT0_0 0x3d400003
> +#define DDRC_ECCPOISONPAT1_0 0x3d400003
> +#define DDRC_ECCPOISONPAT2_0 0x3d400003
> +#define DDRC_HIFCTL_0 0x3d400003
> +
> +#define DDRC_PSTAT_0 0x3d4003fc
> +#define DDRC_PCCFG_0 0x3d400400
> +#define DDRC_PCFGR_0_0 0x3d400404
> +#define DDRC_PCFGR_1_0 0x3d4004b4
> +#define DDRC_PCFGR_2_0 0x3d400564
> +#define DDRC_PCFGR_3_0 0x3d400614
> +#define DDRC_PCFGW_0_0 0x3d400408
> +#define DDRC_PCFGW_1_0 0x3d400408
> +#define DDRC_PCFGW_2_0 0x3d400568
> +#define DDRC_PCFGW_3_0 0x3d400618
> +#define DDRC_PCFGC_0_0 0x3d40040c
> +#define DDRC_PCFGIDMASKCH_0 0x3d400410
> +#define DDRC_PCFGIDVALUECH_0 0x3d400414
> +#define DDRC_PCTRL_0_0 0x3d400490
> +#define DDRC_PCTRL_1_0 0x3d400540
> +#define DDRC_PCTRL_2_0 0x3d4005f0
> +#define DDRC_PCTRL_3_0 0x3d4006a0
> +#define DDRC_PCFGQOS0_0_0 0x3d400494
> +#define DDRC_PCFGQOS1_0_0 0x3d400498
> +#define DDRC_PCFGWQOS0_0_0 0x3d40049c
> +#define DDRC_PCFGWQOS1_0_0 0x3d4004a0
> +#define DDRC_SARBASE0_0 0x3d400f04
> +#define DDRC_SARSIZE0_0 0x3d400f08
> +#define DDRC_SBRCTL_0 0x3d400f24
> +#define DDRC_SBRSTAT_0 0x3d400f28
> +#define DDRC_SBRWDATA0_0 0x3d400f2c
> +#define DDRC_SBRWDATA1_0 0x3d400f30
> +#define DDRC_PDCH_0 0x3d400f34
> +
> +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
> +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
> +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
> +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
> +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
> +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
> +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
> +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
> +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
> +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
> +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
> +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
> +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
> +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
> +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
> +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
> +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
> +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
> +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
> +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
> +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
> +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
> +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
> +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
> +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
> +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
> +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
> +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
> +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
> +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
> +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
> +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
> +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
> +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
> +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
> +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
> +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
> +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
> +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
> +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
> +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
> +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
> +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
> +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
> +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
> +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
> +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
> +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
> +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
> +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
> +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
> +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
> +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
> +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
> +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
> +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
> +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
> +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
> +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
> +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
> +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
> +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
> +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
> +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
> +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
> +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
> +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
> +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
> +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
> +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
> +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
> +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
> +
> +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
> +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
> +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
> +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
> +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
> +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
> +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
> +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
> +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
> +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
> +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
> +
> +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
> +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
> +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
> +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
> +
> +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
> +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
> +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
> +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
> +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
> +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
> +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
> +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
> +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
> +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
> +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
> +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
> +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
> +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
> +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
> +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
> +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
> +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
> +
> +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
> +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
> +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
> +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
> +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
> +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
> +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
> +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
> +
> +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
> +
> +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
> +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
> +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
> +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
> +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
> +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
> +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
> +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
> +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
> +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
> +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
> +
> +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
> +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
> +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
> +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
> +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
> +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
> +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
> +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
> +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
> +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
> +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
> +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
> +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
> +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
> +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
> +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
> +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
> +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
> +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
> +#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
> +#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
> +#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
> +#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
> +#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
> +#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
> +
> +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
> +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
> +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
> +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
> +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
> +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
> +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
> +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
> +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
> +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
> +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
> +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
> +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
> +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
> +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
> +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
> +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
> +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
> +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
> +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
> +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
> +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
> +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
> +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
> +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
> +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
> +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
> +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
> +
> +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
> +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
> +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
> +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
> +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
> +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
> +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
> +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
> +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
> +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
> +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
> +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
> +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
> +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
> +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
> +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
> +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
> +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
> +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
> +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
> +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
> +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
> +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
> +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
> +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
> +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
> +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
> +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
> +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
> +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
> +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
> +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
> +
> +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
> +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
> +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
> +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
> +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
> +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
> +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
> +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
> +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
> +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
> +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
> +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
> +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
> +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
> +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
> +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
> +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
> +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
> +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
> +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
> +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
> +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
> +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
> +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
> +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
> +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
> +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
> +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
> +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
> +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
> +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
> +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
> +
> +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
> +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
> +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
> +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
> +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
> +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
> +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
> +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
> +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
> +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
> +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
> +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
> +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
> +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
> +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
> +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
> +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
> +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
> +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
> +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
> +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
> +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
> +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
> +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
> +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
> +
> +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
> +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
> +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
> +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
> +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
> +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
> +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
> +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
> +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
> +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
> +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
> +
> +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
> +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
This should use structure for I/O access.
Please refer to https://www.denx.de/wiki/U-Boot/CodingStyle for details.
Regards,
Philipp.
> +
> +#endif
> diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile
> index 60c99d4194..286396ee96 100644
> --- a/board/freescale/mx8mq_evk/Makefile
> +++ b/board/freescale/mx8mq_evk/Makefile
> @@ -8,4 +8,5 @@ obj-y += mx8mq_evk.o
>
> ifdef CONFIG_SPL_BUILD
> obj-y += spl.o
> +obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
> endif
> diff --git a/board/freescale/mx8mq_evk/ddr/ddr.h b/board/freescale/mx8mq_evk/ddr/ddr.h
> new file mode 100644
> index 0000000000..bf5aeae801
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/ddr/ddr.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/arch/ddr_memory_map.h>
> +
> +enum fw_type {
> + FW_1D_IMAGE,
> + FW_2D_IMAGE,
> +};
> +
> +void ddr_init(void);
> +void ddr_load_train_code(enum fw_type type);
> +void lpddr4_800M_cfg_phy(void);
> +void dram_pll_init(void);
> +void wait_ddrphy_training_complete(void);
> +
> +static inline void reg32_write(unsigned long addr, u32 val)
> +{
> + writel(val, addr);
> +}
> +
> +static inline uint32_t reg32_read(unsigned long addr)
> +{
> + return readl(addr);
> +}
> +
> +static inline void dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
> +{
> + writel(val, addr);
> +}
> +
> +static inline void reg32setbit(unsigned long addr, u32 bit)
> +{
> + setbits_le32(addr, (1 << bit));
> +}
> diff --git a/board/freescale/mx8mq_evk/ddr/ddr_init.c b/board/freescale/mx8mq_evk/ddr/ddr_init.c
> new file mode 100644
> index 0000000000..6a31d1be60
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/ddr/ddr_init.c
> @@ -0,0 +1,256 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include "ddr.h"
> +
> +#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
> +#define ddr_printf(args...) printf(args)
> +#else
> +#define ddr_printf(args...)
> +#endif
> +
> +#include "wait_ddrphy_training_complete.c"
> +#ifndef SRC_DDRC_RCR_ADDR
> +#define SRC_DDRC_RCR_ADDR ((SRC_IPS_BASE_ADDR) + 0x1000)
> +#endif
> +#ifndef DDR_CSD1_BASE_ADDR
> +#define DDR_CSD1_BASE_ADDR 0x40000000
> +#endif
> +#define SILICON_TRAIN
> +
> +volatile unsigned int tmp, tmp_t, i;
> +void lpddr4_800mhz_cfg_umctl2(void)
> +{
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000304, 0x00000001);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000030, 0x00000001);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000000, 0x83080020);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000064, 0x006180e0);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d0, 0xc003061B);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d4, 0x009D0000);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d8, 0x0000fe05);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000dc, 0x00d4002d);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e0, 0x00310008);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e4, 0x00040009);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e8, 0x0046004d);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000ec, 0x0005004d);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000f4, 0x00000979);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000100, 0x1a203522);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000104, 0x00060630);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000108, 0x070e1214);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000010c, 0x00b0c006);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000110, 0x0f04080f);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000114, 0x0d0d0c0c);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000118, 0x01010007);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000011c, 0x0000060a);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000120, 0x01010101);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000124, 0x40000008);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000128, 0x00050d01);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000012c, 0x01010008);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000130, 0x00020000);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000134, 0x18100002);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000138, 0x00000dc2);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000013c, 0x80000000);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000144, 0x00a00050);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000180, 0x53200018);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000184, 0x02800070);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000188, 0x00000000);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000190, 0x0397820a);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00002190, 0x0397820a);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00003190, 0x0397820a);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000194, 0x00020103);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a0, 0xe0400018);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a4, 0x00df00e4);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a8, 0x00000000);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b0, 0x00000011);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b4, 0x0000170a);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c0, 0x00000001);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c4, 0x00000000);
> + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
> + dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
> + dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
> + /* bank interleave */
> + dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808);
> + dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
> + dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000240, 0x020f0c54);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000244, 0x00000000);
> + dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000490, 0x00000001);
> +
> + /* performance setting */
> + dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
> + dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
> + dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
> + dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
> + dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
> + dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x900093e7);
> + dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
> + dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
> + dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
> + dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
> + dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
> + dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
> + dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
> + dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
> + dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
> + dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
> + dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
> + dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
> + dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
> + dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
> + dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
> + dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
> + dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
> + dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
> +}
> +
> +void lpddr4_100mhz_cfg_umctl2(void)
> +{
> + reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
> + reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
> + reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
> + reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
> + reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
> + reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
> + reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
> + reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
> + reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
> + reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
> + reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
> + reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
> + reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
> + reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
> + reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
> + reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
> + reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
> + reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
> + reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
> + reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
> + reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
> +}
> +
> +void lpddr4_25mhz_cfg_umctl2(void)
> +{
> + reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
> + reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
> + reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
> + reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
> + reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
> + reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
> + reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
> + reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
> + reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
> + reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
> + reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
> + reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
> + reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
> + reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
> + reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
> + reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
> + reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
> + reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
> + reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
> + reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
> + reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
> +}
> +
> +static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
> +
> +void ddr_init(void)
> +{
> + /* change the clock source of dram_apb_clk_root */
> + writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
> + writel((0x4 << 24) | (0x3 << 16), &ccm_reg->ip_root[1].target_root_set);
> +
> + /* disable the clock gating */
> + reg32_write(0x303A00EC, 0x0000ffff);
> + reg32setbit(0x303A00F8, 5);
> + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
> +
> + dram_pll_init();
> +
> + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
> +
> + /* Configure uMCTL2's registers */
> + lpddr4_800mhz_cfg_umctl2();
> +
> + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
> + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
> +
> + reg32_write(DDRC_DBG1(0), 0x00000000);
> + tmp = reg32_read(DDRC_PWRCTL(0));
> + reg32_write(DDRC_PWRCTL(0), 0x000000a8);
> + /* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */
> + reg32_write(DDRC_SWCTL(0), 0x00000000);
> + reg32_write(DDRC_DDR_SS_GPR0, 0x01);
> + reg32_write(DDRC_DFIMISC(0), 0x00000010);
> +
> + /* Configure LPDDR4 PHY's registers */
> + lpddr4_800M_cfg_phy();
> +
> + reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
> + reg32_write(DDRC_SWCTL(0), 0x0000);
> + /*
> + * ------------------- 9 -------------------
> + * Set DFIMISC.dfi_init_start to 1
> + * -----------------------------------------
> + */
> + reg32_write(DDRC_DFIMISC(0), 0x00000030);
> + reg32_write(DDRC_SWCTL(0), 0x0001);
> +
> + /* wait DFISTAT.dfi_init_complete to 1 */
> + tmp_t = 0;
> + while (tmp_t == 0) {
> + tmp = reg32_read(DDRC_DFISTAT(0));
> + tmp_t = tmp & 0x01;
> + tmp = reg32_read(DDRC_MRSTAT(0));
> + }
> +
> + reg32_write(DDRC_SWCTL(0), 0x0000);
> +
> + /* clear DFIMISC.dfi_init_complete_en */
> + reg32_write(DDRC_DFIMISC(0), 0x00000010);
> + reg32_write(DDRC_DFIMISC(0), 0x00000011);
> + reg32_write(DDRC_PWRCTL(0), 0x00000088);
> +
> + tmp = reg32_read(DDRC_CRCPARSTAT(0));
> + /*
> + * set SWCTL.sw_done to enable quasi-dynamic register
> + * programming outside reset.
> + */
> + reg32_write(DDRC_SWCTL(0), 0x00000001);
> +
> + /* wait SWSTAT.sw_done_ack to 1 */
> + while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
> + ;
> +
> + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
> + while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
> + ;
> +
> + reg32_write(DDRC_PWRCTL(0), 0x00000088);
> + /* reg32_write(DDRC_PWRCTL(0), 0x018a); */
> + tmp = reg32_read(DDRC_CRCPARSTAT(0));
> +
> + /* enable port 0 */
> + reg32_write(DDRC_PCTRL_0(0), 0x00000001);
> + tmp = reg32_read(DDRC_CRCPARSTAT(0));
> + reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
> +
> + reg32_write(DDRC_SWCTL(0), 0x0);
> + lpddr4_100mhz_cfg_umctl2();
> + lpddr4_25mhz_cfg_umctl2();
> + reg32_write(DDRC_SWCTL(0), 0x1);
> +
> + /* wait SWSTAT.sw_done_ack to 1 */
> + while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
> + ;
> +
> + reg32_write(DDRC_SWCTL(0), 0x0);
> +}
> diff --git a/board/freescale/mx8mq_evk/ddr/ddrphy_train.c b/board/freescale/mx8mq_evk/ddr/ddrphy_train.c
> new file mode 100644
> index 0000000000..1bf88a8837
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/ddr/ddrphy_train.c
> @@ -0,0 +1,1147 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include "ddr.h"
> +
> +static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
> +
> +void ddr_pll_bypass_100mts(void)
> +{
> + /* change the clock source of dram_alt_clk_root to source 2 --100MHZ */
> + writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[0].target_root_clr);
> + writel((0x2 << 24), &ccm_reg->ip_root[0].target_root_set);
> +
> + /* change the clock source of dram_apb_clk_root to source 2 --40MHZ */
> + writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
> + writel((0x2 << 24) | (0x1 << 16), &ccm_reg->ip_root[1].target_root_set);
> +
> + /* disable the clock gating */
> + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
> + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
> +
> + /* configure pll bypass mode */
> + reg32_write(0x30389804, 1 << 24);
> +
> + printf("PLL bypass to 100MTS setting done\n");
> +}
> +
> +void ddr_pll_bypass_400mts(void)
> +{
> + /* change the clock source of dram_alt_clk_root to source 2 --400MHZ */
> + writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[0].target_root_clr);
> + writel((0x5 << 24), &ccm_reg->ip_root[0].target_root_set);
> +
> + /* change the clock source of dram_apb_clk_root to source 2 --40MHZ/2 */
> + writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
> + writel((0x2 << 24) | (0x1 << 16), &ccm_reg->ip_root[1].target_root_set);
> +
> + /* disable the clock gating */
> + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
> + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
> +
> + /* configure pll bypass mode */
> + reg32_write(0x30389804, 1 << 24);
> +
> + printf("PLL bypass to 400MTS setting done\n");
> +}
> +
> +void dwc_ddrphy_phyinit_usercustom_e_setdficlk(int pstate)
> +{
> + if (pstate == 2) {
> + ddr_pll_bypass_100mts();
> + } else if (pstate == 1) {
> + ddr_pll_bypass_400mts();
> + } else {
> + writel((0x7 << 24) | (0x7 << 16), &ccm_reg->ip_root[1].target_root_clr);
> + writel((0x4 << 24) | (0x3 << 16), &ccm_reg->ip_root[1].target_root_set);
> + reg32_write(0x30389808, 1 << 24);
> + }
> +}
> +
> +void lpddr4_800M_cfg_phy(void)
> +{
> + unsigned int tmp, tmp_t;
> +
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xab);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xab);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xab);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xe38);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x21);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0x64);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x19c);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x19c);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x19c);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x660);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5555);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x65);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0xd);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x1a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0xfb);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x7);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + /* load the 1D training image */
> + ddr_load_train_code(FW_1D_IMAGE);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> +
> + /* set the PHY input clock to the desired frequency for pstate 2 */
> + dwc_ddrphy_phyinit_usercustom_e_setdficlk(2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x102);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x64);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x3100);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x3100);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
> + wait_ddrphy_training_complete();
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> +
> + /* set the PHY input clock to the desired frequency for pstate 1 */
> + dwc_ddrphy_phyinit_usercustom_e_setdficlk(1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x101);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x190);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x3100);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x3100);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
> + wait_ddrphy_training_complete();
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> +
> + /* set the PHY input clock to the desired frequency for pstate 0 */
> + dwc_ddrphy_phyinit_usercustom_e_setdficlk(0);
> +
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x84d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x84d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
> + wait_ddrphy_training_complete();
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + /* load the 2D training image */
> + ddr_load_train_code(FW_2D_IMAGE);
> +
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> +
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, 0x2828);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, 0x14);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x61);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x100);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x100);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x1f7f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, 0x31);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, 0x4d46);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, 0x4d08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, 0x312d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, 0x084d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, 0x312d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, 0x4600);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, 0x084d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + /* Execute the Training Firmware */
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
> + /* wait for 2D training complete */
> + wait_ddrphy_training_complete();
> +
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> +
> + /* (I) Load PHY Init Engine Image */
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4016);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4004);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x790);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x11a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x7aa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x2a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7b2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7c8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x2a8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x129);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x370);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x129);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x3c8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x1a9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0xc);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x199);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0x14);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x790);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x11a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x18);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0xc);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x199);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x8568);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x108);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0x18);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x790);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x1d8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x8558);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x70);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x788);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x1ff8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x85a8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x1e8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x50);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x798);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x60);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x7a0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x8310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0xa310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x6e);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x68);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x8310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0xa310);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x1ff8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x85a8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x1e8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x68);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0x798);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x78);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x7a0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x790);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x8b10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0xab10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x58);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x68);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x8b10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0xab10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x1d8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x80);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0x790);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x18);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x7aa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x6a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0xa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x1e9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x8080);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x108);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0xc);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x68);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x1a9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x8080);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x108);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x7aa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x6a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8568);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0xb7);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x790);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x16a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x1d);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x68);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x8558);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0xc);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x68);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x8558);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x168);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x3c8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x1a9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x370);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x129);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x20);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x2aa);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x9);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x10e);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0xe8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x8140);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10c);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x10);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0x8138);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x10c);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x7c8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x101);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x448);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x7c0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0xe8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0x47);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x630);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0x618);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0xe0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x7c8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0x8140);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x10c);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x4);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x7c8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x101);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2);
> + dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
> + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x000d0000, 0x0);
> + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010);
> + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x6a);
> + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d);
> + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x1);
> + /*
> + * CalBusy.0 =1, indicates the calibrator is actively calibrating.
> + * Wait Calibrating done.
> + */
> + tmp_t = 1;
> + while (tmp_t) {
> + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097);
> + tmp_t = tmp & 0x01;
> + }
> + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
> + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
> +}
> diff --git a/board/freescale/mx8mq_evk/ddr/helper.c b/board/freescale/mx8mq_evk/ddr/helper.c
> new file mode 100644
> index 0000000000..b58e47be89
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/ddr/helper.c
> @@ -0,0 +1,101 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/sections.h>
> +
> +#include "ddr.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define IMEM_LEN 32768
> +#define DMEM_LEN 16384
> +#define IMEM_2D_OFFSET 49152
> +
> +#define IMEM_OFFSET_ADDR 0x00050000
> +#define DMEM_OFFSET_ADDR 0x00054000
> +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
> +
> +/* We need PHY iMEM PHY is 32KB padded */
> +void ddr_load_train_code(enum fw_type type)
> +{
> + u32 tmp32, i;
> + u32 error = 0;
> + unsigned long pr_to32, pr_from32;
> + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
> + unsigned long imem_start = (unsigned long)&_end + fw_offset;
> + unsigned long dmem_start = imem_start + IMEM_LEN;
> +
> + pr_from32 = imem_start;
> + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
> + for (i = 0x0; i < IMEM_LEN; ) {
> + tmp32 = readl(pr_from32);
> + writew(tmp32 & 0x0000ffff, pr_to32);
> + pr_to32 += 4;
> + writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
> + pr_to32 += 4;
> + pr_from32 += 4;
> + i += 4;
> + }
> +
> + pr_from32 = dmem_start;
> + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
> + for (i = 0x0; i < DMEM_LEN;) {
> + tmp32 = readl(pr_from32);
> + writew(tmp32 & 0x0000ffff, pr_to32);
> + pr_to32 += 4;
> + writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
> + pr_to32 += 4;
> + pr_from32 += 4;
> + i += 4;
> + }
> +
> + printf("check ddr4_pmu_train_imem code\n");
> + pr_from32 = imem_start;
> + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
> + for (i = 0x0; i < IMEM_LEN;) {
> + tmp32 = (readw(pr_to32) & 0x0000ffff);
> + pr_to32 += 4;
> + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
> +
> + if (tmp32 != readl(pr_from32)) {
> + printf("%lx %lx\n", pr_from32, pr_to32);
> + error++;
> + }
> + pr_from32 += 4;
> + pr_to32 += 4;
> + i += 4;
> + }
> + if (error)
> + printf("check ddr4_pmu_train_imem code fail=%d\n", error);
> + else
> + printf("check ddr4_pmu_train_imem code pass\n");
> +
> + printf("check ddr4_pmu_train_dmem code\n");
> + pr_from32 = dmem_start;
> + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
> + for (i = 0x0; i < DMEM_LEN;) {
> + tmp32 = (readw(pr_to32) & 0x0000ffff);
> + pr_to32 += 4;
> + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
> + if (tmp32 != readl(pr_from32)) {
> + printf("%lx %lx\n", pr_from32, pr_to32);
> + error++;
> + }
> + pr_from32 += 4;
> + pr_to32 += 4;
> + i += 4;
> + }
> +
> + if (error)
> + printf("check ddr4_pmu_train_dmem code fail=%d", error);
> + else
> + printf("check ddr4_pmu_train_dmem code pass\n");
> +}
> diff --git a/board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c b/board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c
> new file mode 100644
> index 0000000000..a4eabf0b90
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/ddr/wait_ddrphy_training_complete.c
> @@ -0,0 +1,97 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +static inline void poll_pmu_message_ready(void)
> +{
> + unsigned int reg;
> +
> + do {
> + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
> + } while (reg & 0x1);
> +}
> +
> +static inline void ack_pmu_message_receive(void)
> +{
> + unsigned int reg;
> +
> + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
> +
> + do {
> + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
> + } while (!(reg & 0x1));
> +
> + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
> +}
> +
> +static inline unsigned int get_mail(void)
> +{
> + unsigned int reg;
> +
> + poll_pmu_message_ready();
> +
> + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
> +
> + ack_pmu_message_receive();
> +
> + return reg;
> +}
> +
> +static inline unsigned int get_stream_message(void)
> +{
> + unsigned int reg, reg2;
> +
> + poll_pmu_message_ready();
> +
> + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
> +
> + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
> +
> + reg2 = (reg2 << 16) | reg;
> +
> + ack_pmu_message_receive();
> +
> + return reg2;
> +}
> +
> +static inline void decode_major_message(unsigned int mail)
> +{
> + ddr_printf("[PMU Major message = 0x%08x]\n", mail);
> +}
> +
> +static inline void decode_streaming_message(void)
> +{
> + unsigned int string_index, arg __maybe_unused;
> + int i = 0;
> +
> + string_index = get_stream_message();
> + ddr_printf(" PMU String index = 0x%08x\n", string_index);
> + while (i < (string_index & 0xffff)) {
> + arg = get_stream_message();
> + ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
> + i++;
> + }
> +
> + ddr_printf("\n");
> +}
> +
> +void wait_ddrphy_training_complete(void)
> +{
> + unsigned int mail;
> +
> + while (1) {
> + mail = get_mail();
> + decode_major_message(mail);
> + if (mail == 0x08) {
> + decode_streaming_message();
> + } else if (mail == 0x07) {
> + printf("Training PASS\n");
> + break;
> + } else if (mail == 0xff) {
> + printf("Training FAILED\n");
> + break;
> + }
> + }
> +}
> --
> 2.14.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M
[not found] ` <CANr=Z=Z6ekzYT3+YG7nXWKedQc_3tS42_BAbkqnP8A8Qpij5Pg@mail.gmail.com>
@ 2017-12-05 20:36 ` Joe Hershberger
0 siblings, 0 replies; 65+ messages in thread
From: Joe Hershberger @ 2017-12-05 20:36 UTC (permalink / raw)
To: u-boot
On Sun, Dec 3, 2017 at 10:31 PM, Peng Fan <peng.fan@nxp.com> wrote:
> The MIB RAM and FIFO receive start register does not exist on
> i.MX8M. Accessing these register will cause system hang.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support Peng Fan
@ 2017-12-05 20:37 ` Joe Hershberger
2017-12-07 8:42 ` Stefano Babic
2017-12-16 17:43 ` Fabio Estevam
2 siblings, 0 replies; 65+ messages in thread
From: Joe Hershberger @ 2017-12-05 20:37 UTC (permalink / raw)
To: u-boot
On Sun, Dec 3, 2017 at 10:31 PM, Peng Fan <peng.fan@nxp.com> wrote:
> When building for 64bits system, we get some warnings about type
> cast between pointer and integer. This patch eliminates the warnings
> by using ulong/long type which is 32bits on 32bits system or 64bits on
> 64bits system.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 23/23] Add DDR settings
2017-12-04 17:48 ` Dr. Philipp Tomsich
@ 2017-12-07 7:31 ` Peng Fan
0 siblings, 0 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-07 7:31 UTC (permalink / raw)
To: u-boot
Hi Philipp,
>> +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
>> +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
>> +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
>> +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
>> +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
>> +
>> +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
>> +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
>
>This should use structure for I/O access.
>Please refer to https://www.denx.de/wiki/U-Boot/CodingStyle for details.
I understand. It is a bit hard for me to convert them to structure based.
I'll ask to see if our SoC team could generate that piece structure.
Anyway if this last patch could not be accepted, I hope the rest patches
could be in first.
Regards,
Peng.
>
>Regards,
>Philipp.
>
--
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 12/23] imx: mx8m: add soc related settings and files
2017-12-04 4:31 ` [U-Boot] [PATCH V2 12/23] imx: mx8m: add soc related settings and files Peng Fan
@ 2017-12-07 8:39 ` Stefano Babic
2017-12-07 9:06 ` Peng Fan
0 siblings, 1 reply; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:39 UTC (permalink / raw)
To: u-boot
Hi Peng,
On 04/12/2017 05:31, Peng Fan wrote:
> Add SoC level initialization code
> - arch_cpu_init
> - mmu table
> - detect cpu revision
> - reset cpu and wdog settings
> - M4 boot
> - timer init
> - wdog settings
> - lowlevel init to save/restore registers
> - a few dummy header file to avoid build failure
> - ft_system_setup and ft_add_optee_node
> - mmc env related
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/include/asm/arch-mx8m/crm_regs.h | 10 +
> arch/arm/include/asm/arch-mx8m/gpio.h | 12 +
> arch/arm/include/asm/arch-mx8m/sys_proto.h | 18 +
> arch/arm/mach-imx/Makefile | 1 +
> arch/arm/mach-imx/mx8m/Makefile | 3 +-
> arch/arm/mach-imx/mx8m/lowlevel_init.S | 63 ++++
> arch/arm/mach-imx/mx8m/soc.c | 539 +++++++++++++++++++++++++++++
> 7 files changed, 645 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/include/asm/arch-mx8m/crm_regs.h
> create mode 100644 arch/arm/include/asm/arch-mx8m/gpio.h
> create mode 100644 arch/arm/include/asm/arch-mx8m/sys_proto.h
> create mode 100644 arch/arm/mach-imx/mx8m/lowlevel_init.S
> create mode 100644 arch/arm/mach-imx/mx8m/soc.c
>
> diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-mx8m/crm_regs.h
> new file mode 100644
> index 0000000000..6582318983
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx8m/crm_regs.h
> @@ -0,0 +1,10 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
> +#define _ASM_ARCH_MX8M_CRM_REGS_H
> +/* Dummy header, some imx-common code needs this file */
> +#endif
> diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-mx8m/gpio.h
> new file mode 100644
> index 0000000000..b666d37700
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx8m/gpio.h
> @@ -0,0 +1,12 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_MX8M_GPIO_H
> +#define __ASM_ARCH_MX8M_GPIO_H
> +
> +#include <asm/mach-imx/gpio.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-mx8m/sys_proto.h
> new file mode 100644
> index 0000000000..8bf9ac6697
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx8m/sys_proto.h
> @@ -0,0 +1,18 @@
> +/*
> + * Copyright (C) 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ARCH_MX8M_SYS_PROTO_H
> +#define __ARCH_MX8M_SYS_PROTO_H
> +
> +#include <asm/mach-imx/sys_proto.h>
> +
> +void set_wdog_reset(struct wdog_regs *wdog);
> +void enable_tzc380(void);
> +void restore_boot_params(void);
> +extern unsigned long rom_pointer[];
> +enum boot_device get_boot_device(void);
> +bool is_usb_boot(void);
> +#endif
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index c807174363..27c154b8b3 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -127,4 +127,5 @@ obj-$(CONFIG_MX5) += mx5/
> obj-$(CONFIG_MX6) += mx6/
> obj-$(CONFIG_MX7) += mx7/
> obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
> +obj-$(CONFIG_MX8M) += mx8m/
>
> diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile
> index 05f38842f0..b1c5d74aab 100644
> --- a/arch/arm/mach-imx/mx8m/Makefile
> +++ b/arch/arm/mach-imx/mx8m/Makefile
> @@ -4,4 +4,5 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y += clock.o clock_slice.o
> +obj-y += lowlevel_init.o
> +obj-y += clock.o clock_slice.o soc.o
> diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/mx8m/lowlevel_init.S
> new file mode 100644
> index 0000000000..d388f3ba95
> --- /dev/null
> +++ b/arch/arm/mach-imx/mx8m/lowlevel_init.S
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <config.h>
> +
> +.align 8
> +.global rom_pointer
> +rom_pointer:
> + .space 256
> +
> +/*
> + * Routine: save_boot_params (called after reset from start.S)
> + */
> +
> +.global save_boot_params
> +save_boot_params:
save_boot_params is a weak function, but there is a comment for it about
that stack is not available at this point, any you are using the stack.
And what about this with exception_entry / exception_exit ? Your looks a
rewrite of functions in arch/arm/cpu/armv8/exceptions.S
> + /* The firmware provided ATAG/FDT address can be found in r2/x0 */
> + adr x0, rom_pointer
> + stp x1, x2, [x0], #16
> + stp x3, x4, [x0], #16
> + stp x5, x6, [x0], #16
> + stp x7, x8, [x0], #16
> + stp x9, x10, [x0], #16
> + stp x11, x12, [x0], #16
> + stp x13, x14, [x0], #16
> + stp x15, x16, [x0], #16
> + stp x17, x18, [x0], #16
> + stp x19, x20, [x0], #16
> + stp x21, x22, [x0], #16
> + stp x23, x24, [x0], #16
> + stp x25, x26, [x0], #16
> + stp x27, x28, [x0], #16
> + stp x29, x30, [x0], #16
> + mov x30, sp
> + str x30, [x0], #8
> +
> + /* Returns */
> + b save_boot_params_ret
> +
> +.global restore_boot_params
> +restore_boot_params:
> + adr x0, rom_pointer
> + ldp x1, x2, [x0], #16
> + ldp x3, x4, [x0], #16
> + ldp x5, x6, [x0], #16
> + ldp x7, x8, [x0], #16
> + ldp x9, x10, [x0], #16
> + ldp x11, x12, [x0], #16
> + ldp x13, x14, [x0], #16
> + ldp x15, x16, [x0], #16
> + ldp x17, x18, [x0], #16
> + ldp x19, x20, [x0], #16
> + ldp x21, x22, [x0], #16
> + ldp x23, x24, [x0], #16
> + ldp x25, x26, [x0], #16
> + ldp x27, x28, [x0], #16
> + ldp x29, x30, [x0], #16
> + ldr x0, [x0]
> + mov sp, x0
> + ret
> diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/mx8m/soc.c
> new file mode 100644
> index 0000000000..740e84caa4
> --- /dev/null
> +++ b/arch/arm/mach-imx/mx8m/soc.c
> @@ -0,0 +1,539 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * Peng Fan <peng.fan@nxp.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/hab.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <asm/mach-imx/syscounter.h>
> +#include <asm/armv8/mmu.h>
> +#include <errno.h>
> +#include <fdt_support.h>
> +#include <fsl_wdog.h>
> +#include <imx_sip.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_SECURE_BOOT)
> +struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
> + .bank = 1,
> + .word = 3,
> +};
> +#endif
> +
> +/*
> + * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
> + * defines a 2-bit SPEED_GRADING
> + */
> +#define OCOTP_TESTER3_SPEED_SHIFT 8
> +#define OCOTP_TESTER3_SPEED_800MHZ 0
> +#define OCOTP_TESTER3_SPEED_1GHZ 1
> +#define OCOTP_TESTER3_SPEED_1300MHZ 2
> +#define OCOTP_TESTER3_SPEED_1500MHZ 3
> +
> +u32 get_cpu_speed_grade_hz(void)
> +{
> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> + struct fuse_bank *bank = &ocotp->bank[1];
> + struct fuse_bank1_regs *fuse =
> + (struct fuse_bank1_regs *)bank->fuse_regs;
> + u32 val;
> +
> + val = readl(&fuse->tester3);
> + val >>= OCOTP_TESTER3_SPEED_SHIFT;
> + val &= 0x3;
> +
> + switch (val) {
> + case OCOTP_TESTER3_SPEED_800MHZ:
> + return 800000000;
> + case OCOTP_TESTER3_SPEED_1GHZ:
> + return 1000000000;
> + case OCOTP_TESTER3_SPEED_1300MHZ:
> + return 1300000000;
> + case OCOTP_TESTER3_SPEED_1500MHZ:
> + return 1500000000;
> + }
> + return 0;
> +}
> +
> +/*
> + * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
> + * defines a 2-bit SPEED_GRADING
> + */
> +#define OCOTP_TESTER3_TEMP_SHIFT 6
> +
> +/* CPU Temperature Grades */
> +#define TEMP_COMMERCIAL 0
> +#define TEMP_EXTCOMMERCIAL 1
> +#define TEMP_INDUSTRIAL 2
> +#define TEMP_AUTOMOTIVE 3
> +
> +u32 get_cpu_temp_grade(int *minc, int *maxc)
> +{
> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> + struct fuse_bank *bank = &ocotp->bank[1];
> + struct fuse_bank1_regs *fuse =
> + (struct fuse_bank1_regs *)bank->fuse_regs;
> + u32 val;
> +
> + val = readl(&fuse->tester3);
> + val >>= OCOTP_TESTER3_TEMP_SHIFT;
> + val &= 0x3;
> +
> + if (minc && maxc) {
> + if (val == TEMP_AUTOMOTIVE) {
> + *minc = -40;
> + *maxc = 125;
> + } else if (val == TEMP_INDUSTRIAL) {
> + *minc = -40;
> + *maxc = 105;
> + } else if (val == TEMP_EXTCOMMERCIAL) {
> + *minc = -20;
> + *maxc = 105;
> + } else {
> + *minc = 0;
> + *maxc = 95;
> + }
> + }
> + return val;
> +}
Even if they appear cross-architecture: get_cpu_speed_grade_hz() and
get_cpu_temp_grade() are very similar to the function in mx6/soc.c and
(*sigh*) in mx7/soc.c. This becomes the *third* duplication of the same
code. Can we factorize this and put the function in a file under
mach-imx, shared between mx6/mx7/mx8m ?
The expectation is mac-imx/mxX contains just specific code for that
architecture, while common code can flow into mach-imx.
> +
> +int timer_init(void)
> +{
> +#ifdef CONFIG_SPL_BUILD
> + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
> + unsigned long freq = readl(&sctr->cntfid0);
> +
> + /* Update with accurate clock frequency */
> + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
> +
> + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
> + SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
> +#endif
> +
> + gd->arch.tbl = 0;
> + gd->arch.tbu = 0;
> +
> + return 0;
> +}
> > +void enable_tzc380(void)
> +{
> + struct iomuxc_gpr_base_regs *gpr =
> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> + /* Enable TZASC and lock setting */
> + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
> + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
> +}
> +
> +void set_wdog_reset(struct wdog_regs *wdog)
> +{
> + /*
> + * Output WDOG_B signal to reset external pmic or POR_B decided by
> + * the board desgin.
s/desgin/design/
> Without external reset, the peripherals/DDR/
> + * PMIC are not reset, that may cause system working abnormal.
> + * WDZST bit is write-once only bit. Align this bit in kernel,
> + * otherwise kernel code will have no chance to set this bit.
> + */
> + setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
> +}
> +
> +static struct mm_region imx8m_mem_map[] = {
> + {
> + .virt = 0x0UL,
> + .phys = 0x0UL,
> + .size = 0x100000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_OUTER_SHARE
> + }, {
> + .virt = 0x100000UL,
> + .phys = 0x100000UL,
> + .size = 0x8000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + .virt = 0x7C0000UL,
> + .phys = 0x7C0000UL,
> + .size = 0x80000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + .virt = 0x900000UL,
> + .phys = 0x900000UL,
> + .size = 0x200000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_OUTER_SHARE
> + }, {
> + .virt = 0xB00000UL,
> + .phys = 0xB00000UL,
> + .size = 0x3f500000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0xC0000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_OUTER_SHARE
> + }, {
> + .virt = 0x100000000UL,
> + .phys = 0x100000000UL,
> + .size = 0x040000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_OUTER_SHARE
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
If you can, taking into account that currently documentation is scarce
or missing, can you add comments to each entry to explain each region ?
Thanks !
> +struct mm_region *mem_map = imx8m_mem_map;
> +
> +u32 get_cpu_rev(void)
> +{
> + struct anamix_pll *ana_pll = (struct anamix_pll *)ANA_PLL_BASE_ADDR;
This require a small explanation. My point: I would like that registers
with the same meaning could have the same name, even if defined in
different files according to the i.MX variants.
This looks a base address and it is ANATOP_BASE_ADDR for other
architectures. Any reason for changing it ? Can we at least try to use
the same nomenclature across i.MX processors ?
> + u32 reg = readl(&ana_pll->digprog);
> + u32 type = (reg >> 16) & 0xff;
> + u32 rom_version;
> +
> + reg &= 0xff;
> +
> + if (reg == 0x10) {
> + /*
> + * For B0 chip, the DIGPROG is not updated, still TO1.0.
> + * we have to check ROM version further
> + */
> + rom_version = readl((void __iomem *)0x800);
Has a name this address ? Something like SCU_BASE_ADDR (just copied the
name, no idea if it is correct ) ?
I prefer to remove magic addresses like 0x800, 0x83c and use define for
them.
> + if (rom_version != 0x10) {
> + rom_version = readl((void __iomem *)0x83c);
> + if (rom_version >= 0x20)
> + reg = 0x20;
> + }
> + }
> +
> + return (type << 12) | reg;
> +}
> +
> +static void imx_set_wdog_powerdown(bool enable)
> +{
> + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
> + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
> + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
> +
> + /* Write to the PDE (Power Down Enable) bit */
> + writew(enable, &wdog1->wmcr);
> + writew(enable, &wdog2->wmcr);
> + writew(enable, &wdog3->wmcr);
> +}
> +
> +int arch_cpu_init(void)
> +{
> + /*
> + * Init timer at very early state, because sscg pll setting
> + * will use it
> + */
> + timer_init();
> +
> + if (IS_ENABLED(CONFIG_SPL_BUILD)) {
> + clock_init();
> + imx_set_wdog_powerdown(false);
> + }
> +
> + return 0;
> +}
> +
> +#if defined(CONFIG_FEC_MXC)
> +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
> +{
> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> + struct fuse_bank *bank = &ocotp->bank[9];
> + struct fuse_bank9_regs *fuse =
> + (struct fuse_bank9_regs *)bank->fuse_regs;
> + u32 value = readl(&fuse->mac_addr1);
> +
> + mac[0] = (value >> 8);
> + mac[1] = value;
> +
> + value = readl(&fuse->mac_addr0);
> + mac[2] = value >> 24;
> + mac[3] = value >> 16;
> + mac[4] = value >> 8;
> + mac[5] = value;
> +}
This is the last copy of imx_get_mac_from_fuse() that we introduce in
U-Boot. At least the 3rd copy, and it is time to factorize them. All
functions are doing the same !
> +#endif
> +
> +#ifdef CONFIG_IMX_BOOTAUX
> +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
> +{
> + u32 stack, pc;
> +
> + if (!boot_private_data)
> + return -EINVAL;
> +
> + stack = *(u32 *)boot_private_data;
> + pc = *(u32 *)(boot_private_data + 4);
> +
> + /* Set the stack and pc to M4 bootROM */
> + writel(stack, M4_BOOTROM_BASE_ADDR);
> + writel(pc, M4_BOOTROM_BASE_ADDR + 4);
> +
> + /* Enable M4 */
> + call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
> +
> + return 0;
> +}
Quite the same, apart sip call, and this can be factorized, too.
> +
> +int arch_auxiliary_core_check_up(u32 core_id)
> +{
> + return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
> +}
> +#endif
> +
> +enum boot_device get_boot_device(void)
> +{
> + struct bootrom_sw_info **p =
> + is_soc_rev(CHIP_REV_1_0) ?
> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
> +
> + enum boot_device boot_dev = SD1_BOOT;
> + u8 boot_type = (*p)->boot_dev_type;
> + u8 boot_instance = (*p)->boot_dev_instance;
> +
> + switch (boot_type) {
> + case BOOT_TYPE_SD:
> + boot_dev = boot_instance + SD1_BOOT;
> + break;
> + case BOOT_TYPE_MMC:
> + boot_dev = boot_instance + MMC1_BOOT;
> + break;
> + case BOOT_TYPE_NAND:
> + boot_dev = NAND_BOOT;
> + break;
> + case BOOT_TYPE_QSPI:
> + boot_dev = QSPI_BOOT;
> + break;
> + case BOOT_TYPE_WEIM:
> + boot_dev = WEIM_NOR_BOOT;
> + break;
> + case BOOT_TYPE_SPINOR:
> + boot_dev = SPI_NOR_BOOT;
> + break;
> + case BOOT_TYPE_USB:
> + boot_dev = USB_BOOT;
> + break;
> + default:
> + break;
> + }
> +
I suggest to add BOOT_TYPE_USB for all i.MXes and factorized this
function, too. This is really identical to the one in
arch/arm/mach-imx/mx7/soc.c
> + return boot_dev;
> +}
> +
> +bool is_usb_boot(void)
> +{
> + return get_boot_device() == USB_BOOT;
> +}
> +
> +#ifdef CONFIG_ENV_IS_IN_MMC
> +__weak int board_mmc_get_env_dev(int devno)
> +{
> + return CONFIG_SYS_MMC_ENV_DEV;
> +}
> +
> +int mmc_get_env_dev(void)
> +{
> + struct bootrom_sw_info **p =
> + is_soc_rev(CHIP_REV_1_0) ?
> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
> + int devno = (*p)->boot_dev_instance;
> + u8 boot_type = (*p)->boot_dev_type;
> +
> + /* If not boot from sd/mmc, use default value */
> + if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
> + return CONFIG_SYS_MMC_ENV_DEV;
> +
> + return board_mmc_get_env_dev(devno);
> +}
Quite the same for mmc_get_env_dev()
I sumarize: as you explained, there are much more similarities with imx6
/ imx7 in MX8M. This means we can share the same code between arch, at
least between i.MX7 and i.MX8M (but, ideally, as much as we can).
> +#endif
> +
> +#ifdef CONFIG_OF_SYSTEM_SETUP
> +static int ft_add_optee_node(void *fdt, bd_t *bd)
> +{
> + const char *path, *subpath;
> + int offs;
> +
> + /*
> + * No TEE space allocated indicating no TEE running, so no
> + * need to add optee node in dts
> + */
> + if (!rom_pointer[1])
> + return 0;
> +
> + offs = fdt_increase_size(fdt, 512);
> + if (offs) {
> + printf("No Space for dtb\n");
> + return offs;
> + }
> +
> + path = "/firmware";
> + offs = fdt_path_offset(fdt, path);
> + if (offs < 0) {
> + path = "/";
> + offs = fdt_path_offset(fdt, path);
> +
> + if (offs < 0) {
> + printf("Could not find root node.\n");
> + return offs;
> + }
> +
> + subpath = "firmware";
> + offs = fdt_add_subnode(fdt, offs, subpath);
> + if (offs < 0) {
> + printf("Could not create %s node.\n", subpath);
> + return offs;
> + }
> + }
> +
> + subpath = "optee";
> + offs = fdt_add_subnode(fdt, offs, subpath);
> + if (offs < 0) {
> + printf("Could not create %s node.\n", subpath);
> + return offs;
> + }
> +
> + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
> + fdt_setprop_string(fdt, offs, "method", "smc");
> +
> + return 0;
> +}
This has nothing to do with the specific SOC and should be moved.
> +
> +int ft_system_setup(void *blob, bd_t *bd)
> +{
> + static const char * const status = "disabled";
> + static const char * const usb_dwc3_path = "/usb at 38100000/dwc3";
> + static const char * const speed = "high-speed";
> + int i = 0;
> + int rc;
> + int nodeoff;
> +
> + if (get_boot_device() == USB_BOOT) {
> + static const char * const nodes_path[] = {
> + "/dcss at 32e00000",
> + "/hdmi at 32c00000",
> + "/hdmi_cec at 32c33800",
> + "/hdmi_drm at 32c00000",
> + "/display-subsystem",
> + "/sound-hdmi"
> + };
> +
This should be moved, too, but why do we increase blob size if boot
device is USB ?
> + for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
> + nodeoff = fdt_path_offset(blob, nodes_path[i]);
> + if (nodeoff < 0)
> + continue; /* Not found, skip it */
> +
> + printf("Found %s node\n", nodes_path[i]);
> +
> +add_status:
> + rc = fdt_setprop(blob, nodeoff, "status", status,
> + strlen(status) + 1);
> + if (rc) {
> + if (rc == -FDT_ERR_NOSPACE) {
> + rc = fdt_increase_size(blob, 512);
> + if (!rc)
> + goto add_status;
> + }
> + printf("Unable to update property %s:%s, err=%s\n",
> + nodes_path[i], "status",
> + fdt_strerror(rc));
> + return rc;
> + }
> +
> + printf("Modify %s:%s disabled\n",
> + nodes_path[i], "status");
> + }
> +
> + nodeoff = fdt_path_offset(blob, usb_dwc3_path);
> + if (nodeoff >= 0) {
> + printf("Found %s node\n", usb_dwc3_path);
> +
> +usb_modify_speed:
> +
> + rc = fdt_setprop(blob, nodeoff, "maximum-speed",
> + speed, strlen(speed) + 1);
> + if (rc) {
> + if (rc == -FDT_ERR_NOSPACE) {
> + rc = fdt_increase_size(blob, 512);
> + if (!rc)
> + goto usb_modify_speed;
> + }
> + printf("Unable to set property %s:%s, err=%s\n",
> + usb_dwc3_path, "maximum-speed",
> + fdt_strerror(rc));
> + return rc;
> + }
> +
> + printf("Modify %s:%s = %s\n",
> + usb_dwc3_path, "maximum-speed", speed);
> + } else {
> + printf("Can't found %s node\n", usb_dwc3_path);
> + }
> + }
> +
> + /* Disable the CPU idle for A0 chip since the HW does not support it */
> + if (is_soc_rev(CHIP_REV_1_0)) {
> + static const char * const nodes_path[] = {
> + "/cpus/cpu at 0",
> + "/cpus/cpu at 1",
> + "/cpus/cpu at 2",
> + "/cpus/cpu at 3",
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
> + nodeoff = fdt_path_offset(blob, nodes_path[i]);
> + if (nodeoff < 0)
> + continue; /* Not found, skip it */
> +
> + printf("Found %s node\n", nodes_path[i]);
> +
> + rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
> + if (rc) {
> + printf("Unable to update property %s:%s, err=%s\n",
> + nodes_path[i], "status", fdt_strerror(rc));
> + return rc;
> + }
> +
> + printf("Remove %s:%s\n", nodes_path[i],
> + "cpu-idle-states");
> + }
> + }
> +
> + return ft_add_optee_node(blob, bd);
> +}
> +#endif
> +
> +void reset_cpu(ulong addr)
> +{
> + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
> +
> + /* Clear WDA to trigger WDOG_B immediately */
> + writew((WCR_WDE | WCR_SRS), &wdog->wcr);
> +
> + while (1) {
> + /*
> + * spin for .5 seconds before reset
> + */
> + }
> +}
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M Peng Fan
@ 2017-12-07 8:40 ` Stefano Babic
2017-12-16 17:36 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:40 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> Update get_reset_cause to reflect i.MX8M
> Compile out get_ahb_clk and set_chipselect_size for i.MX8M
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/mach-imx/cpu.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
> index 18205dc984..c811252733 100644
> --- a/arch/arm/mach-imx/cpu.c
> +++ b/arch/arm/mach-imx/cpu.c
> @@ -62,6 +62,11 @@ static char *get_reset_cause(void)
> return "WDOG4";
> case 0x00200:
> return "TEMPSENSE";
> +#elif defined(CONFIG_MX8M)
> + case 0x00100:
> + return "WDOG2";
> + case 0x00200:
> + return "TEMPSENSE";
> #else
> case 0x00100:
> return "TEMPSENSE";
> @@ -137,6 +142,8 @@ unsigned imx_ddr_size(void)
> const char *get_imx_type(u32 imxtype)
> {
> switch (imxtype) {
> + case MXC_CPU_MX8MQ:
> + return "8MQ"; /* Quad-core version of the mx8m */
> case MXC_CPU_MX7S:
> return "7S"; /* Single-core version of the mx7 */
> case MXC_CPU_MX7D:
> @@ -259,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
> }
> #endif
>
> -#ifndef CONFIG_MX7
> +#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
> u32 get_ahb_clk(void)
> {
> struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> @@ -293,6 +300,7 @@ void arch_preboot_os(void)
> #endif
> }
>
> +#ifndef CONFIG_MX8M
> void set_chipselect_size(int const cs_size)
> {
> unsigned int reg;
> @@ -323,3 +331,4 @@ void set_chipselect_size(int const cs_size)
>
> writel(reg, &iomuxc_regs->gpr[1]);
> }
> +#endif
>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support Peng Fan
@ 2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:40 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:41 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> i.MX8M OCOTP follow same flow as i.MX6Q, but it has 64 banks
> and each bank 4 words.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/misc/mxc_ocotp.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
> index 8986bb4ad0..0cf24a4c88 100644
> --- a/drivers/misc/mxc_ocotp.c
> +++ b/drivers/misc/mxc_ocotp.c
> @@ -35,6 +35,8 @@
> #define BM_OUT_STATUS_DED 0x00000400
> #define BM_OUT_STATUS_LOCKED 0x00000800
> #define BM_OUT_STATUS_PROGFAIL 0x00001000
> +#elif defined(CONFIG_MX8M)
> +#define BM_CTRL_ADDR 0x000000ff
> #else
> #define BM_CTRL_ADDR 0x0000007f
> #endif
> @@ -79,6 +81,9 @@
> #elif defined(CONFIG_MX7ULP)
> #define FUSE_BANK_SIZE 0x80
> #define FUSE_BANKS 31
> +#elif defined(CONFIG_MX8M)
> +#define FUSE_BANK_SIZE 0x40
> +#define FUSE_BANKS 64
> #else
> #error "Unsupported architecture\n"
> #endif
> @@ -294,6 +299,8 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
> u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
> #ifdef CONFIG_MX7
> u32 addr = bank;
> +#elif defined CONFIG_MX8M
> + u32 addr = bank << 2 | word;
> #else
> u32 addr;
> /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M Peng Fan
@ 2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:40 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:41 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> Support i.MX8M in fsl esdhc driver.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/mmc/fsl_esdhc.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 499d622c6d..3a56f7c2bc 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -228,7 +228,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
> {
> int timeout;
> struct fsl_esdhc *regs = priv->esdhc_regs;
> -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
> +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> + defined(CONFIG_MX8M)
> dma_addr_t addr;
> #endif
> uint wml_value;
> @@ -241,7 +242,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
>
> esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
> #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
> -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
> +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> + defined(CONFIG_MX8M)
> addr = virt_to_phys((void *)(data->dest));
> if (upper_32_bits(addr))
> printf("Error found for upper 32 bits\n");
> @@ -270,7 +272,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
> esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
> wml_value << 16);
> #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
> -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
> +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> + defined(CONFIG_MX8M)
> addr = virt_to_phys((void *)(data->src));
> if (upper_32_bits(addr))
> printf("Error found for upper 32 bits\n");
> @@ -335,7 +338,8 @@ static void check_and_invalidate_dcache_range
> unsigned end = 0;
> unsigned size = roundup(ARCH_DMA_MINALIGN,
> data->blocks*data->blocksize);
> -#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
> +#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
> + defined(CONFIG_MX8M)
> dma_addr_t addr;
>
> addr = virt_to_phys((void *)(data->dest));
>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M Peng Fan
@ 2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:41 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:41 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> Include i.MX8M in lcdif register layout map.
> Also included i.MX7ULP in this patch, since share same with i.MX8M.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/include/asm/mach-imx/regs-lcdif.h | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
> index 4de401bd22..57e6357608 100644
> --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
> +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
> @@ -20,7 +20,9 @@ struct mxs_lcdif_regs {
> mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
> mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
> #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
> - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
> + defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || \
> + defined(CONFIG_MX6SLL) || defined(CONFIG_MX7ULP) || \
> + defined(CONFIG_MX8M)
> mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
> #endif
> mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
> @@ -56,7 +58,9 @@ struct mxs_lcdif_regs {
> mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
> mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
> #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
> - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
> + defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || \
> + defined(CONFIG_MX6SLL) || defined(CONFIG_MX7ULP) || \
> + defined(CONFIG_MX8M)
> mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
> #endif
> mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
> @@ -65,7 +69,8 @@ struct mxs_lcdif_regs {
> mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
> mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
> #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
> - defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
> + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
> + defined(CONFIG_MX7ULP) || defined(CONFIG_MX8M)
> mxs_reg_32(hw_lcdif_thres)
> mxs_reg_32(hw_lcdif_as_ctrl)
> mxs_reg_32(hw_lcdif_as_buf)
>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M Peng Fan
[not found] ` <CANr=Z=Z6ekzYT3+YG7nXWKedQc_3tS42_BAbkqnP8A8Qpij5Pg@mail.gmail.com>
@ 2017-12-07 8:42 ` Stefano Babic
2017-12-16 17:41 ` Fabio Estevam
2 siblings, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:42 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> The MIB RAM and FIFO receive start register does not exist on
> i.MX8M. Accessing these register will cause system hang.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> ---
> drivers/net/fec_mxc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 433e19f0f8..4cbc8cbbfd 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -562,8 +562,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
> writel(0x00000000, &fec->eth->gaddr1);
> writel(0x00000000, &fec->eth->gaddr2);
>
> - /* Do not access reserved register for i.MX6UL */
> - if (!is_mx6ul() && !is_mx6ull()) {
> + /* Do not access reserved register */
> + if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
> /* clear MIB RAM */
> for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
> writel(0, i);
>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support Peng Fan
2017-12-05 20:37 ` Joe Hershberger
@ 2017-12-07 8:42 ` Stefano Babic
2017-12-16 17:43 ` Fabio Estevam
2 siblings, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:42 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> When building for 64bits system, we get some warnings about type
> cast between pointer and integer. This patch eliminates the warnings
> by using ulong/long type which is 32bits on 32bits system or 64bits on
> 64bits system.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> ---
> drivers/net/fec_mxc.c | 74 ++++++++++++++++++++++++++++++---------------------
> 1 file changed, 43 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 4cbc8cbbfd..ff7ad91116 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -284,7 +284,7 @@ static int fec_tx_task_disable(struct fec_priv *fec)
> static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
> {
> uint32_t size;
> - uint8_t *data;
> + ulong data;
> int i;
>
> /*
> @@ -293,9 +293,9 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
> */
> size = roundup(dsize, ARCH_DMA_MINALIGN);
> for (i = 0; i < count; i++) {
> - data = (uint8_t *)fec->rbd_base[i].data_pointer;
> - memset(data, 0, dsize);
> - flush_dcache_range((uint32_t)data, (uint32_t)data + size);
> + data = fec->rbd_base[i].data_pointer;
> + memset((void *)data, 0, dsize);
> + flush_dcache_range(data, data + size);
>
> fec->rbd_base[i].status = FEC_RBD_EMPTY;
> fec->rbd_base[i].data_length = 0;
> @@ -305,8 +305,8 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
> fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
> fec->rbd_index = 0;
>
> - flush_dcache_range((unsigned)fec->rbd_base,
> - (unsigned)fec->rbd_base + size);
> + flush_dcache_range((ulong)fec->rbd_base,
> + (ulong)fec->rbd_base + size);
> }
>
> /**
> @@ -323,7 +323,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
> */
> static void fec_tbd_init(struct fec_priv *fec)
> {
> - unsigned addr = (unsigned)fec->tbd_base;
> + ulong addr = (ulong)fec->tbd_base;
> unsigned size = roundup(2 * sizeof(struct fec_bd),
> ARCH_DMA_MINALIGN);
>
> @@ -423,7 +423,7 @@ static int fec_open(struct eth_device *edev)
> struct fec_priv *fec = (struct fec_priv *)edev->priv;
> #endif
> int speed;
> - uint32_t addr, size;
> + ulong addr, size;
> int i;
>
> debug("fec_open: fec_open(dev)\n");
> @@ -439,7 +439,7 @@ static int fec_open(struct eth_device *edev)
> /* Flush the descriptors into RAM */
> size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
> ARCH_DMA_MINALIGN);
> - addr = (uint32_t)fec->rbd_base;
> + addr = (ulong)fec->rbd_base;
> flush_dcache_range(addr, addr + size);
>
> #ifdef FEC_QUIRK_ENET_MAC
> @@ -533,8 +533,9 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
> #else
> struct fec_priv *fec = (struct fec_priv *)dev->priv;
> #endif
> - uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
> - int i;
> + u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
> + u8 *i;
> + ulong addr;
>
> /* Initialize MAC address */
> #ifdef CONFIG_DM_ETH
> @@ -574,8 +575,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
>
> /* size and address of each buffer */
> writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
> - writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
> - writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
> +
> + addr = (ulong)fec->tbd_base;
> + writel((uint32_t)addr, &fec->eth->etdsr);
> +
> + addr = (ulong)fec->rbd_base;
> + writel((uint32_t)addr, &fec->eth->erdsr);
>
> #ifndef CONFIG_PHYLIB
> if (fec->xcv_type != SEVENWIRE)
> @@ -640,8 +645,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> #endif
> {
> unsigned int status;
> - uint32_t size, end;
> - uint32_t addr;
> + u32 size;
> + ulong addr, end;
> int timeout = FEC_XFER_TIMEOUT;
> int ret = 0;
>
> @@ -672,13 +677,13 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> swap_packet((uint32_t *)packet, length);
> #endif
>
> - addr = (uint32_t)packet;
> + addr = (ulong)packet;
> end = roundup(addr + length, ARCH_DMA_MINALIGN);
> addr &= ~(ARCH_DMA_MINALIGN - 1);
> flush_dcache_range(addr, end);
>
> writew(length, &fec->tbd_base[fec->tbd_index].data_length);
> - writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
> + writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
>
> /*
> * update BD's status now
> @@ -698,7 +703,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> * can start DMA.
> */
> size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
> - addr = (uint32_t)fec->tbd_base;
> + addr = (ulong)fec->tbd_base;
> flush_dcache_range(addr, addr + size);
>
> /*
> @@ -799,7 +804,7 @@ static int fec_recv(struct eth_device *dev)
> unsigned long ievent;
> int frame_length, len = 0;
> uint16_t bd_status;
> - uint32_t addr, size, end;
> + ulong addr, size, end;
> int i;
> ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
>
> @@ -854,7 +859,7 @@ static int fec_recv(struct eth_device *dev)
> * the descriptor. The solution is to mark the whole cache line when all
> * descriptors in the cache line are processed.
> */
> - addr = (uint32_t)rbd;
> + addr = (ulong)rbd;
> addr &= ~(ARCH_DMA_MINALIGN - 1);
> size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
> invalidate_dcache_range(addr, addr + size);
> @@ -882,8 +887,8 @@ static int fec_recv(struct eth_device *dev)
> len = frame_length;
> } else {
> if (bd_status & FEC_RBD_ERR)
> - debug("error frame: 0x%08x 0x%08x\n",
> - addr, bd_status);
> + debug("error frame: 0x%08lx 0x%08x\n",
> + addr, bd_status);
> }
>
> /*
> @@ -895,7 +900,7 @@ static int fec_recv(struct eth_device *dev)
> size = RXDESC_PER_CACHELINE - 1;
> if ((fec->rbd_index & size) == size) {
> i = fec->rbd_index - size;
> - addr = (uint32_t)&fec->rbd_base[i];
> + addr = (ulong)&fec->rbd_base[i];
> for (; i <= fec->rbd_index ; i++) {
> fec_rbd_clean(i == (FEC_RBD_NUM - 1),
> &fec->rbd_base[i]);
> @@ -922,6 +927,7 @@ static int fec_alloc_descs(struct fec_priv *fec)
> unsigned int size;
> int i;
> uint8_t *data;
> + ulong addr;
>
> /* Allocate TX descriptors. */
> size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
> @@ -950,11 +956,12 @@ static int fec_alloc_descs(struct fec_priv *fec)
>
> memset(data, 0, size);
>
> - fec->rbd_base[i].data_pointer = (uint32_t)data;
> + addr = (ulong)data;
> + fec->rbd_base[i].data_pointer = (uint32_t)addr;
> fec->rbd_base[i].status = FEC_RBD_EMPTY;
> fec->rbd_base[i].data_length = 0;
> /* Flush the buffer to memory. */
> - flush_dcache_range((uint32_t)data, (uint32_t)data + size);
> + flush_dcache_range(addr, addr + size);
> }
>
> /* Mark the last RBD to close the ring. */
> @@ -966,8 +973,10 @@ static int fec_alloc_descs(struct fec_priv *fec)
> return 0;
>
> err_ring:
> - for (; i >= 0; i--)
> - free((void *)fec->rbd_base[i].data_pointer);
> + for (; i >= 0; i--) {
> + addr = fec->rbd_base[i].data_pointer;
> + free((void *)addr);
> + }
> free(fec->rbd_base);
> err_rx:
> free(fec->tbd_base);
> @@ -978,9 +987,12 @@ err_tx:
> static void fec_free_descs(struct fec_priv *fec)
> {
> int i;
> + ulong addr;
>
> - for (i = 0; i < FEC_RBD_NUM; i++)
> - free((void *)fec->rbd_base[i].data_pointer);
> + for (i = 0; i < FEC_RBD_NUM; i++) {
> + addr = fec->rbd_base[i].data_pointer;
> + free((void *)addr);
> + }
> free(fec->rbd_base);
> free(fec->tbd_base);
> }
> @@ -995,7 +1007,7 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
> struct fec_priv *priv = dev_get_priv(dev);
> struct ethernet_regs *eth = priv->eth;
> #else
> - struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
> + struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr;
> #endif
> struct mii_dev *bus;
> int ret;
> @@ -1065,7 +1077,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
> edev->halt = fec_halt;
> edev->write_hwaddr = fec_set_hwaddr;
>
> - fec->eth = (struct ethernet_regs *)base_addr;
> + fec->eth = (struct ethernet_regs *)(ulong)base_addr;
> fec->bd = bd;
>
> fec->xcv_type = CONFIG_FEC_XCV_TYPE;
>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL
2017-12-04 4:31 ` [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL Peng Fan
@ 2017-12-07 8:43 ` Stefano Babic
2017-12-16 17:43 ` Fabio Estevam
2017-12-17 10:33 ` Stefano Babic
2 siblings, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:43 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> Allow the dm driver be omitted by SPL.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> drivers/power/pmic/Makefile | 4 ++--
> drivers/power/regulator/Makefile | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index f7bdfa5609..4abdaf6668 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -5,10 +5,10 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC) += pmic-uclass.o
> obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
> obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
> -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
> obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
> obj-$(CONFIG_PMIC_ACT8846) += act8846.o
> diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
> index 6c149a9263..9809f7c845 100644
> --- a/drivers/power/regulator/Makefile
> +++ b/drivers/power/regulator/Makefile
> @@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
> obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
> obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
> obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
> -obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
> obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
> obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support Peng Fan
@ 2017-12-07 8:52 ` Stefano Babic
2017-12-07 9:13 ` Peng Fan
2017-12-16 17:51 ` Fabio Estevam
1 sibling, 1 reply; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 8:52 UTC (permalink / raw)
To: u-boot
Hi Peng,
On 04/12/2017 05:31, Peng Fan wrote:
> Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
> firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
> DRAM.
>
> The boot log:
> "
> U-Boot SPL 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31)
> PMIC: PFUZE100 ID=0x10
> check ddr4_pmu_train_imem code
> check ddr4_pmu_train_imem code pass
> check ddr4_pmu_train_dmem code
> check ddr4_pmu_train_dmem code pass
> PLL bypass to 100MTS setting done
> Training PASS
> PLL bypass to 400MTS setting done
> Training PASS
> Training PASS
> check ddr4_pmu_train_imem code
> check ddr4_pmu_train_imem code pass
> check ddr4_pmu_train_dmem code
> check ddr4_pmu_train_dmem code pass
> Training PASS
> Normal Boot
> Trying to boot from MMC2
>
> U-Boot 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31 +0800)
>
> CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz
> Reset cause: POR
> Model: Freescale i.MX8MQ EVK
> DRAM: 3 GiB
> MMC: FSL_SDHC: 0, FSL_SDHC: 1
> Using default environment
>
> In: serial
> Out: serial
> Err: serial
> Net: No ethernet found.
> Hit any key to stop autoboot: 0
> "
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/fsl-imx8mq-evk.dts | 424 ++++++++++++++++++++++++++++++++++
> arch/arm/mach-imx/mx8m/Kconfig | 12 +
> board/freescale/mx8mq_evk/Kconfig | 12 +
> board/freescale/mx8mq_evk/Makefile | 11 +
> board/freescale/mx8mq_evk/README | 38 +++
> board/freescale/mx8mq_evk/mx8mq_evk.c | 156 +++++++++++++
> board/freescale/mx8mq_evk/spl.c | 233 +++++++++++++++++++
> configs/mx8mq_evk_defconfig | 28 +++
> include/configs/mx8mq_evk.h | 265 +++++++++++++++++++++
> 10 files changed, 1181 insertions(+)
> create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
> create mode 100644 board/freescale/mx8mq_evk/Kconfig
> create mode 100644 board/freescale/mx8mq_evk/Makefile
> create mode 100644 board/freescale/mx8mq_evk/README
> create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
> create mode 100644 board/freescale/mx8mq_evk/spl.c
> create mode 100644 configs/mx8mq_evk_defconfig
> create mode 100644 include/configs/mx8mq_evk.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index cd540e99ea..d459755904 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -381,6 +381,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
>
> dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>
> +dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb
> +
> dtb-$(CONFIG_RCAR_GEN3) += \
> r8a7795-h3ulcb.dtb \
> r8a7795-salvator-x.dtb \
> diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
> new file mode 100644
> index 0000000000..f0aa3485e6
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8mq-evk.dts
> @@ -0,0 +1,424 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017 NXP
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +/* First 128KB is for PSCI ATF. */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +#include "fsl-imx8mq.dtsi"
> +
> +/ {
> + model = "Freescale i.MX8MQ EVK";
> + compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
> +
> + chosen {
> + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg_usdhc2_vmmc: usdhc2_vmmc {
> + compatible = "regulator-fixed";
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> + };
> +
> + pwmleds {
> + compatible = "pwm-leds";
> +
> + ledpwm2 {
> + label = "PWM2";
> + pwms = <&pwm2 0 50000>;
> + max-brightness = <255>;
> + };
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> +
> + imx8mq-evk {
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
> + >;
> + };
> +
> + pinctrl_qspi: qspigrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
> + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
> + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
> + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
> + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
> + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
> +
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
> + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
> + >;
> + };
> +
> + pinctrl_sai2: sai2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
> + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
> + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
> + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> + };
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy at 0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + at803x,led-act-blind-workaround;
> + at803x,eee-disabled;
> + };
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic: pfuze100 at 08 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-always-on;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-always-on;
> + };
> +
> + sw2_reg: sw2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + sw3a_reg: sw3ab {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-always-on;
> + };
> +
> + sw4_reg: sw4 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-always-on;
> + };
> +
> + vgen1_reg: vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-always-on;
> + };
> +
> + vgen3_reg: vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> + };
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "disabled";
> +};
> +
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "okay";
> +};
> +
> +&lcdif {
> + status = "okay";
> + disp-dev = "mipi_dsi_northwest";
> + display = <&display0>;
> +
> + display0: display at 0 {
> + bits-per-pixel = <24>;
> + bus-width = <24>;
> +
> + display-timings {
> + native-mode = <&timing0>;
> + timing0: timing0 {
> + clock-frequency = <9200000>;
> + hactive = <480>;
> + vactive = <272>;
> + hfront-porch = <8>;
> + hback-porch = <4>;
> + hsync-len = <41>;
> + vback-porch = <2>;
> + vfront-porch = <4>;
> + vsync-len = <10>;
> +
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <0>;
> + };
> + };
> + };
> +};
> +
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi>;
> + status = "okay";
> +
> + flash0: n25q256a at 0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "micron,n25q256a";
> + spi-max-frequency = <29000000>;
> + spi-nor,ddr-quad-read-dummy = <6>;
> + };
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> + bus-width = <4>;
> + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
> index 3a84c2f2b0..e3b57b7915 100644
> --- a/arch/arm/mach-imx/mx8m/Kconfig
> +++ b/arch/arm/mach-imx/mx8m/Kconfig
> @@ -7,4 +7,16 @@ config MX8M
> config SYS_SOC
> default "mx8m"
>
> +choice
> + prompt "NXP i.MX8M board select"
> + optional
> +
> +config TARGET_MX8MQ_EVK
> + bool "mx8mq_evk"
> + select MX8M
> +
> +endchoice
> +
> +source "board/freescale/mx8mq_evk/Kconfig"
> +
> endif
> diff --git a/board/freescale/mx8mq_evk/Kconfig b/board/freescale/mx8mq_evk/Kconfig
> new file mode 100644
> index 0000000000..4e23002803
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_MX8MQ_EVK
> +
> +config SYS_BOARD
> + default "mx8mq_evk"
> +
> +config SYS_VENDOR
> + default "freescale"
> +
> +config SYS_CONFIG_NAME
> + default "mx8mq_evk"
> +
> +endif
> diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile
> new file mode 100644
> index 0000000000..60c99d4194
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/Makefile
> @@ -0,0 +1,11 @@
> +#
> +# Copyright 2017 NXP
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += mx8mq_evk.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +endif
> diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README
> new file mode 100644
> index 0000000000..6be5f51a22
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/README
> @@ -0,0 +1,38 @@
> +U-Boot for the NXP i.MX8MQ EVK board
> +
> +Quick Start
> +====================
> +- Build the ARM Trusted firmware binary
> +- Build U-Boot
> +- Generate flash.bin using imx-mkimage
> +- Boot
> +
> +Build the ARM Trusted firmware
> +====================
> +$ make PLAT=imx8mq bl31
> +
> +Build U-Boot
> +====================
> +$ export ARCH=arm64
> +$ export CROSS_COMPILE=aarch64-poky-linux-
> +$ make mx8mq_evk_defconfig
> +$ make
> +
> +Generate flash.bin using imx-mkimage
> +====================
> +Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to
> + imx-mkimage/iMX8M
> +Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin
> + lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to
> + imx-mkimage/iMX8M
> +If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M
> +
> +make SOC=iMX8M flash_spl_uboot or make SOC=iMX8M flash_hdmi_spl_uboot to
> +generate flash.bin.
> +
> +Burn the flash.bin to MicroSD card offset 33KB
> +$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
> +
> +Boot
> +====================
> +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
> diff --git a/board/freescale/mx8mq_evk/mx8mq_evk.c b/board/freescale/mx8mq_evk/mx8mq_evk.c
> new file mode 100644
> index 0000000000..e31678efb7
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/mx8mq_evk.c
> @@ -0,0 +1,156 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm-generic/gpio.h>
> +#include <fsl_esdhc.h>
> +#include <mmc.h>
> +#include <asm/arch/mx8mq_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/arch/clock.h>
> +#include <spl.h>
> +#include <power/pmic.h>
> +#include <power/pfuze100_pmic.h>
> +#include "../common/pfuze.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
> +
> +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +
> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> +};
> +
> +#ifdef CONFIG_FSL_QSPI
> +static iomux_v3_cfg_t const qspi_pads[] = {
> + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> +
> + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> +};
> +
> +int board_qspi_init(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
> +
> + set_clk_qspi();
> +
> + return 0;
> +}
> +#endif
> +
> +static iomux_v3_cfg_t const uart_pads[] = {
> + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +int board_early_init_f(void)
> +{
> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> + set_wdog_reset(wdog);
> +
> + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + /* rom_pointer[1] contains the size of TEE occupies */
> + if (rom_pointer[1])
> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> + else
> + gd->ram_size = PHYS_SDRAM_SIZE;
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_FEC_MXC
> +#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
> +static iomux_v3_cfg_t const fec1_rst_pads[] = {
> + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_fec(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
> + ARRAY_SIZE(fec1_rst_pads));
> +
> + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
> + gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
> + udelay(500);
> + gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
> +}
> +
> +static int setup_fec(void)
> +{
> + struct iomuxc_gpr_base_regs *gpr =
> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> + setup_iomux_fec();
> +
> + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
> + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
> + return set_clk_enet(ENET_125MHZ);
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> + return 0;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> + board_qspi_init();
> +
> +#ifdef CONFIG_FEC_MXC
> + setup_fec();
> +#endif
> +
> + return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> + return devno;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> + env_set("board_name", "EVK");
> + env_set("board_rev", "iMX8MQ");
> +#endif
> +
> + return 0;
> +}
> diff --git a/board/freescale/mx8mq_evk/spl.c b/board/freescale/mx8mq_evk/spl.c
> new file mode 100644
> index 0000000000..522d076124
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/spl.c
> @@ -0,0 +1,233 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/arch/mx8mq_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <power/pmic.h>
> +#include <power/pfuze100_pmic.h>
> +#include "../common/pfuze.h"
> +#include <asm/arch/clock.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <fsl_esdhc.h>
> +#include <mmc.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +__weak void ddr_init(void)
> +{
> +};
> +
This weak could be dropped, it was surely for test purpose :-)
> +void spl_dram_init(void)
> +{
> + /* ddr init */
> + ddr_init();
> +}
> +
> +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +struct i2c_pads_info i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
> + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
> + .gp = IMX_GPIO_NR(5, 14),
> + },
> + .sda = {
> + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
> + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
> + .gp = IMX_GPIO_NR(5, 15),
> + },
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
> +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC1_BASE_ADDR:
> + ret = 1;
> + break;
> + case USDHC2_BASE_ADDR:
> + ret = !gpio_get_value(USDHC2_CD_GPIO);
> + return ret;
> + }
> +
> + return 1;
> +}
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
> + PAD_CTL_FSEL2)
> +
> +static iomux_v3_cfg_t const usdhc1_pads[] = {
> + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> + {USDHC1_BASE_ADDR, 0, 8},
> + {USDHC2_BASE_ADDR, 0, 4},
> +};
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + int i, ret;
> + /*
> + * According to the board_mmc_init() the following map is done:
> + * (U-Boot device node) (Physical Port)
> + * mmc0 USDHC1
> + * mmc1 USDHC2
> + */
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + init_clk_usdhc(0);
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
> + gpio_direction_output(USDHC1_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC1_PWR_GPIO, 1);
> + break;
> + case 1:
> + init_clk_usdhc(1);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
> + break;
> + default:
> + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
> + return -EINVAL;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_POWER
> +#define I2C_PMIC 0
> +int power_init_board(void)
> +{
> + struct pmic *p;
> + int ret;
> + unsigned int reg;
> +
> + ret = power_pfuze100_init(I2C_PMIC);
> + if (ret)
> + return -ENODEV;
> +
> + p = pmic_get("PFUZE100");
> + ret = pmic_probe(p);
> + if (ret)
> + return -ENODEV;
> +
> + pmic_reg_read(p, PFUZE100_DEVICEID, ®);
> + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
> +
> + pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
> + if ((reg & 0x3f) != 0x18) {
> + reg &= ~0x3f;
> + reg |= 0x18;
> + pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
> + }
> +
> + ret = pfuze_mode_init(p, APS_PFM);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +#endif
> +
> +void spl_board_init(void)
> +{
> + enable_tzc380();
Just for my understanding: is this board specific ? Enabling the
TrustZone controller looks to me more general, but I am maybe wrong. Can
you better explain me this ? Thanks !
> +
> + /* Adjust pmic voltage to 1.0V for 800M */
> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +
> + power_init_board();
> +
> + /* DDR initialization */
> + spl_dram_init();
> +
> + /* Serial download mode */
> + if (is_usb_boot()) {
> + puts("Back to ROM, SDP\n");
> + restore_boot_params();
> + }
> + puts("Normal Boot\n");
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + /* Just empty function now - can't decide what to choose */
> + debug("%s: %s\n", __func__, name);
> +
> + return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> + /* Clear global data */
> + memset((void *)gd, 0, sizeof(gd_t));
> +
> + arch_cpu_init();
> +
> + init_uart_clk(0);
> +
> + board_early_init_f();
> +
> + timer_init();
> +
> + preloader_console_init();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + board_init_r(NULL, 0);
> +}
> diff --git a/configs/mx8mq_evk_defconfig b/configs/mx8mq_evk_defconfig
> new file mode 100644
> index 0000000000..cee339d496
> --- /dev/null
> +++ b/configs/mx8mq_evk_defconfig
> @@ -0,0 +1,28 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX8M=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_MX8MQ_EVK=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
> +CONFIG_FIT=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
> +CONFIG_SPL=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_DM_MMC=y
> +CONFIG_DM_ETH=y
> +CONFIG_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_DM_PMIC_PFUZE100=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_PFUZE100=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_FS_FAT=y
> diff --git a/include/configs/mx8mq_evk.h b/include/configs/mx8mq_evk.h
> new file mode 100644
> index 0000000000..0a70733560
> --- /dev/null
> +++ b/include/configs/mx8mq_evk.h
> @@ -0,0 +1,265 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __IMX8M_EVK_H
> +#define __IMX8M_EVK_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
> +#endif
> +
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_TEXT_BASE 0x7E1000
> +#define CONFIG_SPL_MAX_SIZE (124 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +
> +#ifdef CONFIG_SPL_BUILD
> +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_BOARD_INIT
> +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK 0x187FF0
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_GPIO_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_BSS_START_ADDR 0x00180000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START 0x00182000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#undef CONFIG_DM_MMC
> +#undef CONFIG_DM_PMIC
> +#undef CONFIG_DM_PMIC_PFUZE100
> +
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#define CONFIG_POWER
> +#define CONFIG_POWER_I2C
> +#define CONFIG_POWER_PFUZE100
> +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
> +#endif
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_LATE_INIT
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +#undef CONFIG_CMD_IMLS
> +
> +#undef CONFIG_CMD_CRC32
> +#undef CONFIG_BOOTM_NETBSD
> +
> +/* ENET Config */
> +/* ENET1 */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_MII
> +#define CONFIG_ETHPRIME "FEC"
> +
> +#define CONFIG_FEC_MXC
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +#define FEC_QUIRK_ENET_MAC
> +
> +#define CONFIG_PHY_GIGE
> +#define IMX_FEC_BASE 0x30BE0000
> +
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_ATHEROS
> +#endif
> +
> +#define CONFIG_MFG_ENV_SETTINGS \
> + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
> + "rdinit=/linuxrc " \
> + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
> + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
> + "g_mass_storage.iSerialNumber=\"\" "\
> + "clk_ignore_unused "\
> + "\0" \
> + "initrd_addr=0x43800000\0" \
> + "initrd_high=0xffffffff\0" \
> + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + CONFIG_MFG_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=Image\0" \
> + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
> + "fdt_addr=0x43000000\0" \
> + "fdt_high=0xffffffffffffffff\0" \
> + "boot_fdt=try\0" \
> + "fdt_file=fsl-imx8mq-evk.dtb\0" \
> + "initrd_addr=0x43800000\0" \
> + "initrd_high=0xffffffffffffffff\0" \
> + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "mmcautodetect=yes\0" \
> + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
> + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> + "bootscript=echo Running bootscript from mmc ...; " \
> + "source\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if run loadfdt; then " \
> + "booti ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "else " \
> + "echo wait for boot; " \
> + "fi;\0" \
> + "netargs=setenv bootargs console=${console} " \
> + "root=/dev/nfs " \
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${loadaddr} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "booti ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "else " \
> + "booti; " \
> + "fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc dev ${mmcdev}; if mmc rescan; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "else run netboot; " \
> + "fi; " \
> + "fi; " \
> + "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR 0x40480000
> +#define CONFIG_SYS_TEXT_BASE 0x40200000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> +#define CONFIG_ENV_SIZE 0x1000
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
> +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +#define PHYS_SDRAM 0x40000000
> +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
> +#define CONFIG_NR_DRAM_BANKS 1
> +
> +#define CONFIG_BAUDRATE 115200
> +
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#undef CONFIG_SYS_PROMPT
> +#define CONFIG_SYS_PROMPT "u-boot=> "
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 1024
> +#define CONFIG_SYS_MAXARGS 64
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_CMDLINE_EDITING
> +
> +#define CONFIG_IMX_BOOTAUX
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_EXT4
> +#define CONFIG_CMD_EXT4_WRITE
> +#define CONFIG_CMD_FAT
> +
> +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +
> +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */
> +#ifdef CONFIG_FSL_QSPI
> +#define CONFIG_CMD_SF
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_STMICRO
> +#define CONFIG_SPI_FLASH_BAR
> +#define CONFIG_SF_DEFAULT_BUS 0
> +#define CONFIG_SF_DEFAULT_CS 0
> +#define CONFIG_SF_DEFAULT_SPEED 40000000
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> +
> +#define FSL_QSPI_FLASH_SIZE (SZ_32M)
> +#define FSL_QSPI_FLASH_NUM 1
> +#endif
> +
> +#define CONFIG_MXC_GPIO
> +
> +#define CONFIG_MXC_OCOTP
> +#define CONFIG_CMD_FUSE
> +
> +/* I2C Configs */
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +#define CONFIG_OF_SYSTEM_SETUP
> +
> +#endif
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 12/23] imx: mx8m: add soc related settings and files
2017-12-07 8:39 ` Stefano Babic
@ 2017-12-07 9:06 ` Peng Fan
0 siblings, 0 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-07 9:06 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Thu, Dec 07, 2017 at 09:39:23AM +0100, Stefano Babic wrote:
>Hi Peng,
>
>On 04/12/2017 05:31, Peng Fan wrote:
>> Add SoC level initialization code
>> - arch_cpu_init
>> - mmu table
>> - detect cpu revision
>> - reset cpu and wdog settings
>> - M4 boot
>> - timer init
>> - wdog settings
>> - lowlevel init to save/restore registers
>> - a few dummy header file to avoid build failure
>> - ft_system_setup and ft_add_optee_node
>> - mmc env related
>>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>> arch/arm/include/asm/arch-mx8m/crm_regs.h | 10 +
>> arch/arm/include/asm/arch-mx8m/gpio.h | 12 +
>> arch/arm/include/asm/arch-mx8m/sys_proto.h | 18 +
>> arch/arm/mach-imx/Makefile | 1 +
>> arch/arm/mach-imx/mx8m/Makefile | 3 +-
>> arch/arm/mach-imx/mx8m/lowlevel_init.S | 63 ++++
>> arch/arm/mach-imx/mx8m/soc.c | 539 +++++++++++++++++++++++++++++
>> 7 files changed, 645 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/include/asm/arch-mx8m/crm_regs.h
>> create mode 100644 arch/arm/include/asm/arch-mx8m/gpio.h
>> create mode 100644 arch/arm/include/asm/arch-mx8m/sys_proto.h
>> create mode 100644 arch/arm/mach-imx/mx8m/lowlevel_init.S
>> create mode 100644 arch/arm/mach-imx/mx8m/soc.c
>>
>> diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-mx8m/crm_regs.h
>> new file mode 100644
>> index 0000000000..6582318983
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-mx8m/crm_regs.h
>> @@ -0,0 +1,10 @@
>> +/*
>> + * Copyright 2017 NXP
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
>> +#define _ASM_ARCH_MX8M_CRM_REGS_H
>> +/* Dummy header, some imx-common code needs this file */
>> +#endif
>> diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-mx8m/gpio.h
>> new file mode 100644
>> index 0000000000..b666d37700
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-mx8m/gpio.h
>> @@ -0,0 +1,12 @@
>> +/*
>> + * Copyright 2017 NXP
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __ASM_ARCH_MX8M_GPIO_H
>> +#define __ASM_ARCH_MX8M_GPIO_H
>> +
>> +#include <asm/mach-imx/gpio.h>
>> +
>> +#endif
>> diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-mx8m/sys_proto.h
>> new file mode 100644
>> index 0000000000..8bf9ac6697
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-mx8m/sys_proto.h
>> @@ -0,0 +1,18 @@
>> +/*
>> + * Copyright (C) 2017 NXP
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __ARCH_MX8M_SYS_PROTO_H
>> +#define __ARCH_MX8M_SYS_PROTO_H
>> +
>> +#include <asm/mach-imx/sys_proto.h>
>> +
>> +void set_wdog_reset(struct wdog_regs *wdog);
>> +void enable_tzc380(void);
>> +void restore_boot_params(void);
>> +extern unsigned long rom_pointer[];
>> +enum boot_device get_boot_device(void);
>> +bool is_usb_boot(void);
>> +#endif
>> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>> index c807174363..27c154b8b3 100644
>> --- a/arch/arm/mach-imx/Makefile
>> +++ b/arch/arm/mach-imx/Makefile
>> @@ -127,4 +127,5 @@ obj-$(CONFIG_MX5) += mx5/
>> obj-$(CONFIG_MX6) += mx6/
>> obj-$(CONFIG_MX7) += mx7/
>> obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
>> +obj-$(CONFIG_MX8M) += mx8m/
>>
>> diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile
>> index 05f38842f0..b1c5d74aab 100644
>> --- a/arch/arm/mach-imx/mx8m/Makefile
>> +++ b/arch/arm/mach-imx/mx8m/Makefile
>> @@ -4,4 +4,5 @@
>> # SPDX-License-Identifier: GPL-2.0+
>> #
>>
>> -obj-y += clock.o clock_slice.o
>> +obj-y += lowlevel_init.o
>> +obj-y += clock.o clock_slice.o soc.o
>> diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/mx8m/lowlevel_init.S
>> new file mode 100644
>> index 0000000000..d388f3ba95
>> --- /dev/null
>> +++ b/arch/arm/mach-imx/mx8m/lowlevel_init.S
>> @@ -0,0 +1,63 @@
>> +/*
>> + * Copyright 2017 NXP
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <config.h>
>> +
>> +.align 8
>> +.global rom_pointer
>> +rom_pointer:
>> + .space 256
>> +
>> +/*
>> + * Routine: save_boot_params (called after reset from start.S)
>> + */
>> +
>> +.global save_boot_params
>> +save_boot_params:
>
>save_boot_params is a weak function, but there is a comment for it about
>that stack is not available at this point, any you are using the stack.
No stack usage. This is to save ROM context.
>
>And what about this with exception_entry / exception_exit ? Your looks a
>rewrite of functions in arch/arm/cpu/armv8/exceptions.S
I could not reuse exception_entry/exit. The SP is ROM SP, I would
not like to push data to ROM stack from U-Boot.
>
>> + /* The firmware provided ATAG/FDT address can be found in r2/x0 */
>> + adr x0, rom_pointer
>> + stp x1, x2, [x0], #16
>> + stp x3, x4, [x0], #16
>> + stp x5, x6, [x0], #16
>> + stp x7, x8, [x0], #16
>> + stp x9, x10, [x0], #16
>> + stp x11, x12, [x0], #16
>> + stp x13, x14, [x0], #16
>> + stp x15, x16, [x0], #16
>> + stp x17, x18, [x0], #16
>> + stp x19, x20, [x0], #16
>> + stp x21, x22, [x0], #16
>> + stp x23, x24, [x0], #16
>> + stp x25, x26, [x0], #16
>> + stp x27, x28, [x0], #16
>> + stp x29, x30, [x0], #16
>> + mov x30, sp
>> + str x30, [x0], #8
>> +
>> + /* Returns */
>> + b save_boot_params_ret
>> +
>> +.global restore_boot_params
>> +restore_boot_params:
>> + adr x0, rom_pointer
>> + ldp x1, x2, [x0], #16
>> + ldp x3, x4, [x0], #16
>> + ldp x5, x6, [x0], #16
>> + ldp x7, x8, [x0], #16
>> + ldp x9, x10, [x0], #16
>> + ldp x11, x12, [x0], #16
>> + ldp x13, x14, [x0], #16
>> + ldp x15, x16, [x0], #16
>> + ldp x17, x18, [x0], #16
>> + ldp x19, x20, [x0], #16
>> + ldp x21, x22, [x0], #16
>> + ldp x23, x24, [x0], #16
>> + ldp x25, x26, [x0], #16
>> + ldp x27, x28, [x0], #16
>> + ldp x29, x30, [x0], #16
>> + ldr x0, [x0]
>> + mov sp, x0
>> + ret
>> diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/mx8m/soc.c
>> new file mode 100644
>> index 0000000000..740e84caa4
>> --- /dev/null
>> +++ b/arch/arm/mach-imx/mx8m/soc.c
>> @@ -0,0 +1,539 @@
>> +/*
>> + * Copyright 2017 NXP
>> + *
>> + * Peng Fan <peng.fan@nxp.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <asm/mach-imx/hab.h>
>> +#include <asm/mach-imx/boot_mode.h>
>> +#include <asm/mach-imx/syscounter.h>
>> +#include <asm/armv8/mmu.h>
>> +#include <errno.h>
>> +#include <fdt_support.h>
>> +#include <fsl_wdog.h>
>> +#include <imx_sip.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#if defined(CONFIG_SECURE_BOOT)
>> +struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
>> + .bank = 1,
>> + .word = 3,
>> +};
>> +#endif
>> +
>> +/*
>> + * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
>> + * defines a 2-bit SPEED_GRADING
>> + */
>> +#define OCOTP_TESTER3_SPEED_SHIFT 8
>> +#define OCOTP_TESTER3_SPEED_800MHZ 0
>> +#define OCOTP_TESTER3_SPEED_1GHZ 1
>> +#define OCOTP_TESTER3_SPEED_1300MHZ 2
>> +#define OCOTP_TESTER3_SPEED_1500MHZ 3
>> +
>> +u32 get_cpu_speed_grade_hz(void)
>> +{
>> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
>> + struct fuse_bank *bank = &ocotp->bank[1];
>> + struct fuse_bank1_regs *fuse =
>> + (struct fuse_bank1_regs *)bank->fuse_regs;
>> + u32 val;
>> +
>> + val = readl(&fuse->tester3);
>> + val >>= OCOTP_TESTER3_SPEED_SHIFT;
>> + val &= 0x3;
>> +
>> + switch (val) {
>> + case OCOTP_TESTER3_SPEED_800MHZ:
>> + return 800000000;
>> + case OCOTP_TESTER3_SPEED_1GHZ:
>> + return 1000000000;
>> + case OCOTP_TESTER3_SPEED_1300MHZ:
>> + return 1300000000;
>> + case OCOTP_TESTER3_SPEED_1500MHZ:
>> + return 1500000000;
>> + }
>> + return 0;
>> +}
>> +
>> +/*
>> + * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
>> + * defines a 2-bit SPEED_GRADING
>> + */
>> +#define OCOTP_TESTER3_TEMP_SHIFT 6
>> +
>> +/* CPU Temperature Grades */
>> +#define TEMP_COMMERCIAL 0
>> +#define TEMP_EXTCOMMERCIAL 1
>> +#define TEMP_INDUSTRIAL 2
>> +#define TEMP_AUTOMOTIVE 3
>> +
>> +u32 get_cpu_temp_grade(int *minc, int *maxc)
>> +{
>> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
>> + struct fuse_bank *bank = &ocotp->bank[1];
>> + struct fuse_bank1_regs *fuse =
>> + (struct fuse_bank1_regs *)bank->fuse_regs;
>> + u32 val;
>> +
>> + val = readl(&fuse->tester3);
>> + val >>= OCOTP_TESTER3_TEMP_SHIFT;
>> + val &= 0x3;
>> +
>> + if (minc && maxc) {
>> + if (val == TEMP_AUTOMOTIVE) {
>> + *minc = -40;
>> + *maxc = 125;
>> + } else if (val == TEMP_INDUSTRIAL) {
>> + *minc = -40;
>> + *maxc = 105;
>> + } else if (val == TEMP_EXTCOMMERCIAL) {
>> + *minc = -20;
>> + *maxc = 105;
>> + } else {
>> + *minc = 0;
>> + *maxc = 95;
>> + }
>> + }
>> + return val;
>> +}
>
>Even if they appear cross-architecture: get_cpu_speed_grade_hz() and
>get_cpu_temp_grade() are very similar to the function in mx6/soc.c and
>(*sigh*) in mx7/soc.c. This becomes the *third* duplication of the same
>code. Can we factorize this and put the function in a file under
>mach-imx, shared between mx6/mx7/mx8m ?
>
>The expectation is mac-imx/mxX contains just specific code for that
>architecture, while common code can flow into mach-imx.
The mx8m could share with mx7. But mx6 use different fuse banks.
I'll try.
>
>> +
>> +int timer_init(void)
>> +{
>> +#ifdef CONFIG_SPL_BUILD
>> + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
>> + unsigned long freq = readl(&sctr->cntfid0);
>> +
>> + /* Update with accurate clock frequency */
>> + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
>> +
>> + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
>> + SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
>> +#endif
>> +
>> + gd->arch.tbl = 0;
>> + gd->arch.tbu = 0;
>> +
>> + return 0;
>> +}
>> > +void enable_tzc380(void)
>> +{
>> + struct iomuxc_gpr_base_regs *gpr =
>> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>> +
>> + /* Enable TZASC and lock setting */
>> + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
>> + setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
>> +}
>> +
>> +void set_wdog_reset(struct wdog_regs *wdog)
>> +{
>> + /*
>> + * Output WDOG_B signal to reset external pmic or POR_B decided by
>> + * the board desgin.
>
>s/desgin/design/
Fix in V3.
>
>> Without external reset, the peripherals/DDR/
>> + * PMIC are not reset, that may cause system working abnormal.
>> + * WDZST bit is write-once only bit. Align this bit in kernel,
>> + * otherwise kernel code will have no chance to set this bit.
>> + */
>> + setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
>> +}
>> +
>> +static struct mm_region imx8m_mem_map[] = {
>> + {
>> + .virt = 0x0UL,
>> + .phys = 0x0UL,
>> + .size = 0x100000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>> + PTE_BLOCK_OUTER_SHARE
>> + }, {
>> + .virt = 0x100000UL,
>> + .phys = 0x100000UL,
>> + .size = 0x8000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>> + PTE_BLOCK_NON_SHARE |
>> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
>> + }, {
>> + .virt = 0x7C0000UL,
>> + .phys = 0x7C0000UL,
>> + .size = 0x80000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>> + PTE_BLOCK_NON_SHARE |
>> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
>> + }, {
>> + .virt = 0x900000UL,
>> + .phys = 0x900000UL,
>> + .size = 0x200000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>> + PTE_BLOCK_OUTER_SHARE
>> + }, {
>> + .virt = 0xB00000UL,
>> + .phys = 0xB00000UL,
>> + .size = 0x3f500000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>> + PTE_BLOCK_NON_SHARE |
>> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
>> + }, {
>> + .virt = 0x40000000UL,
>> + .phys = 0x40000000UL,
>> + .size = 0xC0000000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>> + PTE_BLOCK_OUTER_SHARE
>> + }, {
>> + .virt = 0x100000000UL,
>> + .phys = 0x100000000UL,
>> + .size = 0x040000000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>> + PTE_BLOCK_OUTER_SHARE
>> + }, {
>> + /* List terminator */
>> + 0,
>> + }
>> +};
>> +
>
>If you can, taking into account that currently documentation is scarce
>or missing, can you add comments to each entry to explain each region ?
>Thanks !
Will add in V3.
>
>> +struct mm_region *mem_map = imx8m_mem_map;
>> +
>> +u32 get_cpu_rev(void)
>> +{
>> + struct anamix_pll *ana_pll = (struct anamix_pll *)ANA_PLL_BASE_ADDR;
>
>This require a small explanation. My point: I would like that registers
>with the same meaning could have the same name, even if defined in
>different files according to the i.MX variants.
>
>This looks a base address and it is ANATOP_BASE_ADDR for other
>architectures. Any reason for changing it ? Can we at least try to use
>the same nomenclature across i.MX processors ?
I just use the name(ANA_PLL) from DOC.
It is ok for me use ANATOP_BASE_ADDR.
>
>> + u32 reg = readl(&ana_pll->digprog);
>> + u32 type = (reg >> 16) & 0xff;
>> + u32 rom_version;
>> +
>> + reg &= 0xff;
>> +
>> + if (reg == 0x10) {
>> + /*
>> + * For B0 chip, the DIGPROG is not updated, still TO1.0.
>> + * we have to check ROM version further
>> + */
>> + rom_version = readl((void __iomem *)0x800);
>
>Has a name this address ? Something like SCU_BASE_ADDR (just copied the
>name, no idea if it is correct ) ?
>
>I prefer to remove magic addresses like 0x800, 0x83c and use define for
>them.
ok. Fix in V3.
>
>> + if (rom_version != 0x10) {
>> + rom_version = readl((void __iomem *)0x83c);
>> + if (rom_version >= 0x20)
>> + reg = 0x20;
>> + }
>> + }
>> +
>> + return (type << 12) | reg;
>> +}
>> +
>> +static void imx_set_wdog_powerdown(bool enable)
>> +{
>> + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
>> + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
>> + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
>> +
>> + /* Write to the PDE (Power Down Enable) bit */
>> + writew(enable, &wdog1->wmcr);
>> + writew(enable, &wdog2->wmcr);
>> + writew(enable, &wdog3->wmcr);
>> +}
>> +
>> +int arch_cpu_init(void)
>> +{
>> + /*
>> + * Init timer at very early state, because sscg pll setting
>> + * will use it
>> + */
>> + timer_init();
>> +
>> + if (IS_ENABLED(CONFIG_SPL_BUILD)) {
>> + clock_init();
>> + imx_set_wdog_powerdown(false);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +#if defined(CONFIG_FEC_MXC)
>> +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
>> +{
>> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
>> + struct fuse_bank *bank = &ocotp->bank[9];
>> + struct fuse_bank9_regs *fuse =
>> + (struct fuse_bank9_regs *)bank->fuse_regs;
>> + u32 value = readl(&fuse->mac_addr1);
>> +
>> + mac[0] = (value >> 8);
>> + mac[1] = value;
>> +
>> + value = readl(&fuse->mac_addr0);
>> + mac[2] = value >> 24;
>> + mac[3] = value >> 16;
>> + mac[4] = value >> 8;
>> + mac[5] = value;
>> +}
>
>This is the last copy of imx_get_mac_from_fuse() that we introduce in
>U-Boot. At least the 3rd copy, and it is time to factorize them. All
>functions are doing the same !
ok. I'll try to factorize them, but mx6 use different fuse banks.
>
>> +#endif
>> +
>> +#ifdef CONFIG_IMX_BOOTAUX
>> +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
>> +{
>> + u32 stack, pc;
>> +
>> + if (!boot_private_data)
>> + return -EINVAL;
>> +
>> + stack = *(u32 *)boot_private_data;
>> + pc = *(u32 *)(boot_private_data + 4);
>> +
>> + /* Set the stack and pc to M4 bootROM */
>> + writel(stack, M4_BOOTROM_BASE_ADDR);
>> + writel(pc, M4_BOOTROM_BASE_ADDR + 4);
>> +
>> + /* Enable M4 */
>> + call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
>> +
>> + return 0;
>> +}
>
>Quite the same, apart sip call, and this can be factorized, too.
Ok.
>
>> +
>> +int arch_auxiliary_core_check_up(u32 core_id)
>> +{
>> + return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
>> +}
>> +#endif
>> +
>> +enum boot_device get_boot_device(void)
>> +{
>> + struct bootrom_sw_info **p =
>> + is_soc_rev(CHIP_REV_1_0) ?
>> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
>> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
>> +
>> + enum boot_device boot_dev = SD1_BOOT;
>> + u8 boot_type = (*p)->boot_dev_type;
>> + u8 boot_instance = (*p)->boot_dev_instance;
>> +
>> + switch (boot_type) {
>> + case BOOT_TYPE_SD:
>> + boot_dev = boot_instance + SD1_BOOT;
>> + break;
>> + case BOOT_TYPE_MMC:
>> + boot_dev = boot_instance + MMC1_BOOT;
>> + break;
>> + case BOOT_TYPE_NAND:
>> + boot_dev = NAND_BOOT;
>> + break;
>> + case BOOT_TYPE_QSPI:
>> + boot_dev = QSPI_BOOT;
>> + break;
>> + case BOOT_TYPE_WEIM:
>> + boot_dev = WEIM_NOR_BOOT;
>> + break;
>> + case BOOT_TYPE_SPINOR:
>> + boot_dev = SPI_NOR_BOOT;
>> + break;
>> + case BOOT_TYPE_USB:
>> + boot_dev = USB_BOOT;
>> + break;
>> + default:
>> + break;
>> + }
>> +
>
>I suggest to add BOOT_TYPE_USB for all i.MXes and factorized this
>function, too. This is really identical to the one in
>arch/arm/mach-imx/mx7/soc.c
Ok.
>
>> + return boot_dev;
>> +}
>> +
>> +bool is_usb_boot(void)
>> +{
>> + return get_boot_device() == USB_BOOT;
>> +}
>> +
>> +#ifdef CONFIG_ENV_IS_IN_MMC
>> +__weak int board_mmc_get_env_dev(int devno)
>> +{
>> + return CONFIG_SYS_MMC_ENV_DEV;
>> +}
>> +
>> +int mmc_get_env_dev(void)
>> +{
>> + struct bootrom_sw_info **p =
>> + is_soc_rev(CHIP_REV_1_0) ?
>> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
>> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
>> + int devno = (*p)->boot_dev_instance;
>> + u8 boot_type = (*p)->boot_dev_type;
>> +
>> + /* If not boot from sd/mmc, use default value */
>> + if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
>> + return CONFIG_SYS_MMC_ENV_DEV;
>> +
>> + return board_mmc_get_env_dev(devno);
>> +}
>
>Quite the same for mmc_get_env_dev()
>
>I sumarize: as you explained, there are much more similarities with imx6
>/ imx7 in MX8M. This means we can share the same code between arch, at
>least between i.MX7 and i.MX8M (but, ideally, as much as we can).
ok.
>
>> +#endif
>> +
>> +#ifdef CONFIG_OF_SYSTEM_SETUP
>> +static int ft_add_optee_node(void *fdt, bd_t *bd)
>> +{
>> + const char *path, *subpath;
>> + int offs;
>> +
>> + /*
>> + * No TEE space allocated indicating no TEE running, so no
>> + * need to add optee node in dts
>> + */
>> + if (!rom_pointer[1])
>> + return 0;
>> +
>> + offs = fdt_increase_size(fdt, 512);
>> + if (offs) {
>> + printf("No Space for dtb\n");
>> + return offs;
>> + }
>> +
>> + path = "/firmware";
>> + offs = fdt_path_offset(fdt, path);
>> + if (offs < 0) {
>> + path = "/";
>> + offs = fdt_path_offset(fdt, path);
>> +
>> + if (offs < 0) {
>> + printf("Could not find root node.\n");
>> + return offs;
>> + }
>> +
>> + subpath = "firmware";
>> + offs = fdt_add_subnode(fdt, offs, subpath);
>> + if (offs < 0) {
>> + printf("Could not create %s node.\n", subpath);
>> + return offs;
>> + }
>> + }
>> +
>> + subpath = "optee";
>> + offs = fdt_add_subnode(fdt, offs, subpath);
>> + if (offs < 0) {
>> + printf("Could not create %s node.\n", subpath);
>> + return offs;
>> + }
>> +
>> + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
>> + fdt_setprop_string(fdt, offs, "method", "smc");
>> +
>> + return 0;
>> +}
>
>This has nothing to do with the specific SOC and should be moved.
For MX6/7, no need this code. Now only MX8M needs this code, so
could this be moved later when more needs it?
>
>> +
>> +int ft_system_setup(void *blob, bd_t *bd)
>> +{
>> + static const char * const status = "disabled";
>> + static const char * const usb_dwc3_path = "/usb at 38100000/dwc3";
>> + static const char * const speed = "high-speed";
>> + int i = 0;
>> + int rc;
>> + int nodeoff;
>> +
>> + if (get_boot_device() == USB_BOOT) {
>> + static const char * const nodes_path[] = {
>> + "/dcss at 32e00000",
>> + "/hdmi at 32c00000",
>> + "/hdmi_cec at 32c33800",
>> + "/hdmi_drm at 32c00000",
>> + "/display-subsystem",
>> + "/sound-hdmi"
>> + };
>> +
>
>This should be moved, too, but why do we increase blob size if boot
>device is USB ?
This is MX8M specific. The following code will modify dtb
,to avoid NOSPACE error, we increase blob size.
Thanks,
Peng.
--
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support
2017-12-07 8:52 ` Stefano Babic
@ 2017-12-07 9:13 ` Peng Fan
2017-12-07 9:27 ` Stefano Babic
2017-12-07 9:28 ` Stefano Babic
0 siblings, 2 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-07 9:13 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Thu, Dec 07, 2017 at 09:52:46AM +0100, Stefano Babic wrote:
>Hi Peng,
>
>On 04/12/2017 05:31, Peng Fan wrote:
>> Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
>> firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
>> DRAM.
>>
>> The boot log:
>> "
>> U-Boot SPL 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31)
>> PMIC: PFUZE100 ID=0x10
>> check ddr4_pmu_train_imem code
>> check ddr4_pmu_train_imem code pass
>> check ddr4_pmu_train_dmem code
>> check ddr4_pmu_train_dmem code pass
>> PLL bypass to 100MTS setting done
>> Training PASS
>> PLL bypass to 400MTS setting done
>> Training PASS
>> Training PASS
>> check ddr4_pmu_train_imem code
>> check ddr4_pmu_train_imem code pass
>> check ddr4_pmu_train_dmem code
>> check ddr4_pmu_train_dmem code pass
>> Training PASS
>> Normal Boot
>> Trying to boot from MMC2
>>
>> U-Boot 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31 +0800)
>>
>> CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz
>> Reset cause: POR
>> Model: Freescale i.MX8MQ EVK
>> DRAM: 3 GiB
>> MMC: FSL_SDHC: 0, FSL_SDHC: 1
>> Using default environment
>>
>> In: serial
>> Out: serial
>> Err: serial
>> Net: No ethernet found.
>> Hit any key to stop autoboot: 0
>> "
>>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>> arch/arm/dts/Makefile | 2 +
>> arch/arm/dts/fsl-imx8mq-evk.dts | 424 ++++++++++++++++++++++++++++++++++
>> arch/arm/mach-imx/mx8m/Kconfig | 12 +
>> board/freescale/mx8mq_evk/Kconfig | 12 +
>> board/freescale/mx8mq_evk/Makefile | 11 +
>> board/freescale/mx8mq_evk/README | 38 +++
>> board/freescale/mx8mq_evk/mx8mq_evk.c | 156 +++++++++++++
>> board/freescale/mx8mq_evk/spl.c | 233 +++++++++++++++++++
>> configs/mx8mq_evk_defconfig | 28 +++
>> include/configs/mx8mq_evk.h | 265 +++++++++++++++++++++
>> 10 files changed, 1181 insertions(+)
>> create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
>> create mode 100644 board/freescale/mx8mq_evk/Kconfig
>> create mode 100644 board/freescale/mx8mq_evk/Makefile
>> create mode 100644 board/freescale/mx8mq_evk/README
>> create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
>> create mode 100644 board/freescale/mx8mq_evk/spl.c
>> create mode 100644 configs/mx8mq_evk_defconfig
>> create mode 100644 include/configs/mx8mq_evk.h
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index cd540e99ea..d459755904 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -381,6 +381,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
>>
>> dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>>
>> +dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb
>> +
>> dtb-$(CONFIG_RCAR_GEN3) += \
>> r8a7795-h3ulcb.dtb \
>> r8a7795-salvator-x.dtb \
>> diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
>> new file mode 100644
>> index 0000000000..f0aa3485e6
>> --- /dev/null
>> +++ b/arch/arm/dts/fsl-imx8mq-evk.dts
>> @@ -0,0 +1,424 @@
>> +/*
>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>> + * Copyright 2017 NXP
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version 2
>> + * of the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +/* First 128KB is for PSCI ATF. */
>> +/memreserve/ 0x40000000 0x00020000;
>> +
>> +#include "fsl-imx8mq.dtsi"
>> +
>> +/ {
>> + model = "Freescale i.MX8MQ EVK";
>> + compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
>> +
>> + chosen {
>> + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
>> + };
>> +
>> + regulators {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + reg_usdhc2_vmmc: usdhc2_vmmc {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VSD_3V3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> + };
>> +
>> + pwmleds {
>> + compatible = "pwm-leds";
>> +
>> + ledpwm2 {
>> + label = "PWM2";
>> + pwms = <&pwm2 0 50000>;
>> + max-brightness = <255>;
>> + };
>> + };
>> +};
>> +
>> +&iomuxc {
>> + pinctrl-names = "default";
>> +
>> + imx8mq-evk {
>> + pinctrl_fec1: fec1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
>> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
>> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
>> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
>> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
>> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
>> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>> + >;
>> + };
>> +
>> + pinctrl_i2c1: i2c1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
>> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
>> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>> + >;
>> + };
>> +
>> + pinctrl_pwm2: pwm2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
>> + >;
>> + };
>> +
>> + pinctrl_qspi: qspigrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
>> + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
>> + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
>> + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
>> + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
>> + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>> +
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>> + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_sai2: sai2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
>> + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
>> + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
>> + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
>> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>> + >;
>> + };
>> +
>> + pinctrl_wdog: wdoggrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>> + >;
>> + };
>> + };
>> +};
>> +
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_fec1>;
>> + phy-mode = "rgmii-id";
>> + phy-handle = <ðphy0>;
>> + fsl,magic-packet;
>> + status = "okay";
>> +
>> + mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy at 0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <0>;
>> + at803x,led-act-blind-workaround;
>> + at803x,eee-disabled;
>> + };
>> + };
>> +};
>> +
>> +&i2c1 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + status = "okay";
>> +
>> + pmic: pfuze100 at 08 {
>> + compatible = "fsl,pfuze100";
>> + reg = <0x08>;
>> +
>> + regulators {
>> + sw1a_reg: sw1ab {
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1875000>;
>> + regulator-always-on;
>> + };
>> +
>> + sw1c_reg: sw1c {
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1875000>;
>> + regulator-always-on;
>> + };
>> +
>> + sw2_reg: sw2 {
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + sw3a_reg: sw3ab {
>> + regulator-min-microvolt = <400000>;
>> + regulator-max-microvolt = <1975000>;
>> + regulator-always-on;
>> + };
>> +
>> + sw4_reg: sw4 {
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + swbst_reg: swbst {
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5150000>;
>> + };
>> +
>> + snvs_reg: vsnvs {
>> + regulator-min-microvolt = <1000000>;
>> + regulator-max-microvolt = <3000000>;
>> + regulator-always-on;
>> + };
>> +
>> + vref_reg: vrefddr {
>> + regulator-always-on;
>> + };
>> +
>> + vgen1_reg: vgen1 {
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <1550000>;
>> + };
>> +
>> + vgen2_reg: vgen2 {
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <1550000>;
>> + regulator-always-on;
>> + };
>> +
>> + vgen3_reg: vgen3 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + vgen4_reg: vgen4 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + vgen5_reg: vgen5 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + vgen6_reg: vgen6 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + status = "disabled";
>> +};
>> +
>> +&pwm2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm2>;
>> + status = "okay";
>> +};
>> +
>> +&lcdif {
>> + status = "okay";
>> + disp-dev = "mipi_dsi_northwest";
>> + display = <&display0>;
>> +
>> + display0: display at 0 {
>> + bits-per-pixel = <24>;
>> + bus-width = <24>;
>> +
>> + display-timings {
>> + native-mode = <&timing0>;
>> + timing0: timing0 {
>> + clock-frequency = <9200000>;
>> + hactive = <480>;
>> + vactive = <272>;
>> + hfront-porch = <8>;
>> + hback-porch = <4>;
>> + hsync-len = <41>;
>> + vback-porch = <2>;
>> + vfront-porch = <4>;
>> + vsync-len = <10>;
>> +
>> + hsync-active = <0>;
>> + vsync-active = <0>;
>> + de-active = <1>;
>> + pixelclk-active = <0>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&qspi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_qspi>;
>> + status = "okay";
>> +
>> + flash0: n25q256a at 0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "micron,n25q256a";
>> + spi-max-frequency = <29000000>;
>> + spi-nor,ddr-quad-read-dummy = <6>;
>> + };
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>> + bus-width = <8>;
>> + non-removable;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
>> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
>> + bus-width = <4>;
>> + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
>> + vmmc-supply = <®_usdhc2_vmmc>;
>> + status = "okay";
>> +};
>> +
>> +&wdog1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_wdog>;
>> + fsl,ext-reset-output;
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
>> index 3a84c2f2b0..e3b57b7915 100644
>> --- a/arch/arm/mach-imx/mx8m/Kconfig
>> +++ b/arch/arm/mach-imx/mx8m/Kconfig
>> @@ -7,4 +7,16 @@ config MX8M
>> config SYS_SOC
>> default "mx8m"
>>
>> +choice
>> + prompt "NXP i.MX8M board select"
>> + optional
>> +
>> +config TARGET_MX8MQ_EVK
>> + bool "mx8mq_evk"
>> + select MX8M
>> +
>> +endchoice
>> +
>> +source "board/freescale/mx8mq_evk/Kconfig"
>> +
>> endif
>> diff --git a/board/freescale/mx8mq_evk/Kconfig b/board/freescale/mx8mq_evk/Kconfig
>> new file mode 100644
>> index 0000000000..4e23002803
>> --- /dev/null
>> +++ b/board/freescale/mx8mq_evk/Kconfig
>> @@ -0,0 +1,12 @@
>> +if TARGET_MX8MQ_EVK
>> +
>> +config SYS_BOARD
>> + default "mx8mq_evk"
>> +
>> +config SYS_VENDOR
>> + default "freescale"
>> +
>> +config SYS_CONFIG_NAME
>> + default "mx8mq_evk"
>> +
>> +endif
>> diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile
>> new file mode 100644
>> index 0000000000..60c99d4194
>> --- /dev/null
>> +++ b/board/freescale/mx8mq_evk/Makefile
>> @@ -0,0 +1,11 @@
>> +#
>> +# Copyright 2017 NXP
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y += mx8mq_evk.o
>> +
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y += spl.o
>> +endif
>> diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README
>> new file mode 100644
>> index 0000000000..6be5f51a22
>> --- /dev/null
>> +++ b/board/freescale/mx8mq_evk/README
>> @@ -0,0 +1,38 @@
>> +U-Boot for the NXP i.MX8MQ EVK board
>> +
>> +Quick Start
>> +====================
>> +- Build the ARM Trusted firmware binary
>> +- Build U-Boot
>> +- Generate flash.bin using imx-mkimage
>> +- Boot
>> +
>> +Build the ARM Trusted firmware
>> +====================
>> +$ make PLAT=imx8mq bl31
>> +
>> +Build U-Boot
>> +====================
>> +$ export ARCH=arm64
>> +$ export CROSS_COMPILE=aarch64-poky-linux-
>> +$ make mx8mq_evk_defconfig
>> +$ make
>> +
>> +Generate flash.bin using imx-mkimage
>> +====================
>> +Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to
>> + imx-mkimage/iMX8M
>> +Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin
>> + lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to
>> + imx-mkimage/iMX8M
>> +If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M
>> +
>> +make SOC=iMX8M flash_spl_uboot or make SOC=iMX8M flash_hdmi_spl_uboot to
>> +generate flash.bin.
>> +
>> +Burn the flash.bin to MicroSD card offset 33KB
>> +$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
>> +
>> +Boot
>> +====================
>> +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
>> diff --git a/board/freescale/mx8mq_evk/mx8mq_evk.c b/board/freescale/mx8mq_evk/mx8mq_evk.c
>> new file mode 100644
>> index 0000000000..e31678efb7
>> --- /dev/null
>> +++ b/board/freescale/mx8mq_evk/mx8mq_evk.c
>> @@ -0,0 +1,156 @@
>> +/*
>> + * Copyright 2017 NXP
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <malloc.h>
>> +#include <errno.h>
>> +#include <asm/io.h>
>> +#include <miiphy.h>
>> +#include <netdev.h>
>> +#include <asm/mach-imx/iomux-v3.h>
>> +#include <asm-generic/gpio.h>
>> +#include <fsl_esdhc.h>
>> +#include <mmc.h>
>> +#include <asm/arch/mx8mq_pins.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <asm/mach-imx/gpio.h>
>> +#include <asm/mach-imx/mxc_i2c.h>
>> +#include <asm/arch/clock.h>
>> +#include <spl.h>
>> +#include <power/pmic.h>
>> +#include <power/pfuze100_pmic.h>
>> +#include "../common/pfuze.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
>> +
>> +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
>> +
>> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
>> +
>> +static iomux_v3_cfg_t const wdog_pads[] = {
>> + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
>> +};
>> +
>> +#ifdef CONFIG_FSL_QSPI
>> +static iomux_v3_cfg_t const qspi_pads[] = {
>> + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>> + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>> +
>> + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>> + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>> + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>> + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>> +};
>> +
>> +int board_qspi_init(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
>> +
>> + set_clk_qspi();
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static iomux_v3_cfg_t const uart_pads[] = {
>> + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +int board_early_init_f(void)
>> +{
>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
>> +
>> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
>> + set_wdog_reset(wdog);
>> +
>> + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
>> +
>> + return 0;
>> +}
>> +
>> +int dram_init(void)
>> +{
>> + /* rom_pointer[1] contains the size of TEE occupies */
>> + if (rom_pointer[1])
>> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
>> + else
>> + gd->ram_size = PHYS_SDRAM_SIZE;
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_FEC_MXC
>> +#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
>> +static iomux_v3_cfg_t const fec1_rst_pads[] = {
>> + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_fec(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
>> + ARRAY_SIZE(fec1_rst_pads));
>> +
>> + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
>> + gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
>> + udelay(500);
>> + gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
>> +}
>> +
>> +static int setup_fec(void)
>> +{
>> + struct iomuxc_gpr_base_regs *gpr =
>> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>> +
>> + setup_iomux_fec();
>> +
>> + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
>> + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
>> + return set_clk_enet(ENET_125MHZ);
>> +}
>> +
>> +int board_phy_config(struct phy_device *phydev)
>> +{
>> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
>> +
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>> +
>> + if (phydev->drv->config)
>> + phydev->drv->config(phydev);
>> + return 0;
>> +}
>> +#endif
>> +
>> +int board_init(void)
>> +{
>> + board_qspi_init();
>> +
>> +#ifdef CONFIG_FEC_MXC
>> + setup_fec();
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +int board_mmc_get_env_dev(int devno)
>> +{
>> + return devno;
>> +}
>> +
>> +int board_late_init(void)
>> +{
>> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>> + env_set("board_name", "EVK");
>> + env_set("board_rev", "iMX8MQ");
>> +#endif
>> +
>> + return 0;
>> +}
>> diff --git a/board/freescale/mx8mq_evk/spl.c b/board/freescale/mx8mq_evk/spl.c
>> new file mode 100644
>> index 0000000000..522d076124
>> --- /dev/null
>> +++ b/board/freescale/mx8mq_evk/spl.c
>> @@ -0,0 +1,233 @@
>> +/*
>> + * Copyright 2017 NXP
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <spl.h>
>> +#include <asm/io.h>
>> +#include <errno.h>
>> +#include <asm/io.h>
>> +#include <asm/mach-imx/iomux-v3.h>
>> +#include <asm/arch/mx8mq_pins.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <power/pmic.h>
>> +#include <power/pfuze100_pmic.h>
>> +#include "../common/pfuze.h"
>> +#include <asm/arch/clock.h>
>> +#include <asm/mach-imx/gpio.h>
>> +#include <asm/mach-imx/mxc_i2c.h>
>> +#include <fsl_esdhc.h>
>> +#include <mmc.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +__weak void ddr_init(void)
>> +{
>> +};
>> +
>
>This weak could be dropped, it was surely for test purpose :-)
I understand patch 23/23 about the ddr script, it is hard to be accepted.
So I add a weak function here to avoid build failure if other 22 patches
could be accepted. It may take long time to convert the ddr script to
structure based.
So would you like to me to drop it and keep 23/23 in V3, or keep the weak
ddr_init and drop 23/23 in V3?
>
>> +void spl_dram_init(void)
>> +{
>> + /* ddr init */
>> + ddr_init();
>> +}
>> +
>> +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>> +struct i2c_pads_info i2c_pad_info1 = {
>> + .scl = {
>> + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
>> + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
>> + .gp = IMX_GPIO_NR(5, 14),
>> + },
>> + .sda = {
>> + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
>> + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
>> + .gp = IMX_GPIO_NR(5, 15),
>> + },
>> +};
>> +
>> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
>> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
>> +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
>> +
>> +int board_mmc_getcd(struct mmc *mmc)
>> +{
>> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
>> + int ret = 0;
>> +
>> + switch (cfg->esdhc_base) {
>> + case USDHC1_BASE_ADDR:
>> + ret = 1;
>> + break;
>> + case USDHC2_BASE_ADDR:
>> + ret = !gpio_get_value(USDHC2_CD_GPIO);
>> + return ret;
>> + }
>> +
>> + return 1;
>> +}
>> +
>> +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
>> + PAD_CTL_FSEL2)
>> +
>> +static iomux_v3_cfg_t const usdhc1_pads[] = {
>> + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
>> +};
>> +
>> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
>> + {USDHC1_BASE_ADDR, 0, 8},
>> + {USDHC2_BASE_ADDR, 0, 4},
>> +};
>> +
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + int i, ret;
>> + /*
>> + * According to the board_mmc_init() the following map is done:
>> + * (U-Boot device node) (Physical Port)
>> + * mmc0 USDHC1
>> + * mmc1 USDHC2
>> + */
>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>> + switch (i) {
>> + case 0:
>> + init_clk_usdhc(0);
>> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
>> + imx_iomux_v3_setup_multiple_pads(
>> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
>> + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
>> + gpio_direction_output(USDHC1_PWR_GPIO, 0);
>> + udelay(500);
>> + gpio_direction_output(USDHC1_PWR_GPIO, 1);
>> + break;
>> + case 1:
>> + init_clk_usdhc(1);
>> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
>> + imx_iomux_v3_setup_multiple_pads(
>> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
>> + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
>> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
>> + udelay(500);
>> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
>> + break;
>> + default:
>> + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
>> + return -EINVAL;
>> + }
>> +
>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_POWER
>> +#define I2C_PMIC 0
>> +int power_init_board(void)
>> +{
>> + struct pmic *p;
>> + int ret;
>> + unsigned int reg;
>> +
>> + ret = power_pfuze100_init(I2C_PMIC);
>> + if (ret)
>> + return -ENODEV;
>> +
>> + p = pmic_get("PFUZE100");
>> + ret = pmic_probe(p);
>> + if (ret)
>> + return -ENODEV;
>> +
>> + pmic_reg_read(p, PFUZE100_DEVICEID, ®);
>> + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
>> +
>> + pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
>> + if ((reg & 0x3f) != 0x18) {
>> + reg &= ~0x3f;
>> + reg |= 0x18;
>> + pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
>> + }
>> +
>> + ret = pfuze_mode_init(p, APS_PFM);
>> + if (ret < 0)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +void spl_board_init(void)
>> +{
>> + enable_tzc380();
>
>Just for my understanding: is this board specific ? Enabling the
>TrustZone controller looks to me more general, but I am maybe wrong. Can
>you better explain me this ? Thanks !
If want to use TZC380 on i.MX, TZC380 needs to be enabled
before DDR initialization. So I put it in spl_board_init.
TZC380 enablement is not a must for all boards.
We will enable TEE on i.MX8MQ EVK board, so need to enable TZC380.
Thanks,
Peng
--
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support
2017-12-07 9:13 ` Peng Fan
@ 2017-12-07 9:27 ` Stefano Babic
2017-12-07 9:59 ` Peng Fan
2017-12-07 9:28 ` Stefano Babic
1 sibling, 1 reply; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 9:27 UTC (permalink / raw)
To: u-boot
Hi Peng,
On 07/12/2017 10:13, Peng Fan wrote:
> Hi Stefano,
>
> On Thu, Dec 07, 2017 at 09:52:46AM +0100, Stefano Babic wrote:
>> Hi Peng,
>>
>> On 04/12/2017 05:31, Peng Fan wrote:
>>> Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
>>> firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
>>> DRAM.
>>>
>>> The boot log:
>>> "
>>> U-Boot SPL 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31)
>>> PMIC: PFUZE100 ID=0x10
>>> check ddr4_pmu_train_imem code
>>> check ddr4_pmu_train_imem code pass
>>> check ddr4_pmu_train_dmem code
>>> check ddr4_pmu_train_dmem code pass
>>> PLL bypass to 100MTS setting done
>>> Training PASS
>>> PLL bypass to 400MTS setting done
>>> Training PASS
>>> Training PASS
>>> check ddr4_pmu_train_imem code
>>> check ddr4_pmu_train_imem code pass
>>> check ddr4_pmu_train_dmem code
>>> check ddr4_pmu_train_dmem code pass
>>> Training PASS
>>> Normal Boot
>>> Trying to boot from MMC2
>>>
>>> U-Boot 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31 +0800)
>>>
>>> CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz
>>> Reset cause: POR
>>> Model: Freescale i.MX8MQ EVK
>>> DRAM: 3 GiB
>>> MMC: FSL_SDHC: 0, FSL_SDHC: 1
>>> Using default environment
>>>
>>> In: serial
>>> Out: serial
>>> Err: serial
>>> Net: No ethernet found.
>>> Hit any key to stop autoboot: 0
>>> "
>>>
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>> ---
>>> arch/arm/dts/Makefile | 2 +
>>> arch/arm/dts/fsl-imx8mq-evk.dts | 424 ++++++++++++++++++++++++++++++++++
>>> arch/arm/mach-imx/mx8m/Kconfig | 12 +
>>> board/freescale/mx8mq_evk/Kconfig | 12 +
>>> board/freescale/mx8mq_evk/Makefile | 11 +
>>> board/freescale/mx8mq_evk/README | 38 +++
>>> board/freescale/mx8mq_evk/mx8mq_evk.c | 156 +++++++++++++
>>> board/freescale/mx8mq_evk/spl.c | 233 +++++++++++++++++++
>>> configs/mx8mq_evk_defconfig | 28 +++
>>> include/configs/mx8mq_evk.h | 265 +++++++++++++++++++++
>>> 10 files changed, 1181 insertions(+)
>>> create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
>>> create mode 100644 board/freescale/mx8mq_evk/Kconfig
>>> create mode 100644 board/freescale/mx8mq_evk/Makefile
>>> create mode 100644 board/freescale/mx8mq_evk/README
>>> create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
>>> create mode 100644 board/freescale/mx8mq_evk/spl.c
>>> create mode 100644 configs/mx8mq_evk_defconfig
>>> create mode 100644 include/configs/mx8mq_evk.h
>>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index cd540e99ea..d459755904 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -381,6 +381,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
>>>
>>> dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
>>>
>>> +dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb
>>> +
>>> dtb-$(CONFIG_RCAR_GEN3) += \
>>> r8a7795-h3ulcb.dtb \
>>> r8a7795-salvator-x.dtb \
>>> diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
>>> new file mode 100644
>>> index 0000000000..f0aa3485e6
>>> --- /dev/null
>>> +++ b/arch/arm/dts/fsl-imx8mq-evk.dts
>>> @@ -0,0 +1,424 @@
>>> +/*
>>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>>> + * Copyright 2017 NXP
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License
>>> + * as published by the Free Software Foundation; either version 2
>>> + * of the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +/* First 128KB is for PSCI ATF. */
>>> +/memreserve/ 0x40000000 0x00020000;
>>> +
>>> +#include "fsl-imx8mq.dtsi"
>>> +
>>> +/ {
>>> + model = "Freescale i.MX8MQ EVK";
>>> + compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
>>> +
>>> + chosen {
>>> + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
>>> + };
>>> +
>>> + regulators {
>>> + compatible = "simple-bus";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + reg_usdhc2_vmmc: usdhc2_vmmc {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "VSD_3V3";
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>>> + enable-active-high;
>>> + };
>>> + };
>>> +
>>> + pwmleds {
>>> + compatible = "pwm-leds";
>>> +
>>> + ledpwm2 {
>>> + label = "PWM2";
>>> + pwms = <&pwm2 0 50000>;
>>> + max-brightness = <255>;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&iomuxc {
>>> + pinctrl-names = "default";
>>> +
>>> + imx8mq-evk {
>>> + pinctrl_fec1: fec1grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
>>> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
>>> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
>>> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
>>> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
>>> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>>> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>>> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>>> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>>> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>>> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>>> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>>> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
>>> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>>> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>>> + >;
>>> + };
>>> +
>>> + pinctrl_i2c1: i2c1grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
>>> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>>> + >;
>>> + };
>>> +
>>> + pinctrl_i2c2: i2c2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
>>> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>>> + >;
>>> + };
>>> +
>>> + pinctrl_pwm2: pwm2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
>>> + >;
>>> + };
>>> +
>>> + pinctrl_qspi: qspigrp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
>>> + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
>>> + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>>> +
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc1: usdhc1grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
>>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
>>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
>>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
>>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
>>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
>>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
>>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
>>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
>>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
>>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
>>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
>>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>>> + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2: usdhc2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
>>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
>>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
>>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
>>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
>>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
>>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
>>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
>>> + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>>> + >;
>>> + };
>>> +
>>> + pinctrl_sai2: sai2grp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
>>> + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
>>> + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
>>> + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
>>> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>>> + >;
>>> + };
>>> +
>>> + pinctrl_wdog: wdoggrp {
>>> + fsl,pins = <
>>> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>>> + >;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&fec1 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_fec1>;
>>> + phy-mode = "rgmii-id";
>>> + phy-handle = <ðphy0>;
>>> + fsl,magic-packet;
>>> + status = "okay";
>>> +
>>> + mdio {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + ethphy0: ethernet-phy at 0 {
>>> + compatible = "ethernet-phy-ieee802.3-c22";
>>> + reg = <0>;
>>> + at803x,led-act-blind-workaround;
>>> + at803x,eee-disabled;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&i2c1 {
>>> + clock-frequency = <100000>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_i2c1>;
>>> + status = "okay";
>>> +
>>> + pmic: pfuze100 at 08 {
>>> + compatible = "fsl,pfuze100";
>>> + reg = <0x08>;
>>> +
>>> + regulators {
>>> + sw1a_reg: sw1ab {
>>> + regulator-min-microvolt = <300000>;
>>> + regulator-max-microvolt = <1875000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw1c_reg: sw1c {
>>> + regulator-min-microvolt = <300000>;
>>> + regulator-max-microvolt = <1875000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw2_reg: sw2 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw3a_reg: sw3ab {
>>> + regulator-min-microvolt = <400000>;
>>> + regulator-max-microvolt = <1975000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + sw4_reg: sw4 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + swbst_reg: swbst {
>>> + regulator-min-microvolt = <5000000>;
>>> + regulator-max-microvolt = <5150000>;
>>> + };
>>> +
>>> + snvs_reg: vsnvs {
>>> + regulator-min-microvolt = <1000000>;
>>> + regulator-max-microvolt = <3000000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vref_reg: vrefddr {
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen1_reg: vgen1 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <1550000>;
>>> + };
>>> +
>>> + vgen2_reg: vgen2 {
>>> + regulator-min-microvolt = <800000>;
>>> + regulator-max-microvolt = <1550000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen3_reg: vgen3 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen4_reg: vgen4 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen5_reg: vgen5 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + };
>>> +
>>> + vgen6_reg: vgen6 {
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + };
>>> + };
>>> + };
>>> +};
>>> +
>>> +&i2c2 {
>>> + clock-frequency = <100000>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_i2c2>;
>>> + status = "disabled";
>>> +};
>>> +
>>> +&pwm2 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_pwm2>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&lcdif {
>>> + status = "okay";
>>> + disp-dev = "mipi_dsi_northwest";
>>> + display = <&display0>;
>>> +
>>> + display0: display at 0 {
>>> + bits-per-pixel = <24>;
>>> + bus-width = <24>;
>>> +
>>> + display-timings {
>>> + native-mode = <&timing0>;
>>> + timing0: timing0 {
>>> + clock-frequency = <9200000>;
>>> + hactive = <480>;
>>> + vactive = <272>;
>>> + hfront-porch = <8>;
>>> + hback-porch = <4>;
>>> + hsync-len = <41>;
>>> + vback-porch = <2>;
>>> + vfront-porch = <4>;
>>> + vsync-len = <10>;
>>> +
>>> + hsync-active = <0>;
>>> + vsync-active = <0>;
>>> + de-active = <1>;
>>> + pixelclk-active = <0>;
>>> + };
>>> + };
>>> + };
>>> +};
>>> +
>>> +&qspi {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_qspi>;
>>> + status = "okay";
>>> +
>>> + flash0: n25q256a at 0 {
>>> + reg = <0>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + compatible = "micron,n25q256a";
>>> + spi-max-frequency = <29000000>;
>>> + spi-nor,ddr-quad-read-dummy = <6>;
>>> + };
>>> +};
>>> +
>>> +&usdhc1 {
>>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>> + pinctrl-0 = <&pinctrl_usdhc1>;
>>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>>> + bus-width = <8>;
>>> + non-removable;
>>> + status = "okay";
>>> +};
>>> +
>>> +&usdhc2 {
>>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>>> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
>>> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
>>> + bus-width = <4>;
>>> + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
>>> + vmmc-supply = <®_usdhc2_vmmc>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&wdog1 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_wdog>;
>>> + fsl,ext-reset-output;
>>> + status = "okay";
>>> +};
>>> diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
>>> index 3a84c2f2b0..e3b57b7915 100644
>>> --- a/arch/arm/mach-imx/mx8m/Kconfig
>>> +++ b/arch/arm/mach-imx/mx8m/Kconfig
>>> @@ -7,4 +7,16 @@ config MX8M
>>> config SYS_SOC
>>> default "mx8m"
>>>
>>> +choice
>>> + prompt "NXP i.MX8M board select"
>>> + optional
>>> +
>>> +config TARGET_MX8MQ_EVK
>>> + bool "mx8mq_evk"
>>> + select MX8M
>>> +
>>> +endchoice
>>> +
>>> +source "board/freescale/mx8mq_evk/Kconfig"
>>> +
>>> endif
>>> diff --git a/board/freescale/mx8mq_evk/Kconfig b/board/freescale/mx8mq_evk/Kconfig
>>> new file mode 100644
>>> index 0000000000..4e23002803
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/Kconfig
>>> @@ -0,0 +1,12 @@
>>> +if TARGET_MX8MQ_EVK
>>> +
>>> +config SYS_BOARD
>>> + default "mx8mq_evk"
>>> +
>>> +config SYS_VENDOR
>>> + default "freescale"
>>> +
>>> +config SYS_CONFIG_NAME
>>> + default "mx8mq_evk"
>>> +
>>> +endif
>>> diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile
>>> new file mode 100644
>>> index 0000000000..60c99d4194
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/Makefile
>>> @@ -0,0 +1,11 @@
>>> +#
>>> +# Copyright 2017 NXP
>>> +#
>>> +# SPDX-License-Identifier: GPL-2.0+
>>> +#
>>> +
>>> +obj-y += mx8mq_evk.o
>>> +
>>> +ifdef CONFIG_SPL_BUILD
>>> +obj-y += spl.o
>>> +endif
>>> diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README
>>> new file mode 100644
>>> index 0000000000..6be5f51a22
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/README
>>> @@ -0,0 +1,38 @@
>>> +U-Boot for the NXP i.MX8MQ EVK board
>>> +
>>> +Quick Start
>>> +====================
>>> +- Build the ARM Trusted firmware binary
>>> +- Build U-Boot
>>> +- Generate flash.bin using imx-mkimage
>>> +- Boot
>>> +
>>> +Build the ARM Trusted firmware
>>> +====================
>>> +$ make PLAT=imx8mq bl31
>>> +
>>> +Build U-Boot
>>> +====================
>>> +$ export ARCH=arm64
>>> +$ export CROSS_COMPILE=aarch64-poky-linux-
>>> +$ make mx8mq_evk_defconfig
>>> +$ make
>>> +
>>> +Generate flash.bin using imx-mkimage
>>> +====================
>>> +Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to
>>> + imx-mkimage/iMX8M
>>> +Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin
>>> + lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to
>>> + imx-mkimage/iMX8M
>>> +If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M
>>> +
>>> +make SOC=iMX8M flash_spl_uboot or make SOC=iMX8M flash_hdmi_spl_uboot to
>>> +generate flash.bin.
>>> +
>>> +Burn the flash.bin to MicroSD card offset 33KB
>>> +$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
>>> +
>>> +Boot
>>> +====================
>>> +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
>>> diff --git a/board/freescale/mx8mq_evk/mx8mq_evk.c b/board/freescale/mx8mq_evk/mx8mq_evk.c
>>> new file mode 100644
>>> index 0000000000..e31678efb7
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/mx8mq_evk.c
>>> @@ -0,0 +1,156 @@
>>> +/*
>>> + * Copyright 2017 NXP
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <malloc.h>
>>> +#include <errno.h>
>>> +#include <asm/io.h>
>>> +#include <miiphy.h>
>>> +#include <netdev.h>
>>> +#include <asm/mach-imx/iomux-v3.h>
>>> +#include <asm-generic/gpio.h>
>>> +#include <fsl_esdhc.h>
>>> +#include <mmc.h>
>>> +#include <asm/arch/mx8mq_pins.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +#include <asm/mach-imx/gpio.h>
>>> +#include <asm/mach-imx/mxc_i2c.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <spl.h>
>>> +#include <power/pmic.h>
>>> +#include <power/pfuze100_pmic.h>
>>> +#include "../common/pfuze.h"
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
>>> +
>>> +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
>>> +
>>> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
>>> +
>>> +static iomux_v3_cfg_t const wdog_pads[] = {
>>> + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
>>> +};
>>> +
>>> +#ifdef CONFIG_FSL_QSPI
>>> +static iomux_v3_cfg_t const qspi_pads[] = {
>>> + IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> +
>>> + IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> + IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
>>> +};
>>> +
>>> +int board_qspi_init(void)
>>> +{
>>> + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
>>> +
>>> + set_clk_qspi();
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +static iomux_v3_cfg_t const uart_pads[] = {
>>> + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +};
>>> +
>>> +int board_early_init_f(void)
>>> +{
>>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
>>> +
>>> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
>>> + set_wdog_reset(wdog);
>>> +
>>> + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int dram_init(void)
>>> +{
>>> + /* rom_pointer[1] contains the size of TEE occupies */
>>> + if (rom_pointer[1])
>>> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
>>> + else
>>> + gd->ram_size = PHYS_SDRAM_SIZE;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_FEC_MXC
>>> +#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
>>> +static iomux_v3_cfg_t const fec1_rst_pads[] = {
>>> + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> +};
>>> +
>>> +static void setup_iomux_fec(void)
>>> +{
>>> + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
>>> + ARRAY_SIZE(fec1_rst_pads));
>>> +
>>> + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
>>> + gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
>>> + udelay(500);
>>> + gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
>>> +}
>>> +
>>> +static int setup_fec(void)
>>> +{
>>> + struct iomuxc_gpr_base_regs *gpr =
>>> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
>>> +
>>> + setup_iomux_fec();
>>> +
>>> + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
>>> + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
>>> + return set_clk_enet(ENET_125MHZ);
>>> +}
>>> +
>>> +int board_phy_config(struct phy_device *phydev)
>>> +{
>>> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
>>> +
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>>> +
>>> + if (phydev->drv->config)
>>> + phydev->drv->config(phydev);
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +int board_init(void)
>>> +{
>>> + board_qspi_init();
>>> +
>>> +#ifdef CONFIG_FEC_MXC
>>> + setup_fec();
>>> +#endif
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int board_mmc_get_env_dev(int devno)
>>> +{
>>> + return devno;
>>> +}
>>> +
>>> +int board_late_init(void)
>>> +{
>>> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>>> + env_set("board_name", "EVK");
>>> + env_set("board_rev", "iMX8MQ");
>>> +#endif
>>> +
>>> + return 0;
>>> +}
>>> diff --git a/board/freescale/mx8mq_evk/spl.c b/board/freescale/mx8mq_evk/spl.c
>>> new file mode 100644
>>> index 0000000000..522d076124
>>> --- /dev/null
>>> +++ b/board/freescale/mx8mq_evk/spl.c
>>> @@ -0,0 +1,233 @@
>>> +/*
>>> + * Copyright 2017 NXP
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <spl.h>
>>> +#include <asm/io.h>
>>> +#include <errno.h>
>>> +#include <asm/io.h>
>>> +#include <asm/mach-imx/iomux-v3.h>
>>> +#include <asm/arch/mx8mq_pins.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +#include <power/pmic.h>
>>> +#include <power/pfuze100_pmic.h>
>>> +#include "../common/pfuze.h"
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/mach-imx/gpio.h>
>>> +#include <asm/mach-imx/mxc_i2c.h>
>>> +#include <fsl_esdhc.h>
>>> +#include <mmc.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +__weak void ddr_init(void)
>>> +{
>>> +};
>>> +
>>
>> This weak could be dropped, it was surely for test purpose :-)
>
> I understand patch 23/23 about the ddr script, it is hard to be accepted.
> So I add a weak function here to avoid build failure if other 22 patches
> could be accepted. It may take long time to convert the ddr script to
> structure based.
Ok, understand.
>
> So would you like to me to drop it and keep 23/23 in V3, or keep the weak
> ddr_init and drop 23/23 in V3?
Thing is that this patch is dead code without DDR setup. I am ready to
merge reviewed patch, even if they add MX8M and there is not yet any
board using - theoretically, this is also dead code and I could not. But
this simplifies the development and you can reduce the number of patches
to be posted next time. But merging a board that is known to be broken
due to a missing part, it is nonsense. Board will be merged when we have
a suitable way to set the DDR controller.
Regards,
Stefano
>
>>
>>> +void spl_dram_init(void)
>>> +{
>>> + /* ddr init */
>>> + ddr_init();
>>> +}
>>> +
>>> +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
>>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>>> +struct i2c_pads_info i2c_pad_info1 = {
>>> + .scl = {
>>> + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
>>> + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
>>> + .gp = IMX_GPIO_NR(5, 14),
>>> + },
>>> + .sda = {
>>> + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
>>> + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
>>> + .gp = IMX_GPIO_NR(5, 15),
>>> + },
>>> +};
>>> +
>>> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
>>> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
>>> +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
>>> +
>>> +int board_mmc_getcd(struct mmc *mmc)
>>> +{
>>> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
>>> + int ret = 0;
>>> +
>>> + switch (cfg->esdhc_base) {
>>> + case USDHC1_BASE_ADDR:
>>> + ret = 1;
>>> + break;
>>> + case USDHC2_BASE_ADDR:
>>> + ret = !gpio_get_value(USDHC2_CD_GPIO);
>>> + return ret;
>>> + }
>>> +
>>> + return 1;
>>> +}
>>> +
>>> +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
>>> + PAD_CTL_FSEL2)
>>> +
>>> +static iomux_v3_cfg_t const usdhc1_pads[] = {
>>> + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> +};
>>> +
>>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>>> + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> +};
>>> +
>>> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
>>> + {USDHC1_BASE_ADDR, 0, 8},
>>> + {USDHC2_BASE_ADDR, 0, 4},
>>> +};
>>> +
>>> +int board_mmc_init(bd_t *bis)
>>> +{
>>> + int i, ret;
>>> + /*
>>> + * According to the board_mmc_init() the following map is done:
>>> + * (U-Boot device node) (Physical Port)
>>> + * mmc0 USDHC1
>>> + * mmc1 USDHC2
>>> + */
>>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>>> + switch (i) {
>>> + case 0:
>>> + init_clk_usdhc(0);
>>> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
>>> + imx_iomux_v3_setup_multiple_pads(
>>> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
>>> + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
>>> + gpio_direction_output(USDHC1_PWR_GPIO, 0);
>>> + udelay(500);
>>> + gpio_direction_output(USDHC1_PWR_GPIO, 1);
>>> + break;
>>> + case 1:
>>> + init_clk_usdhc(1);
>>> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
>>> + imx_iomux_v3_setup_multiple_pads(
>>> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
>>> + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
>>> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
>>> + udelay(500);
>>> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
>>> + break;
>>> + default:
>>> + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_POWER
>>> +#define I2C_PMIC 0
>>> +int power_init_board(void)
>>> +{
>>> + struct pmic *p;
>>> + int ret;
>>> + unsigned int reg;
>>> +
>>> + ret = power_pfuze100_init(I2C_PMIC);
>>> + if (ret)
>>> + return -ENODEV;
>>> +
>>> + p = pmic_get("PFUZE100");
>>> + ret = pmic_probe(p);
>>> + if (ret)
>>> + return -ENODEV;
>>> +
>>> + pmic_reg_read(p, PFUZE100_DEVICEID, ®);
>>> + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
>>> +
>>> + pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
>>> + if ((reg & 0x3f) != 0x18) {
>>> + reg &= ~0x3f;
>>> + reg |= 0x18;
>>> + pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
>>> + }
>>> +
>>> + ret = pfuze_mode_init(p, APS_PFM);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +void spl_board_init(void)
>>> +{
>>> + enable_tzc380();
>>
>> Just for my understanding: is this board specific ? Enabling the
>> TrustZone controller looks to me more general, but I am maybe wrong. Can
>> you better explain me this ? Thanks !
>
> If want to use TZC380 on i.MX, TZC380 needs to be enabled
> before DDR initialization. So I put it in spl_board_init.
>
> TZC380 enablement is not a must for all boards.
>
> We will enable TEE on i.MX8MQ EVK board, so need to enable TZC380.
>
> Thanks,
> Peng
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support
2017-12-07 9:13 ` Peng Fan
2017-12-07 9:27 ` Stefano Babic
@ 2017-12-07 9:28 ` Stefano Babic
1 sibling, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-07 9:28 UTC (permalink / raw)
To: u-boot
Hi Peng,
On 07/12/2017 10:13, Peng Fan wrote:
> Hi Stefano,
>> Just for my understanding: is this board specific ? Enabling the
>> TrustZone controller looks to me more general, but I am maybe wrong. Can
>> you better explain me this ? Thanks !
>
> If want to use TZC380 on i.MX, TZC380 needs to be enabled
> before DDR initialization. So I put it in spl_board_init.
>
> TZC380 enablement is not a must for all boards.
>
> We will enable TEE on i.MX8MQ EVK board, so need to enable TZC380.
ok, got it, thanks for explanation.
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support
2017-12-07 9:27 ` Stefano Babic
@ 2017-12-07 9:59 ` Peng Fan
0 siblings, 0 replies; 65+ messages in thread
From: Peng Fan @ 2017-12-07 9:59 UTC (permalink / raw)
To: u-boot
Hi Stefano,
> >>> +
> >>> +DECLARE_GLOBAL_DATA_PTR;
> >>> +
> >>> +__weak void ddr_init(void)
> >>> +{
> >>> +};
> >>> +
> >>
> >> This weak could be dropped, it was surely for test purpose :-)
> >
> > I understand patch 23/23 about the ddr script, it is hard to be accepted.
> > So I add a weak function here to avoid build failure if other 22
> > patches could be accepted. It may take long time to convert the ddr
> > script to structure based.
>
> Ok, understand.
>
> >
> > So would you like to me to drop it and keep 23/23 in V3, or keep the
> > weak ddr_init and drop 23/23 in V3?
>
> Thing is that this patch is dead code without DDR setup. I am ready to merge
> reviewed patch, even if they add MX8M and there is not yet any board using -
> theoretically, this is also dead code and I could not. But this simplifies the
> development and you can reduce the number of patches to be posted next
> time.
Thanks.
But merging a board that is known to be broken due to a missing part, it is
> nonsense. Board will be merged when we have a suitable way to set the DDR
> controller.
Ok. Understand.
Thanks,
Peng.
>
> Regards,
> Stefano
>
> >
> >>
> >>> +void spl_dram_init(void)
> >>> +{
> >>> + /* ddr init */
> >>> + ddr_init();
> >>> +}
> >>> +
> >>> +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> PAD_CTL_PUE)
> >>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) struct i2c_pads_info
> >>> +i2c_pad_info1 = {
> >>> + .scl = {
> >>> + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
> >>> + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
> >>> + .gp = IMX_GPIO_NR(5, 14),
> >>> + },
> >>> + .sda = {
> >>> + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
> >>> + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
> >>> + .gp = IMX_GPIO_NR(5, 15),
> >>> + },
> >>> +};
> >>> +
> >>> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
> >>> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) #define
> USDHC2_PWR_GPIO
> >>> +IMX_GPIO_NR(2, 19)
> >>> +
> >>> +int board_mmc_getcd(struct mmc *mmc) {
> >>> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> >>> + int ret = 0;
> >>> +
> >>> + switch (cfg->esdhc_base) {
> >>> + case USDHC1_BASE_ADDR:
> >>> + ret = 1;
> >>> + break;
> >>> + case USDHC2_BASE_ADDR:
> >>> + ret = !gpio_get_value(USDHC2_CD_GPIO);
> >>> + return ret;
> >>> + }
> >>> +
> >>> + return 1;
> >>> +}
> >>> +
> >>> +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
> PAD_CTL_PUE | \
> >>> + PAD_CTL_FSEL2)
> >>> +
> >>> +static iomux_v3_cfg_t const usdhc1_pads[] = {
> >>> + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 |
> MUX_PAD_CTRL(NO_PAD_CTRL), };
> >>> +
> >>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> >>> + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 |
> MUX_PAD_CTRL(NO_PAD_CTRL),
> >>> + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 |
> MUX_PAD_CTRL(NO_PAD_CTRL), };
> >>> +
> >>> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> >>> + {USDHC1_BASE_ADDR, 0, 8},
> >>> + {USDHC2_BASE_ADDR, 0, 4},
> >>> +};
> >>> +
> >>> +int board_mmc_init(bd_t *bis)
> >>> +{
> >>> + int i, ret;
> >>> + /*
> >>> + * According to the board_mmc_init() the following map is done:
> >>> + * (U-Boot device node) (Physical Port)
> >>> + * mmc0 USDHC1
> >>> + * mmc1 USDHC2
> >>> + */
> >>> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> >>> + switch (i) {
> >>> + case 0:
> >>> + init_clk_usdhc(0);
> >>> + usdhc_cfg[0].sdhc_clk =
> mxc_get_clock(USDHC1_CLK_ROOT);
> >>> + imx_iomux_v3_setup_multiple_pads(
> >>> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> >>> + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
> >>> + gpio_direction_output(USDHC1_PWR_GPIO, 0);
> >>> + udelay(500);
> >>> + gpio_direction_output(USDHC1_PWR_GPIO, 1);
> >>> + break;
> >>> + case 1:
> >>> + init_clk_usdhc(1);
> >>> + usdhc_cfg[1].sdhc_clk =
> mxc_get_clock(USDHC2_CLK_ROOT);
> >>> + imx_iomux_v3_setup_multiple_pads(
> >>> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> >>> + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
> >>> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
> >>> + udelay(500);
> >>> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
> >>> + break;
> >>> + default:
> >>> + printf("Warning: you configured more USDHC
> controllers(%d) than supported by the board\n", i + 1);
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> >>> + if (ret)
> >>> + return ret;
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +#ifdef CONFIG_POWER
> >>> +#define I2C_PMIC 0
> >>> +int power_init_board(void)
> >>> +{
> >>> + struct pmic *p;
> >>> + int ret;
> >>> + unsigned int reg;
> >>> +
> >>> + ret = power_pfuze100_init(I2C_PMIC);
> >>> + if (ret)
> >>> + return -ENODEV;
> >>> +
> >>> + p = pmic_get("PFUZE100");
> >>> + ret = pmic_probe(p);
> >>> + if (ret)
> >>> + return -ENODEV;
> >>> +
> >>> + pmic_reg_read(p, PFUZE100_DEVICEID, ®);
> >>> + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
> >>> +
> >>> + pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
> >>> + if ((reg & 0x3f) != 0x18) {
> >>> + reg &= ~0x3f;
> >>> + reg |= 0x18;
> >>> + pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
> >>> + }
> >>> +
> >>> + ret = pfuze_mode_init(p, APS_PFM);
> >>> + if (ret < 0)
> >>> + return ret;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +#endif
> >>> +
> >>> +void spl_board_init(void)
> >>> +{
> >>> + enable_tzc380();
> >>
> >> Just for my understanding: is this board specific ? Enabling the
> >> TrustZone controller looks to me more general, but I am maybe wrong.
> >> Can you better explain me this ? Thanks !
> >
> > If want to use TZC380 on i.MX, TZC380 needs to be enabled before DDR
> > initialization. So I put it in spl_board_init.
> >
> > TZC380 enablement is not a must for all boards.
> >
> > We will enable TEE on i.MX8MQ EVK board, so need to enable TZC380.
> >
> > Thanks,
> > Peng
> >
>
>
> --
> ============================================================
> =========
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> ============================================================
> =========
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 01/23] imx: add i.MX8M into Kconfig
2017-12-04 4:31 ` [U-Boot] [PATCH V2 01/23] imx: add i.MX8M into Kconfig Peng Fan
@ 2017-12-16 17:16 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:16 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add i.MX8M into Kconfig, create a new folder mx8m
> dedicated for i.MX8M.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/Kconfig | 8 ++++++++
> arch/arm/Makefile | 4 ++--
> arch/arm/mach-imx/mx8m/Kconfig | 10 ++++++++++
> 3 files changed, 20 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/mach-imx/mx8m/Kconfig
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index ca386decfe..3b2adbc1f2 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -604,6 +604,12 @@ config ARCH_MESON
> targeted at media players and tablet computers. We currently
> support the S905 (GXBaby) 64-bit SoC.
>
> +config ARCH_MX8M
> + bool "NXP i.MX8M platform"
> + select ARM64
> + select DM
> + select SUPPORT_SPL
> +
> config ARCH_MX25
> bool "NXP MX25"
> select CPU_ARM926EJS
> @@ -1177,6 +1183,8 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
>
> source "arch/arm/mach-imx/mx2/Kconfig"
>
> +source "arch/arm/mach-imx/mx8m/Kconfig"
Please keep in alphabetical order.
Other than this:
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 02/23] imx: mx8m: add register definition header file
2017-12-04 4:31 ` [U-Boot] [PATCH V2 02/23] imx: mx8m: add register definition header file Peng Fan
@ 2017-12-16 17:17 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:17 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add register definition header file for i.MX8M
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 03/23] imx: mx8m: add pin header file
2017-12-04 4:31 ` [U-Boot] [PATCH V2 03/23] imx: mx8m: add pin " Peng Fan
@ 2017-12-16 17:18 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:18 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add pin header file for i.MX8M
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 04/23] imx: mx8m: add clock driver
2017-12-04 4:31 ` [U-Boot] [PATCH V2 04/23] imx: mx8m: add clock driver Peng Fan
@ 2017-12-16 17:33 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:33 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> + switch (frac_pll) {
> + case ARM_PLL_CLK:
> + pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
> + pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
> + pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
> + pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
> + break;
> + default:
> + printf("Not supported\n");
Please improve the error message. "Not supported" is simply too vague.
Also, you use this same error message in several parts of the driver.
Please distinguish between them so that it can make it easier for
people debugging issues to know where exactly the error message comes
from.
> +
> +static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
> +{
> + u32 pll_cfg0, pll_cfg1, pll_cfg2;
> + u32 pll_refclk_sel, pll_refclk;
> + u32 divr1, divr2, divf1, divf2, divq, div;
> + u32 sse;
> + u32 pll_clke;
> + u32 pllout_div_shift, pllout_div_mask, pllout_div;
> + u32 pllout;
> +
> + switch (sscg_pll) {
> + case SYSTEM_PLL1_800M_CLK:
> + case SYSTEM_PLL1_400M_CLK:
> + case SYSTEM_PLL1_266M_CLK:
> + case SYSTEM_PLL1_200M_CLK:
> + case SYSTEM_PLL1_160M_CLK:
> + case SYSTEM_PLL1_133M_CLK:
> + case SYSTEM_PLL1_100M_CLK:
> + case SYSTEM_PLL1_80M_CLK:
> + case SYSTEM_PLL1_40M_CLK:
> + pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
> + pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
> + pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
> + pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
> + pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
> + break;
> + case SYSTEM_PLL2_1000M_CLK:
> + case SYSTEM_PLL2_500M_CLK:
> + case SYSTEM_PLL2_333M_CLK:
> + case SYSTEM_PLL2_250M_CLK:
> + case SYSTEM_PLL2_200M_CLK:
> + case SYSTEM_PLL2_166M_CLK:
> + case SYSTEM_PLL2_125M_CLK:
> + case SYSTEM_PLL2_100M_CLK:
> + case SYSTEM_PLL2_50M_CLK:
> + pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
> + pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
> + pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
> + pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
> + pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
> + break;
> + case SYSTEM_PLL3_CLK:
> + pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
> + pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
> + pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
> + pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
> + pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
> + break;
> + case DRAM_PLL1_CLK:
> + pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
> + pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
> + pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
> + pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
> + pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
> + break;
> + default:
> + printf("Not supported\n");
Ditto.
> + case SYSTEM_PLL2_50M_CLK:
> + case SYSTEM_PLL1_40M_CLK:
> + pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
> + div = 20;
> + break;
> + default:
> + printf("Not supported\n");
Ditto.
> +static u32 get_root_src_clk(enum clk_root_src root_src)
> +{
> + switch (root_src) {
> + case OSC_25M_CLK:
> + return 25000000u;
Is this 'u' in the end really needed? It doesn't seem so.
> +#ifdef CONFIG_MXC_OCOTP
> +void enable_ocotp_clk(unsigned char enable)
> +{
> + clock_enable(CCGR_OCOTP, !!enable);
Not a big fan of a function called clock_enabled() that can be used to
enable or disable a clock.
I prefer the kernel style: clock_enable() and clock_disable().
> +}
> +#endif
> +
> +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
> +{
> + /* 0 - 3 is valid i2c num */
> + if (i2c_num > 3)
> + return -EINVAL;
> +
> + clock_enable(CCGR_I2C1 + i2c_num, !!enable);
> +
> + return 0;
> +}
> +
> +unsigned int mxc_get_clock(enum clk_root_index clk)
> +{
> + u32 val;
> +
> + if (clk >= CLK_ROOT_MAX)
> + return 0;
> +
> + if (clk == MXC_ARM_CLK)
> + return get_root_clk(ARM_A53_CLK_ROOT);
> +
> + if (clk == MXC_IPG_CLK) {
> + clock_get_target_val(IPG_CLK_ROOT, &val);
> + val = val & 0x3;
> + return get_root_clk(AHB_CLK_ROOT) / (val + 1);
> + }
> +
> + return get_root_clk(clk);
> +}
> +
> +u32 imx_get_uartclk(void)
> +{
> + return mxc_get_clock(UART1_CLK_ROOT);
> +}
> +
> +void mxs_set_lcdclk(u32 base_addr, u32 freq)
> +{
> + /*
> + * LCDIF_PIXEL_CLK: select 800MHz root clock,
> + * select pre divider 8, output is 100 MHz
> + */
> + clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(4) |
> + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
> +}
> +
> +void init_wdog_clk(void)
> +{
> + clock_enable(CCGR_WDOG1, 0);
> + clock_enable(CCGR_WDOG2, 0);
> + clock_enable(CCGR_WDOG3, 0);
> + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(0));
> + clock_enable(CCGR_WDOG1, 1);
> + clock_enable(CCGR_WDOG2, 1);
> + clock_enable(CCGR_WDOG3, 1);
> +}
> +
> +void init_usb_clk(void)
> +{
> + if (!is_usb_boot()) {
> + clock_enable(CCGR_USB_CTRL1, 0);
> + clock_enable(CCGR_USB_CTRL2, 0);
> + clock_enable(CCGR_USB_PHY1, 0);
> + clock_enable(CCGR_USB_PHY2, 0);
> + /* 500M */
500 MHz
> + clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1));
> + /* 100M */
100 MHz
> + clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
> + CLK_ROOT_SOURCE_SEL(1));
> + /* 100M */
100 MHz again?
> +#ifdef CONFIG_SPL_BUILD
> +void dram_pll_init(void)
> +{
> + struct src *src = (struct src *)SRC_BASE_ADDR;
> + void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
> + u32 pwdn_mask = 0;
> + u32 pll_clke = 0;
> + u32 bypass1 = 0;
> + u32 bypass2 = 0;
> +
> + setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
> + setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
> +
> + pwdn_mask = SSCG_PLL_PD_MASK;
> + pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
> + bypass1 = SSCG_PLL_BYPASS1_MASK;
> + bypass2 = SSCG_PLL_BYPASS2_MASK;
> +
> + /* Enable DDR1 and DDR2 domain */
> + writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
> + writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
> +
> + /* Clear power down bit */
> + clrbits_le32(pll_control_reg, pwdn_mask);
> + /* Eanble ARM_PLL/SYS_PLL */
> + setbits_le32(pll_control_reg, pll_clke);
> +
> + /* Clear bypass */
> + clrbits_le32(pll_control_reg, bypass1);
> + __udelay(100);
> + clrbits_le32(pll_control_reg, bypass2);
> + /* Wait until lock */
> + while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
> + ;
No timeout? If bad things happens we can get stuck here forever.
> +}
> +
> +int frac_pll_init(u32 pll, enum frac_pll_out_val val)
> +{
> + void __iomem *pll_cfg0, __iomem *pll_cfg1;
> + u32 val_cfg0, val_cfg1;
> +
> + switch (pll) {
> + case ANATOP_ARM_PLL:
> + pll_cfg0 = &ana_pll->arm_pll_cfg0;
> + pll_cfg1 = &ana_pll->arm_pll_cfg1;
> +
> + if (val == FRAC_PLL_OUT_1000M)
> + val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
> + else
> + val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
> + val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
> + FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
> + FRAC_PLL_REFCLK_DIV_VAL(4) |
> + FRAC_PLL_OUTPUT_DIV_VAL(0);
> + break;
> + default:
> + return -1;
-EINVAL, please.
> + }
> +
> + /* bypass the clock */
> + setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
> + /* Set the value */
> + writel(val_cfg1, pll_cfg1);
> + writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
> + val_cfg0 = readl(pll_cfg0);
> + /* unbypass the clock */
> + clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
> + while (!(readl(pll_cfg0) & FRAC_PLL_LOCK_MASK))
> + ;
Same here.
> + case ANATOP_SYSTEM_PLL3:
> + pll_cfg0 = &ana_pll->sys_pll3_cfg0;
> + pll_cfg1 = &ana_pll->sys_pll3_cfg1;
> + pll_cfg2 = &ana_pll->sys_pll3_cfg2;
> + /* 800MHz */
> + val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
> + SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
> + val_cfg1 = 0;
> + val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
> + SSCG_PLL_REFCLK_SEL_OSC_25M;
> + break;
> + default:
> + return -1;
-EINVAL
> + }
> +
> + /*bypass*/
> + setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
> + /* set value */
> + writel(val_cfg2, pll_cfg2);
> + writel(val_cfg1, pll_cfg1);
> + /*unbypass1 and wait 70us */
> + writel(val_cfg0 | bypass2_mask, pll_cfg1);
> +
> + __udelay(70);
> +
> + /* unbypass2 and wait lock */
> + writel(val_cfg0, pll_cfg1);
> + while (!(readl(pll_cfg0) & SSCG_PLL_LOCK_MASK))
> + ;
Timeout please.
> +#endif
> +
> +/*
> + * Dump some clockes.
Typo: clocks
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 05/23] imx: add sip function
2017-12-04 4:31 ` [U-Boot] [PATCH V2 05/23] imx: add sip function Peng Fan
@ 2017-12-16 17:35 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:35 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add SiP (Silicon Provider) services function to issue
> SMC call to Arm Trusted Firmware.
>
> More SiP information could be found in
> https://github.com/ARM-software/arm-trusted-firmware/blob/master/
> docs/arm-sip-service.rst
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 06/23] imx: boot_mode: add USB_BOOT entry
2017-12-04 4:31 ` [U-Boot] [PATCH V2 06/23] imx: boot_mode: add USB_BOOT entry Peng Fan
@ 2017-12-16 17:35 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:35 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add USB_BOOT entry.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h
2017-12-04 4:31 ` [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h Peng Fan
@ 2017-12-16 17:35 ` Fabio Estevam
2017-12-17 10:32 ` Stefano Babic
1 sibling, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:35 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Include dm/ofnode.h.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M Peng Fan
2017-12-07 8:40 ` Stefano Babic
@ 2017-12-16 17:36 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:36 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Update get_reset_cause to reflect i.MX8M
> Compile out get_ahb_clk and set_chipselect_size for i.MX8M
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 09/23] imx: spl: implement spl_boot_device for i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 09/23] imx: spl: implement spl_boot_device for i.MX8M Peng Fan
@ 2017-12-16 17:36 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:36 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Implement spl_boot_device for i.MX8M.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 10/23] imx: add i.MX8MQ SoC Revision and is_mx8m helper
2017-12-04 4:31 ` [U-Boot] [PATCH V2 10/23] imx: add i.MX8MQ SoC Revision and is_mx8m helper Peng Fan
@ 2017-12-16 17:37 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:37 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add i.MX8MQ SoC Revision
> Add is_mx8m helper
> The 7ULP is a dummy number, so use 0xEx.
Typo: 0xE1
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 11/23] imx: add pad settings bit definition for i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 11/23] imx: add pad settings bit definition for i.MX8M Peng Fan
@ 2017-12-16 17:38 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:38 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add pad settings bit definition for i.MX8M.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 13/23] imx: makefile: compile files for i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 13/23] imx: makefile: compile files for i.MX8M Peng Fan
@ 2017-12-16 17:39 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:39 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Compile files for i.MX8M
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support Peng Fan
2017-12-07 8:41 ` Stefano Babic
@ 2017-12-16 17:40 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:40 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> i.MX8M OCOTP follow same flow as i.MX6Q, but it has 64 banks
> and each bank 4 words.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M Peng Fan
2017-12-07 8:41 ` Stefano Babic
@ 2017-12-16 17:40 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:40 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Support i.MX8M in fsl esdhc driver.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M Peng Fan
2017-12-07 8:41 ` Stefano Babic
@ 2017-12-16 17:41 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:41 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Include i.MX8M in lcdif register layout map.
> Also included i.MX7ULP in this patch, since share same with i.MX8M.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 17/23] gpio: mxc: add i.MX8M support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 17/23] gpio: mxc: add i.MX8M support Peng Fan
@ 2017-12-16 17:41 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:41 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add i.MX8M GPIO support.
> There are 4 GPIO banks on i.MX8M.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M
2017-12-04 4:31 ` [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M Peng Fan
[not found] ` <CANr=Z=Z6ekzYT3+YG7nXWKedQc_3tS42_BAbkqnP8A8Qpij5Pg@mail.gmail.com>
2017-12-07 8:42 ` Stefano Babic
@ 2017-12-16 17:41 ` Fabio Estevam
2 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:41 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> The MIB RAM and FIFO receive start register does not exist on
> i.MX8M. Accessing these register will cause system hang.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support Peng Fan
2017-12-05 20:37 ` Joe Hershberger
2017-12-07 8:42 ` Stefano Babic
@ 2017-12-16 17:43 ` Fabio Estevam
2 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:43 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> When building for 64bits system, we get some warnings about type
> cast between pointer and integer. This patch eliminates the warnings
> by using ulong/long type which is 32bits on 32bits system or 64bits on
> 64bits system.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
Is this patch from Ye Li or from you?
If it comes from Ye Li then his name should appear in the Author field.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL
2017-12-04 4:31 ` [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL Peng Fan
2017-12-07 8:43 ` Stefano Babic
@ 2017-12-16 17:43 ` Fabio Estevam
2017-12-17 10:33 ` Stefano Babic
2 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:43 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Allow the dm driver be omitted by SPL.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 21/23] imx: imx8mq: add dtsi file
2017-12-04 4:31 ` [U-Boot] [PATCH V2 21/23] imx: imx8mq: add dtsi file Peng Fan
@ 2017-12-16 17:44 ` Fabio Estevam
0 siblings, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:44 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add dtsi file for i.MX8MQ.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support
2017-12-04 4:31 ` [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support Peng Fan
2017-12-07 8:52 ` Stefano Babic
@ 2017-12-16 17:51 ` Fabio Estevam
1 sibling, 0 replies; 65+ messages in thread
From: Fabio Estevam @ 2017-12-16 17:51 UTC (permalink / raw)
To: u-boot
On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan <peng.fan@nxp.com> wrote:
> Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
> firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
> DRAM.
>
> The boot log:
> "
> U-Boot SPL 2017.11-00062-gd4c7c3ebb3-dirty (Dec 01 2017 - 14:49:31)
> PMIC: PFUZE100 ID=0x10
> check ddr4_pmu_train_imem code
> check ddr4_pmu_train_imem code pass
> check ddr4_pmu_train_dmem code
> check ddr4_pmu_train_dmem code pass
> PLL bypass to 100MTS setting done
> Training PASS
> PLL bypass to 400MTS setting done
> Training PASS
> Training PASS
> check ddr4_pmu_train_imem code
> check ddr4_pmu_train_imem code pass
> check ddr4_pmu_train_dmem code
> check ddr4_pmu_train_dmem code pass
> Training PASS
Please turn these messages into debug level. They are too noisy to
appear on every boot.
> diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README
> new file mode 100644
> index 0000000000..6be5f51a22
> --- /dev/null
> +++ b/board/freescale/mx8mq_evk/README
> @@ -0,0 +1,38 @@
> +U-Boot for the NXP i.MX8MQ EVK board
> +
> +Quick Start
> +====================
> +- Build the ARM Trusted firmware binary
> +- Build U-Boot
> +- Generate flash.bin using imx-mkimage
> +- Boot
> +
> +Build the ARM Trusted firmware
> +====================
> +$ make PLAT=imx8mq bl31
> +
> +Build U-Boot
> +====================
> +$ export ARCH=arm64
> +$ export CROSS_COMPILE=aarch64-poky-linux-
> +$ make mx8mq_evk_defconfig
> +$ make
> +
> +Generate flash.bin using imx-mkimage
What is imx-mkimage? Why do you need a special tool and can't use the
official mkimage one?
> +====================
> +Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to
> + imx-mkimage/iMX8M
> +Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin
> + lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to
> + imx-mkimage/iMX8M
> +If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M
> +
> +make SOC=iMX8M flash_spl_uboot or make SOC=iMX8M flash_hdmi_spl_uboot to
> +generate flash.bin.
> +
> +Burn the flash.bin to MicroSD card offset 33KB
> +$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
> +
> +Boot
> +====================
> +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
Sorry, but this README simply does not work.
All these required firmwares and imx-mkimage are really confusing.
I am not able to get a bootable image by reading this README file.
Please improve the README so that a user can really make a bootable SD
card by following the described step by step sequence.
That's what the README is for :-)
Thanks
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h
2017-12-04 4:31 ` [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h Peng Fan
2017-12-16 17:35 ` Fabio Estevam
@ 2017-12-17 10:32 ` Stefano Babic
1 sibling, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-17 10:32 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> Include dm/ofnode.h.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> include/power/pmic.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/power/pmic.h b/include/power/pmic.h
> index 4b34316427..f2fe537fb7 100644
> --- a/include/power/pmic.h
> +++ b/include/power/pmic.h
> @@ -11,6 +11,7 @@
> #ifndef __CORE_PMIC_H_
> #define __CORE_PMIC_H_
>
> +#include <dm/ofnode.h>
> #include <i2c.h>
> #include <linux/list.h>
> #include <power/power_chrg.h>
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
* [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL
2017-12-04 4:31 ` [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL Peng Fan
2017-12-07 8:43 ` Stefano Babic
2017-12-16 17:43 ` Fabio Estevam
@ 2017-12-17 10:33 ` Stefano Babic
2 siblings, 0 replies; 65+ messages in thread
From: Stefano Babic @ 2017-12-17 10:33 UTC (permalink / raw)
To: u-boot
On 04/12/2017 05:31, Peng Fan wrote:
> Allow the dm driver be omitted by SPL.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> drivers/power/pmic/Makefile | 4 ++--
> drivers/power/regulator/Makefile | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index f7bdfa5609..4abdaf6668 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -5,10 +5,10 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC) += pmic-uclass.o
> obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
> obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
> -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
> obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
> obj-$(CONFIG_PMIC_ACT8846) += act8846.o
> diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
> index 6c149a9263..9809f7c845 100644
> --- a/drivers/power/regulator/Makefile
> +++ b/drivers/power/regulator/Makefile
> @@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
> obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
> obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
> obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
> -obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
> obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
> obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 65+ messages in thread
end of thread, other threads:[~2017-12-17 10:33 UTC | newest]
Thread overview: 65+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-04 4:31 [U-Boot] [PATCH V2 00/23] imx: add i.MX8M support and i.MX8MQ EVK Peng Fan
2017-12-04 4:31 ` [U-Boot] [PATCH V2 01/23] imx: add i.MX8M into Kconfig Peng Fan
2017-12-16 17:16 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 02/23] imx: mx8m: add register definition header file Peng Fan
2017-12-16 17:17 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 03/23] imx: mx8m: add pin " Peng Fan
2017-12-16 17:18 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 04/23] imx: mx8m: add clock driver Peng Fan
2017-12-16 17:33 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 05/23] imx: add sip function Peng Fan
2017-12-16 17:35 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 06/23] imx: boot_mode: add USB_BOOT entry Peng Fan
2017-12-16 17:35 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 07/23] power: pmic.h: include dm/ofnode.h Peng Fan
2017-12-16 17:35 ` Fabio Estevam
2017-12-17 10:32 ` Stefano Babic
2017-12-04 4:31 ` [U-Boot] [PATCH V2 08/23] imx: cpu: update cpu file to support i.MX8M Peng Fan
2017-12-07 8:40 ` Stefano Babic
2017-12-16 17:36 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 09/23] imx: spl: implement spl_boot_device for i.MX8M Peng Fan
2017-12-16 17:36 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 10/23] imx: add i.MX8MQ SoC Revision and is_mx8m helper Peng Fan
2017-12-16 17:37 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 11/23] imx: add pad settings bit definition for i.MX8M Peng Fan
2017-12-16 17:38 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 12/23] imx: mx8m: add soc related settings and files Peng Fan
2017-12-07 8:39 ` Stefano Babic
2017-12-07 9:06 ` Peng Fan
2017-12-04 4:31 ` [U-Boot] [PATCH V2 13/23] imx: makefile: compile files for i.MX8M Peng Fan
2017-12-16 17:39 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 14/23] misc: ocotp: add i.MX8M support Peng Fan
2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:40 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 15/23] mmc: fsl_esdhc: support i.MX8M Peng Fan
2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:40 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 16/23] imx: lcdif: include i.MX8M Peng Fan
2017-12-07 8:41 ` Stefano Babic
2017-12-16 17:41 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 17/23] gpio: mxc: add i.MX8M support Peng Fan
2017-12-16 17:41 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 18/23] net: fec: do not access reserved register for i.MX8M Peng Fan
[not found] ` <CANr=Z=Z6ekzYT3+YG7nXWKedQc_3tS42_BAbkqnP8A8Qpij5Pg@mail.gmail.com>
2017-12-05 20:36 ` Joe Hershberger
2017-12-07 8:42 ` Stefano Babic
2017-12-16 17:41 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 19/23] net: fec: fix build warnings for 64bits support Peng Fan
2017-12-05 20:37 ` Joe Hershberger
2017-12-07 8:42 ` Stefano Babic
2017-12-16 17:43 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 20/23] power: pmic/regulator allow dm be omitted by SPL Peng Fan
2017-12-07 8:43 ` Stefano Babic
2017-12-16 17:43 ` Fabio Estevam
2017-12-17 10:33 ` Stefano Babic
2017-12-04 4:31 ` [U-Boot] [PATCH V2 21/23] imx: imx8mq: add dtsi file Peng Fan
2017-12-16 17:44 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 22/23] imx: add i.MX8MQ EVK support Peng Fan
2017-12-07 8:52 ` Stefano Babic
2017-12-07 9:13 ` Peng Fan
2017-12-07 9:27 ` Stefano Babic
2017-12-07 9:59 ` Peng Fan
2017-12-07 9:28 ` Stefano Babic
2017-12-16 17:51 ` Fabio Estevam
2017-12-04 4:31 ` [U-Boot] [PATCH V2 23/23] Add DDR settings Peng Fan
2017-12-04 17:48 ` Dr. Philipp Tomsich
2017-12-07 7:31 ` Peng Fan
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