* [GIT PULL] gvt-fixes for 4.15-rc3
@ 2017-12-06 7:51 Zhenyu Wang
2017-12-07 12:08 ` Joonas Lahtinen
2017-12-08 9:32 ` Daniel Vetter
0 siblings, 2 replies; 3+ messages in thread
From: Zhenyu Wang @ 2017-12-06 7:51 UTC (permalink / raw)
To: Joonas Lahtinen, Jani Nikula, Vivi, Rodrigo
Cc: intel-gfx, Yuan, Hang, Xu, Terrence, Lv, Zhiyuan, intel-gvt-dev
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Hi,
Here's gvt-fixes for 4.15-rc3 with several fixes backported.
thanks
--
The following changes since commit b721b65af4eb46df6a1d9e34b14003225e403565:
drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition (2017-11-28 17:24:30 +0800)
are available in the Git repository at:
https://github.com/intel/gvt-linux.git tags/gvt-fixes-2017-12-06
for you to fetch changes up to 11474e9091cf2002e948647fd9f63a7f027e488a:
drm/i915/gvt: set max priority for gvt context (2017-12-06 11:38:21 +0800)
----------------------------------------------------------------
gvt-fixes-2017-12-06
- Fix invalid hw reg read value for vGPU (Xiong)
- Fix qemu warning on PCI ROM bar missing (Changbin)
- Workaround preemption regression (Zhenyu)
----------------------------------------------------------------
Changbin Du (1):
drm/i915/gvt: Emulate PCI expansion ROM base address register
Xiong Zhang (1):
drm/i915/gvt: Limit read hw reg to active vgpu
Zhenyu Wang (2):
drm/i915/gvt: Don't mark vgpu context as inactive when preempted
drm/i915/gvt: set max priority for gvt context
Zhi Wang (1):
drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
drivers/gpu/drm/i915/gvt/cfg_space.c | 21 ++++++++++++++++
drivers/gpu/drm/i915/gvt/handlers.c | 47 ++++++++++++++++++++++++++++--------
drivers/gpu/drm/i915/gvt/mmio.h | 2 ++
drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++++++++++++++++-
4 files changed, 81 insertions(+), 11 deletions(-)
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [GIT PULL] gvt-fixes for 4.15-rc3
2017-12-06 7:51 [GIT PULL] gvt-fixes for 4.15-rc3 Zhenyu Wang
@ 2017-12-07 12:08 ` Joonas Lahtinen
2017-12-08 9:32 ` Daniel Vetter
1 sibling, 0 replies; 3+ messages in thread
From: Joonas Lahtinen @ 2017-12-07 12:08 UTC (permalink / raw)
To: Zhenyu Wang, Jani Nikula, Vivi, Rodrigo
Cc: intel-gfx, Yuan, Hang, Xu, Terrence, Lv, Zhiyuan, intel-gvt-dev
Hi,
Pulled these, I will give it a final go with CI and send the pull forward. Thanks.
Regards, Joonas
On Wed, 2017-12-06 at 15:51 +0800, Zhenyu Wang wrote:
> Hi,
>
> Here's gvt-fixes for 4.15-rc3 with several fixes backported.
>
> thanks
> --
> The following changes since commit b721b65af4eb46df6a1d9e34b14003225e403565:
>
> drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition (2017-11-28 17:24:30 +0800)
>
> are available in the Git repository at:
>
> https://github.com/intel/gvt-linux.git tags/gvt-fixes-2017-12-06
>
> for you to fetch changes up to 11474e9091cf2002e948647fd9f63a7f027e488a:
>
> drm/i915/gvt: set max priority for gvt context (2017-12-06 11:38:21 +0800)
>
> ----------------------------------------------------------------
> gvt-fixes-2017-12-06
>
> - Fix invalid hw reg read value for vGPU (Xiong)
> - Fix qemu warning on PCI ROM bar missing (Changbin)
> - Workaround preemption regression (Zhenyu)
>
> ----------------------------------------------------------------
> Changbin Du (1):
> drm/i915/gvt: Emulate PCI expansion ROM base address register
>
> Xiong Zhang (1):
> drm/i915/gvt: Limit read hw reg to active vgpu
>
> Zhenyu Wang (2):
> drm/i915/gvt: Don't mark vgpu context as inactive when preempted
> drm/i915/gvt: set max priority for gvt context
>
> Zhi Wang (1):
> drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
>
> drivers/gpu/drm/i915/gvt/cfg_space.c | 21 ++++++++++++++++
> drivers/gpu/drm/i915/gvt/handlers.c | 47 ++++++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/gvt/mmio.h | 2 ++
> drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++++++++++++++++-
> 4 files changed, 81 insertions(+), 11 deletions(-)
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [GIT PULL] gvt-fixes for 4.15-rc3
2017-12-06 7:51 [GIT PULL] gvt-fixes for 4.15-rc3 Zhenyu Wang
2017-12-07 12:08 ` Joonas Lahtinen
@ 2017-12-08 9:32 ` Daniel Vetter
1 sibling, 0 replies; 3+ messages in thread
From: Daniel Vetter @ 2017-12-08 9:32 UTC (permalink / raw)
To: Zhenyu Wang
Cc: Jani Nikula, intel-gfx, Yuan, Hang, Xu, Terrence, Lv, Zhiyuan,
Vivi, Rodrigo, intel-gvt-dev
On Wed, Dec 06, 2017 at 03:51:05PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's gvt-fixes for 4.15-rc3 with several fixes backported.
>
> thanks
> --
> The following changes since commit b721b65af4eb46df6a1d9e34b14003225e403565:
>
> drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition (2017-11-28 17:24:30 +0800)
>
> are available in the Git repository at:
>
> https://github.com/intel/gvt-linux.git tags/gvt-fixes-2017-12-06
>
> for you to fetch changes up to 11474e9091cf2002e948647fd9f63a7f027e488a:
>
> drm/i915/gvt: set max priority for gvt context (2017-12-06 11:38:21 +0800)
Somehow patchwork is not picking up your pull requests, which means the
Link: tags we auto-add go nowhere. Can you pls check your pull request
genration script and maybe compare with what we have in our
maintainer-tools? That one works.
-Daniel
>
> ----------------------------------------------------------------
> gvt-fixes-2017-12-06
>
> - Fix invalid hw reg read value for vGPU (Xiong)
> - Fix qemu warning on PCI ROM bar missing (Changbin)
> - Workaround preemption regression (Zhenyu)
>
> ----------------------------------------------------------------
> Changbin Du (1):
> drm/i915/gvt: Emulate PCI expansion ROM base address register
>
> Xiong Zhang (1):
> drm/i915/gvt: Limit read hw reg to active vgpu
>
> Zhenyu Wang (2):
> drm/i915/gvt: Don't mark vgpu context as inactive when preempted
> drm/i915/gvt: set max priority for gvt context
>
> Zhi Wang (1):
> drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
>
> drivers/gpu/drm/i915/gvt/cfg_space.c | 21 ++++++++++++++++
> drivers/gpu/drm/i915/gvt/handlers.c | 47 ++++++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/gvt/mmio.h | 2 ++
> drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++++++++++++++++-
> 4 files changed, 81 insertions(+), 11 deletions(-)
>
> --
> Open Source Technology Center, Intel ltd.
>
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-12-06 7:51 [GIT PULL] gvt-fixes for 4.15-rc3 Zhenyu Wang
2017-12-07 12:08 ` Joonas Lahtinen
2017-12-08 9:32 ` Daniel Vetter
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