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From: Vinod Koul <vinod.koul@intel.com>
To: "Patel, Chintan M" <chintan.m.patel@intel.com>
Cc: "Periyasamy, SriramX" <sriramx.periyasamy@intel.com>,
	ALSA ML <alsa-devel@alsa-project.org>,
	Mark Brown <broonie@kernel.org>, Takashi Iwai <tiwai@suse.de>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
	Patches Audio <patches.audio@intel.com>,
	Liam Girdwood <liam.r.girdwood@linux.intel.com>,
	"Prusty, Subhransu S" <subhransu.s.prusty@intel.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Subject: Re: [alsa-devel] [PATCH v5 5/6] ASoC: Intel: Skylake: Make DSP replies	more human readable
Date: Wed, 13 Dec 2017 08:55:59 +0530	[thread overview]
Message-ID: <20171213032559.GH18649@localhost> (raw)
In-Reply-To: <074180B186AC2945B61C466FE6C478304ADE8101@ORSMSX103.amr.corp.intel.com>

On Tue, Dec 12, 2017 at 11:57:07PM +0530, Patel, Chintan M wrote:
> I would also suggest to make similar changes for FW error code, since it doesn't give any clue what does FW error code indicates.

First, Why are you top posting ?
Second, why are you not wrapping your replies ?

Please never top post on mailing list and wrap your replies.

On the actual question, sure a good suggestion but not relvant in this context.
Will check and see if we can do that.

-- 
~Vinod

WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vinod.koul@intel.com>
To: "Patel, Chintan M" <chintan.m.patel@intel.com>
Cc: "Periyasamy, SriramX" <sriramx.periyasamy@intel.com>,
	ALSA ML <alsa-devel@alsa-project.org>,
	Mark Brown <broonie@kernel.org>, Takashi Iwai <tiwai@suse.de>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
	Patches Audio <patches.audio@intel.com>,
	Liam Girdwood <liam.r.girdwood@linux.intel.com>,
	"Prusty, Subhransu S" <subhransu.s.prusty@intel.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Subject: Re: [alsa-devel] [PATCH v5 5/6] ASoC: Intel: Skylake: Make DSP replies        more human readable
Date: Wed, 13 Dec 2017 08:55:59 +0530	[thread overview]
Message-ID: <20171213032559.GH18649@localhost> (raw)
In-Reply-To: <074180B186AC2945B61C466FE6C478304ADE8101@ORSMSX103.amr.corp.intel.com>

On Tue, Dec 12, 2017 at 11:57:07PM +0530, Patel, Chintan M wrote:
> I would also suggest to make similar changes for FW error code, since it doesn't give any clue what does FW error code indicates.

First, Why are you top posting ?
Second, why are you not wrapping your replies ?

Please never top post on mailing list and wrap your replies.

On the actual question, sure a good suggestion but not relvant in this context.
Will check and see if we can do that.

-- 
~Vinod

  reply	other threads:[~2017-12-13  3:25 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-11  7:46 [alsa-devel] [PATCH v5 0/6] ASoC: Intel: Skylake: Add a clk driver to enable ssp clks early Sriram Periyasamy
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 1/6] ASoC: Intel: Skylake: Add ssp clock driver Sriram Periyasamy
2017-12-13 22:30   ` Stephen Boyd
2017-12-18  3:57     ` Subhransu S. Prusty
2017-12-18  5:01       ` Subhransu S. Prusty
2017-12-18 19:10         ` Stephen Boyd
2017-12-19  5:41           ` Subhransu S. Prusty
2017-12-19 19:17             ` Stephen Boyd
2017-12-20  3:33               ` Subhransu S. Prusty
2017-12-22  2:04                 ` Stephen Boyd
2017-12-22  4:52                   ` Subhransu S. Prusty
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 2/6] ASoC: Intel: Skylake: Add extended I2S config blob support in Clock driver Sriram Periyasamy
2018-01-26 12:54   ` Applied "ASoC: Intel: Skylake: Add extended I2S config blob support in Clock driver" to the asoc tree Mark Brown
2018-01-26 12:54     ` Mark Brown
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 3/6] ASoC: Intel: kbl: Enable mclk and ssp sclk early Sriram Periyasamy
2018-01-26 12:53   ` Applied "ASoC: Intel: kbl: Enable mclk and ssp sclk early" to the asoc tree Mark Brown
2018-01-26 12:53     ` Mark Brown
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 4/6] ASoC: Intel: eve: Enable mclk and ssp sclk early Sriram Periyasamy
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 5/6] ASoC: Intel: Skylake: Make DSP replies more human readable Sriram Periyasamy
2017-12-12 18:27   ` Patel, Chintan M
2017-12-12 18:27     ` Patel, Chintan M
2017-12-13  3:25     ` Vinod Koul [this message]
2017-12-13  3:25       ` Vinod Koul
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 6/6] ASoC: Intel: Skylake: Add FW reply for MCLK/SCLK IPC Sriram Periyasamy

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