* [PATCH 00/17] ICL display initialization and some plane bits
@ 2018-01-23 19:05 Paulo Zanoni
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
` (22 more replies)
0 siblings, 23 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Hi
Here's another ICL series. This one includes the very basic steps of display
initialization (although missing quite a few pieces) and some patches related to
planes (dbuf, mbus, bit field changes). Nothing special.
Again, as explained in the other series, the R-B tags in these patches were
given to earlier versions, so they need to be re-confirmed since upstream has
moved quite a bit since then.
Thanks,
Paulo
James Ausmus (1):
drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
Mahesh Kumar (12):
drm/i915/icl: Enable both DBuf slices during init
drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
drm/i915/icl: Do not fix dbuf block size to 512
drm/i915/icl: Fail flip if ddb allocated are less than min display
buffer needed
drm/i915/icl: NV12 y-plane ddb is not in same plane
drm/i915/icl: Introduce MBus related registers
drm/i915/icl: initialize MBus during display init
drm/i915/icl: program mbus during pipe enable
drm/i915/icl: track dbuf slice-2 status
drm/i915/icl: Enable 2nd DBuf slice only when needed
drm/i915/icl: update ddb entry start/end mask during hw ddb readout
drm/i915/icl: enable SAGV for ICL platform
Paulo Zanoni (4):
drm/i915/icl: add the main CDCLK functions
drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
drm/i915/icl: implement the display init/uninit sequences
drm/i915/gen11: fix the SAGV block time for gen11
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 85 ++++++++++-
drivers/gpu/drm/i915/intel_cdclk.c | 253 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 42 +++++-
drivers/gpu/drm/i915/intel_drv.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 173 ++++++++++++++++++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 188 ++++++++++++++++++++++--
7 files changed, 706 insertions(+), 45 deletions(-)
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-26 23:14 ` James Ausmus
` (2 more replies)
2018-01-23 19:05 ` [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Paulo Zanoni
` (21 subsequent siblings)
22 siblings, 3 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.
v2:
- Implement the voltage levels.
- Rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
drivers/gpu/drm/i915/intel_cdclk.c | 253 ++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 261 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abd9ee876186..d72e206b2b9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7113,8 +7113,12 @@ enum {
#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
-#define SKL_DSSM _MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
+#define SKL_DSSM _MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
@@ -8760,6 +8764,8 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
+#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
+#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
/* LCPLL_CTL */
#define LCPLL1_CTL _MMIO(0x46010)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index c4392ea34a3d..d867956d5a9f 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
dev_priv->cdclk.hw.vco = -1;
}
+static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
+{
+ int ranges_24[] = { 312000, 552000, 648000 };
+ int ranges_19_38[] = { 307200, 556800, 652800 };
+ int *ranges;
+
+ switch (ref) {
+ default:
+ MISSING_CASE(ref);
+ case 24000:
+ ranges = ranges_24;
+ break;
+ case 19200:
+ case 38400:
+ ranges = ranges_19_38;
+ break;
+ }
+
+ if (min_cdclk > ranges[1])
+ return ranges[2];
+ else if (min_cdclk > ranges[0])
+ return ranges[1];
+ else
+ return ranges[0];
+}
+
+static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+ int ratio;
+
+ /* 50MHz == CDCLK PLL disabled. */
+ if (cdclk == 50000)
+ return 0;
+
+ switch (cdclk) {
+ default:
+ MISSING_CASE(cdclk);
+ case 307200:
+ case 556800:
+ case 652800:
+ WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
+ dev_priv->cdclk.hw.ref != 38400);
+ break;
+ case 312000:
+ case 552000:
+ case 648000:
+ WARN_ON(dev_priv->cdclk.hw.ref != 24000);
+ }
+
+ ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
+
+ return dev_priv->cdclk.hw.ref * ratio;
+}
+
+static void icl_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *cdclk_state)
+{
+ unsigned int cdclk = cdclk_state->cdclk;
+ unsigned int vco = cdclk_state->vco;
+ int ret;
+ u32 voltage_level;
+
+ mutex_lock(&dev_priv->pcu_lock);
+ ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
+ mutex_unlock(&dev_priv->pcu_lock);
+ if (ret) {
+ DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+ ret);
+ return;
+ }
+
+ /* FIXME: We should also consider the DDI clock here. */
+ switch (cdclk) {
+ case 307200:
+ case 312000:
+ voltage_level = 0;
+ break;
+ case 556800:
+ case 552000:
+ voltage_level = 1;
+ break;
+ default:
+ MISSING_CASE(cdclk);
+ case 652800:
+ case 648000:
+ voltage_level = 2;
+ break;
+ }
+
+ if (dev_priv->cdclk.hw.vco != 0 &&
+ dev_priv->cdclk.hw.vco != vco)
+ cnl_cdclk_pll_disable(dev_priv);
+
+ if (dev_priv->cdclk.hw.vco != vco)
+ cnl_cdclk_pll_enable(dev_priv, vco);
+
+ I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
+ skl_cdclk_decimal(cdclk));
+
+ mutex_lock(&dev_priv->pcu_lock);
+ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ voltage_level);
+ mutex_unlock(&dev_priv->pcu_lock);
+
+ intel_update_cdclk(dev_priv);
+}
+
+static void icl_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state *cdclk_state)
+{
+ u32 val;
+
+ val = I915_READ(SKL_DSSM);
+ switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
+ default:
+ MISSING_CASE(val);
+ case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
+ cdclk_state->ref = 24000;
+ break;
+ case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
+ cdclk_state->ref = 19200;
+ break;
+ case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
+ cdclk_state->ref = 38400;
+ break;
+ }
+
+ val = I915_READ(BXT_DE_PLL_ENABLE);
+ if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
+ (val & BXT_DE_PLL_LOCK) == 0) {
+ /* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
+ * setting it to zero is a way to signal that. */
+ cdclk_state->vco = 0;
+ cdclk_state->cdclk = 50000;
+ return;
+ }
+
+ cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
+
+ val = I915_READ(CDCLK_CTL);
+ WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
+
+ cdclk_state->cdclk = cdclk_state->vco / 2;
+}
+
+/**
+ * icl_init_cdclk - Initialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Initialize CDCLK for ICL. This consists mainly of initializing
+ * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
+ * is generally done only during the display core initialization sequence, after
+ * which the DMC will take care of turning CDCLK off/on as needed.
+ */
+void icl_init_cdclk(struct drm_i915_private *dev_priv)
+{
+ struct intel_cdclk_state cdclk_state;
+ u32 val;
+
+ /* This sets dev_priv->cdclk.hw. */
+ intel_update_cdclk(dev_priv);
+
+ cdclk_state = dev_priv->cdclk.hw;
+
+ /* This means CDCLK disabled. */
+ if (cdclk_state.cdclk == 50000)
+ goto sanitize;
+
+ val = I915_READ(CDCLK_CTL);
+
+ if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
+ goto sanitize;
+
+ if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
+ skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
+ goto sanitize;
+
+ return;
+
+sanitize:
+ DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
+
+ cdclk_state.ref = dev_priv->cdclk.hw.ref;
+ cdclk_state.cdclk = icl_calc_cdclk(0, cdclk_state.ref);
+ cdclk_state.vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
+
+ icl_set_cdclk(dev_priv, &cdclk_state);
+}
+
+/**
+ * icl_uninit_cdclk - Uninitialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Uninitialize CDCLK for ICL. This is done only during the display core
+ * uninitialization sequence.
+ */
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
+{
+ struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+
+ cdclk_state.cdclk = cdclk_state.ref;
+ cdclk_state.vco = 0;
+
+ icl_set_cdclk(dev_priv, &cdclk_state);
+}
+
/**
* cnl_init_cdclk - Initialize CDCLK on CNL
* @dev_priv: i915 device
@@ -2204,6 +2413,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
return 0;
}
+static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ unsigned int ref = intel_state->cdclk.logical.ref;
+ int min_cdclk, cdclk, vco;
+
+ min_cdclk = intel_compute_min_cdclk(state);
+ if (min_cdclk < 0)
+ return min_cdclk;
+
+ cdclk = icl_calc_cdclk(min_cdclk, ref);
+ vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+ intel_state->cdclk.logical.vco = vco;
+ intel_state->cdclk.logical.cdclk = cdclk;
+
+ if (!intel_state->active_crtcs) {
+ cdclk = icl_calc_cdclk(0, ref);
+ vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+ intel_state->cdclk.actual.vco = vco;
+ intel_state->cdclk.actual.cdclk = cdclk;
+ } else {
+ intel_state->cdclk.actual = intel_state->cdclk.logical;
+ }
+
+ return 0;
+}
+
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
int max_cdclk_freq = dev_priv->max_cdclk_freq;
@@ -2237,7 +2476,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ if (dev_priv->cdclk.hw.ref == 24000)
+ dev_priv->max_cdclk_freq = 648000;
+ else
+ dev_priv->max_cdclk_freq = 652800;
+ } else if (IS_CANNONLAKE(dev_priv)) {
dev_priv->max_cdclk_freq = 528000;
} else if (IS_GEN9_BC(dev_priv)) {
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
@@ -2461,9 +2705,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.set_cdclk = cnl_set_cdclk;
dev_priv->display.modeset_calc_cdclk =
cnl_modeset_calc_cdclk;
+ } else if (IS_ICELAKE(dev_priv)) {
+ dev_priv->display.set_cdclk = icl_set_cdclk;
+ dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
}
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.get_cdclk = icl_get_cdclk;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.get_cdclk = cnl_get_cdclk;
else if (IS_GEN9_BC(dev_priv))
dev_priv->display.get_cdclk = skl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3cee54bc0352..c5d6092aca41 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
+void icl_init_cdclk(struct drm_i915_private *dev_priv);
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-24 0:32 ` James Ausmus
` (2 more replies)
2018-01-23 19:05 ` [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences Paulo Zanoni
` (20 subsequent siblings)
22 siblings, 3 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
On ICL we have two sets of registers: one for port A and another for
port B. The set of port A registers is the same as the CNL registers.
Since the procmon table on ICL is the same we want to reuse the CNL
function. To do that we add a port argument and make CNL always call
the function passing port A. This way, we'll be able to easily reuse
the function on ICL when we add icl_display_core_init().
v2: Don't use _PICK() when you can use a ternary operator.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++++++++++++++-------
2 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d72e206b2b9f..ebf6261d30fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2102,6 +2102,32 @@ enum i915_power_well_id {
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
+#define _ICL_PORT_COMP_DW0_A 0x162100
+#define _ICL_PORT_COMP_DW0_B 0x6C100
+#define ICL_PORT_COMP_DW0(port) _MMIO((port == PORT_A) ? \
+ _ICL_PORT_COMP_DW0_A : \
+ _ICL_PORT_COMP_DW0_B)
+#define _ICL_PORT_COMP_DW1_A 0x162104
+#define _ICL_PORT_COMP_DW1_B 0x6C104
+#define ICL_PORT_COMP_DW1(port) _MMIO((port == PORT_A) ? \
+ _ICL_PORT_COMP_DW1_A : \
+ _ICL_PORT_COMP_DW1_B)
+#define _ICL_PORT_COMP_DW3_A 0x16210C
+#define _ICL_PORT_COMP_DW3_B 0x6C10C
+#define ICL_PORT_COMP_DW3(port) _MMIO((port == PORT_A) ? \
+ _ICL_PORT_COMP_DW3_A : \
+ _ICL_PORT_COMP_DW3_B)
+#define _ICL_PORT_COMP_DW9_A 0x162124
+#define _ICL_PORT_COMP_DW9_B 0x6C124
+#define ICL_PORT_COMP_DW9(port) _MMIO((port == PORT_A) ? \
+ _ICL_PORT_COMP_DW9_A : \
+ _ICL_PORT_COMP_DW9_B)
+#define _ICL_PORT_COMP_DW10_A 0x162128
+#define _ICL_PORT_COMP_DW10_B 0x6C128
+#define ICL_PORT_COMP_DW10(port) _MMIO((port == PORT_A) ? \
+ _ICL_PORT_COMP_DW10_A : \
+ _ICL_PORT_COMP_DW10_B)
+
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5b1aa4b9c72c..73dd525d241a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
};
-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
+/*
+ * CNL has just one set of registers, while ICL has two sets: one for port A and
+ * the other for port B. The CNL registers are equivalent to the ICL port A
+ * registers, that's why we call the ICL macros even though the function has CNL
+ * on its name.
+ */
+static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
+ enum port port)
{
const struct cnl_procmon *procmon;
u32 val;
- val = I915_READ(CNL_PORT_COMP_DW3);
+ val = I915_READ(ICL_PORT_COMP_DW3(port));
switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
default:
MISSING_CASE(val);
@@ -2784,13 +2791,13 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
break;
}
- val = I915_READ(CNL_PORT_COMP_DW1);
+ val = I915_READ(ICL_PORT_COMP_DW1(port));
val &= ~((0xff << 16) | 0xff);
val |= procmon->dw1;
- I915_WRITE(CNL_PORT_COMP_DW1, val);
+ I915_WRITE(ICL_PORT_COMP_DW1(port), val);
- I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
- I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
+ I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
+ I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
}
static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
@@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
val &= ~CNL_COMP_PWR_DOWN;
I915_WRITE(CHICKEN_MISC_2, val);
- cnl_set_procmon_ref_values(dev_priv);
+ cnl_set_procmon_ref_values(dev_priv, PORT_A);
val = I915_READ(CNL_PORT_COMP_DW0);
val |= COMP_INIT;
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
2018-01-23 19:05 ` [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-26 23:25 ` James Ausmus
2018-01-23 19:05 ` [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init Paulo Zanoni
` (19 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This code is similar enough to the CNL code that I considered just
adding ICL support to the CNL function, but I think it's still
different enough, and having a function specific to ICL allows us to
more easily adapt code in case the spec changes more later.
We're still missing the power wells and the mbus code, so leave those
pieces with a FIXME comment while they're not here yet.
v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 16 ++++++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 82 ++++++++++++++++++++++++++++++++-
2 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ebf6261d30fd..979bc06a59f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1904,6 +1904,11 @@ enum i915_power_well_id {
#define CL_POWER_DOWN_ENABLE (1 << 4)
#define SUS_CLOCK_CONFIG (3 << 0)
+#define _ICL_PORT_CL_DW5_A 0x162014
+#define _ICL_PORT_CL_DW5_B 0x6C014
+#define ICL_PORT_CL_DW5(port) _MMIO((port == PORT_A) ? \
+ _ICL_PORT_CL_DW5_A : _ICL_PORT_CL_DW5_B)
+
#define _PORT_CL1CM_DW9_A 0x162024
#define _PORT_CL1CM_DW9_BC 0x6C024
#define IREF0RC_OFFSET_SHIFT 8
@@ -7126,8 +7131,9 @@ enum {
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
-#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
-#define MASK_WAKEMEM (1<<13)
+#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
+#define MASK_WAKEMEM (1 << 13)
+#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
#define SKL_DFSM _MMIO(0x51000)
#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
@@ -9696,4 +9702,10 @@ enum skl_power_gate {
#define MMCD_PCLA (1 << 31)
#define MMCD_HOTSPOT_EN (1 << 27)
+#define _ICL_PHY_MISC_A 0x64C00
+#define _ICL_PHY_MISC_B 0x64C04
+#define ICL_PHY_MISC(port) _MMIO((port == PORT_A) ? \
+ _ICL_PHY_MISC_A : _ICL_PHY_MISC_B)
+#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 73dd525d241a..2556db16c76a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2882,6 +2882,80 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
}
+static void icl_display_core_init(struct drm_i915_private *dev_priv,
+ bool resume)
+{
+ enum port port;
+ u32 val;
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+ /* 1. Enable PCH reset handshake. */
+ val = I915_READ(HSW_NDE_RSTWRN_OPT);
+ val |= RESET_PCH_HANDSHAKE_ENABLE;
+ I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+ for (port = PORT_A; port <= PORT_B; port++) {
+ /* 2. Enable DDI combo PHY comp. */
+ val = I915_READ(ICL_PHY_MISC(port));
+ val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
+ I915_WRITE(ICL_PHY_MISC(port), val);
+
+ cnl_set_procmon_ref_values(dev_priv, port);
+
+ val = I915_READ(ICL_PORT_COMP_DW0(port));
+ val |= COMP_INIT;
+ I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+
+ /* 3. Set power down enable. */
+ val = I915_READ(ICL_PORT_CL_DW5(port));
+ val |= CL_POWER_DOWN_ENABLE;
+ I915_WRITE(ICL_PORT_CL_DW5(port), val);
+ }
+
+ /* 4. Enable power well 1 (PG1) and aux IO power. */
+ /* FIXME: ICL power wells code not here yet. */
+
+ /* 5. Enable CDCLK. */
+ icl_init_cdclk(dev_priv);
+
+ /* 6. Enable DBUF. */
+ gen9_dbuf_enable(dev_priv);
+
+ /* 7. Setup MBUS. */
+ /* FIXME: MBUS code not here yet. */
+
+ /* 8. CHICKEN_DCPR_1 */
+ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
+ CNL_DDI_CLOCK_REG_ACCESS_ON);
+}
+
+static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
+{
+ enum port port;
+ u32 val;
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+ /* 1. Disable all display engine functions -> aready done */
+
+ /* 2. Disable DBUF */
+ gen9_dbuf_disable(dev_priv);
+
+ /* 3. Disable CD clock */
+ icl_uninit_cdclk(dev_priv);
+
+ /* 4. Disable Power Well 1 (PG1) and Aux IO Power */
+ /* FIXME: ICL power wells code not here yet. */
+
+ /* 5. Disable Comp */
+ for (port = PORT_A; port <= PORT_B; port++) {
+ val = I915_READ(ICL_PHY_MISC(port));
+ val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
+ I915_WRITE(ICL_PHY_MISC(port), val);
+ }
+}
+
static void chv_phy_control_init(struct drm_i915_private *dev_priv)
{
struct i915_power_well *cmn_bc =
@@ -3014,7 +3088,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
power_domains->initializing = true;
- if (IS_CANNONLAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ icl_display_core_init(dev_priv, resume);
+ } else if (IS_CANNONLAKE(dev_priv)) {
cnl_display_core_init(dev_priv, resume);
} else if (IS_GEN9_BC(dev_priv)) {
skl_display_core_init(dev_priv, resume);
@@ -3055,7 +3131,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
if (!i915_modparams.disable_power_well)
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ icl_display_core_uninit(dev_priv);
+ else if (IS_CANNONLAKE(dev_priv))
cnl_display_core_uninit(dev_priv);
else if (IS_GEN9_BC(dev_priv))
skl_display_core_uninit(dev_priv);
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (2 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-24 0:49 ` James Ausmus
2018-01-23 19:05 ` [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
` (18 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
ICL has 2 slices of DBuf, enable both the slices during display init.
Ideally we should only enable the second slice when needed in order to
save power, but while we're not there yet, adopt the simpler solution
to keep us bug-free.
v2 (from Paulo):
- Add the TODO comment.
- Reorganize where things are defined.
- Fix indentation.
- Remove unnecessary POSTING_READ() calls.
- Improve the commit message.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++++++++++++++++--
2 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 979bc06a59f4..1746df9a263d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7122,6 +7122,8 @@ enum {
#define DISP_DATA_PARTITION_5_6 (1<<6)
#define DISP_IPC_ENABLE (1<<3)
#define DBUF_CTL _MMIO(0x45008)
+#define DBUF_CTL_S1 _MMIO(0x45008)
+#define DBUF_CTL_S2 _MMIO(0x44FE8)
#define DBUF_POWER_REQUEST (1<<31)
#define DBUF_POWER_STATE (1<<30)
#define GEN7_MSG_CTL _MMIO(0x45010)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 2556db16c76a..7801a425398f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
DRM_ERROR("DBuf power disable timeout!\n");
}
+/*
+ * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
+ * needed and keep it disabled as much as possible.
+ */
+static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
+ I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
+ POSTING_READ(DBUF_CTL_S2);
+
+ udelay(10);
+
+ if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
+ !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
+ DRM_ERROR("DBuf power enable timeout\n");
+}
+
+static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
+ I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
+ POSTING_READ(DBUF_CTL_S2);
+
+ udelay(10);
+
+ if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
+ (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
+ DRM_ERROR("DBuf power disable timeout!\n");
+}
+
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
@@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
icl_init_cdclk(dev_priv);
/* 6. Enable DBUF. */
- gen9_dbuf_enable(dev_priv);
+ icl_dbuf_enable(dev_priv);
/* 7. Setup MBUS. */
/* FIXME: MBUS code not here yet. */
@@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 1. Disable all display engine functions -> aready done */
/* 2. Disable DBUF */
- gen9_dbuf_disable(dev_priv);
+ icl_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
icl_uninit_cdclk(dev_priv);
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (3 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-24 0:58 ` James Ausmus
2018-01-23 19:05 ` [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
` (17 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
GEN9 onwards bypass path allocation of 4 blocks was needed, as per
hardware design. ICL doesn't require bypass path allocation of 4 DDB
blocks, handling the same in this patch.
v2 (from Paulo):
- No need for a comment that says what the code already says.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b92ea1dbd40..11aac65d1543 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3778,7 +3778,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
- ddb_size -= 4; /* 4 blocks for bypass path allocation */
+ if (INTEL_GEN(dev_priv) < 11)
+ ddb_size -= 4; /* 4 blocks for bypass path allocation */
/*
* If the state doesn't change the active CRTC's, then there's
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (4 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-24 1:14 ` James Ausmus
2018-01-29 23:07 ` Paulo Zanoni
2018-01-23 19:05 ` [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
` (16 subsequent siblings)
22 siblings, 2 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512
This patch addresses the same.
v2 (from Paulo):
- Make it compile.
- Fix a few coding style issues.
v3
- Rebase on top of upstream patches
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++-------
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8333692dac5a..cc5ac327f267 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1460,6 +1460,7 @@ struct skl_wm_params {
uint_fixed_16_16_t plane_blocks_per_line;
uint_fixed_16_16_t y_tile_minimum;
uint32_t linetime_us;
+ uint32_t dbuf_block_size;
};
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 11aac65d1543..44d952a3d9a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
static uint_fixed_16_16_t
skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
- uint8_t cpp, uint32_t latency)
+ uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
{
uint32_t wm_intermediate_val;
uint_fixed_16_16_t ret;
@@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
return FP_16_16_MAX;
wm_intermediate_val = latency * pixel_rate * cpp;
- ret = div_fixed16(wm_intermediate_val, 1000 * 512);
+ ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
if (INTEL_GEN(dev_priv) >= 10)
ret = add_fixed16_u32(ret, 1);
@@ -4431,6 +4431,15 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if (fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
+ wp->dbuf_block_size = 256;
+ else
+ wp->dbuf_block_size = 512;
+ } else {
+ wp->dbuf_block_size = 512;
+ }
+
if (drm_rotation_90_or_270(pstate->rotation)) {
switch (wp->cpp) {
@@ -4457,7 +4466,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_bytes_per_line = wp->width * wp->cpp;
if (wp->y_tiled) {
interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
- wp->y_min_scanlines, 512);
+ wp->y_min_scanlines,
+ wp->dbuf_block_size);
if (INTEL_GEN(dev_priv) >= 10)
interm_pbpl++;
@@ -4465,10 +4475,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
wp->y_min_scanlines);
} else if (wp->x_tiled && IS_GEN9(dev_priv)) {
- interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
+ interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+ wp->dbuf_block_size);
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
} else {
- interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
+ interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+ wp->dbuf_block_size) + 1;
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
}
@@ -4515,7 +4527,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
latency += 15;
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
- wp->cpp, latency);
+ wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
cstate->base.adjusted_mode.crtc_htotal,
latency,
@@ -4525,7 +4537,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
selected_result = max_fixed16(method2, wp->y_tile_minimum);
} else {
if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
- 512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
+ wp->dbuf_block_size < 1) &&
+ (wp->plane_bytes_per_line / wp->dbuf_block_size < 1))
selected_result = method2;
else if (ddb_allocation >=
fixed16_to_u32_round_up(wp->plane_blocks_per_line))
--
2.14.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (5 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-26 23:50 ` James Ausmus
2018-01-29 23:08 ` [PATCH 07/13] " Paulo Zanoni
2018-01-23 19:05 ` [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
` (15 subsequent siblings)
22 siblings, 2 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.
This patch implements and consider the same while allocating DDB
and enabling WM.
Changes Since V1:
- rebase
Changes Since V2:
- Remove extra parentheses
- Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
- Rebase
Changes since v4 (from Paulo)
- Coding style issue.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 44d952a3d9a6..c6d31a5075ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+ uint32_t min_disp_buf_needed;
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
@@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
- if (res_blocks >= ddb_allocation || res_lines > 31) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if (wp->y_tiled) {
+ uint32_t extra_lines;
+ uint_fixed_16_16_t fp_min_disp_buf_needed;
+
+ if (res_lines % wp->y_min_scanlines == 0)
+ extra_lines = wp->y_min_scanlines;
+ else
+ extra_lines = wp->y_min_scanlines * 2 -
+ res_lines % wp->y_min_scanlines;
+
+ fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
+ extra_lines,
+ wp->plane_blocks_per_line);
+ min_disp_buf_needed = fixed16_to_u32_round_up(
+ fp_min_disp_buf_needed);
+ } else {
+ min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
+ }
+ } else {
+ /*
+ * To enable a WM level ddb_allocation should be
+ * greater than result blocks for GEN-9/10.
+ */
+ min_disp_buf_needed = res_blocks + 1;
+ }
+
+ if (min_disp_buf_needed > ddb_allocation || res_lines > 31) {
*enabled = false;
/*
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (6 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 22:31 ` James Ausmus
2018-01-23 19:05 ` [PATCH 09/17] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
` (14 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
We don't have planar pixel format support implemented for ICL yet.
ICL require 2 display planes to be allocated for Planar formats unlike
previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in ICL.
This patch removes the PLANE_NV12_BUF_CFG write for ICL.
Changes Since V1:
- Improve commit message as per Paulo's comment
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c6d31a5075ad..0237362ccf83 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4832,8 +4832,10 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
&ddb->plane[pipe][plane_id]);
- skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
- &ddb->y_plane[pipe][plane_id]);
+ if (INTEL_GEN(dev_priv) < 11)
+ skl_ddb_entry_write(dev_priv,
+ PLANE_NV12_BUF_CFG(pipe, plane_id),
+ &ddb->y_plane[pipe][plane_id]);
}
static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 09/17] drm/i915/icl: Introduce MBus related registers
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (7 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 22:38 ` James Ausmus
2018-01-23 19:05 ` [PATCH 10/17] drm/i915/icl: initialize MBus during display init Paulo Zanoni
` (13 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1746df9a263d..0cb77cd18cdb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2679,6 +2679,31 @@ enum i915_power_well_id {
#define LM_FIFO_WATERMARK 0x0000001F
#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
+#define MBUS_ABOX_CTL _MMIO(0x45038)
+#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
+#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
+#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
+#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
+#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
+#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
+
+#define _PIPEA_MBUS_DBOX_CTL 0x7003C
+#define _PIPEB_MBUS_DBOX_CTL 0x7103C
+#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
+ _PIPEB_MBUS_DBOX_CTL)
+#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
+#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
+#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
+#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
+#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
+#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
+
+#define MBUS_UBOX_CTL _MMIO(0x4503C)
+#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
+#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
+
/* Make render/texture TLB fetches lower priorty than associated data
* fetches. This is not turned on by default
*/
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 10/17] drm/i915/icl: initialize MBus during display init
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (8 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 09/17] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 22:39 ` James Ausmus
2018-01-23 19:05 ` [PATCH 11/17] drm/i915/icl: program mbus during pipe enable Paulo Zanoni
` (12 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch initializes MBus during display initialization.
Changes since V2 (from Paulo):
- Don't forget to remove the WARN_ON(1) call.
Changes since V1:
- Rebase to use function like Macros
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 7801a425398f..a6ed01a528bd 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2640,6 +2640,18 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
DRM_ERROR("DBuf power disable timeout!\n");
}
+static void icl_mbus_init(struct drm_i915_private *dev_priv)
+{
+ uint32_t val;
+
+ val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
+ MBUS_ABOX_BT_CREDIT_POOL2(16) |
+ MBUS_ABOX_B_CREDIT(1) |
+ MBUS_ABOX_BW_CREDIT(1);
+
+ I915_WRITE(MBUS_ABOX_CTL, val);
+}
+
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
@@ -2953,7 +2965,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
icl_dbuf_enable(dev_priv);
/* 7. Setup MBUS. */
- /* FIXME: MBUS code not here yet. */
+ icl_mbus_init(dev_priv);
/* 8. CHICKEN_DCPR_1 */
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 11/17] drm/i915/icl: program mbus during pipe enable
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (9 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 10/17] drm/i915/icl: initialize MBus during display init Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 22:42 ` James Ausmus
2018-01-23 19:05 ` [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status Paulo Zanoni
` (11 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch program default values of MBus credit during pipe enable.
Changes since V2:
- We don't need to do anything when disabling the pipe
Changes Since V1:
- Add WARN_ON (Paulo)
- Remove TODO comment
- Program 0 during pipe disable
- Rebase
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d585ce4c8732..0dc4ef6cd46e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5380,6 +5380,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
}
+static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ uint32_t val;
+
+ if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+ return;
+
+ val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
+
+ /* Program B credit equally to all pipes */
+ val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
+
+ I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
+}
+
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct drm_atomic_state *old_state)
{
@@ -5457,6 +5474,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_pipe_mbus_enable(intel_crtc);
+
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
intel_enable_pipe(pipe_config);
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (10 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 11/17] drm/i915/icl: program mbus during pipe enable Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 23:08 ` James Ausmus
2018-01-23 19:05 ` [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed Paulo Zanoni
` (10 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch adds support to start tracking status of DBUF slices.
This is foundation to introduce support for enabling/disabling second
DBUF slice dynamically for ICL.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 5 +++++
drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++++
4 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cc5ac327f267..eae18661eaec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1435,6 +1435,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
struct skl_ddb_allocation {
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+ uint8_t enabled_slices; /* GEN11 has configurable 2 slices */
};
struct skl_wm_values {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0dc4ef6cd46e..bad3b112ac3e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11302,6 +11302,11 @@ static void verify_wm_state(struct drm_crtc *crtc,
skl_ddb_get_hw_state(dev_priv, &hw_ddb);
sw_ddb = &dev_priv->wm.skl_hw.ddb;
+ if (INTEL_GEN(dev_priv) >= 11)
+ if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
+ DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
+ sw_ddb->enabled_slices,
+ hw_ddb.enabled_slices);
/* planes */
for_each_universal_plane(dev_priv, pipe, plane) {
hw_plane_wm = &hw_wm.planes[plane];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0237362ccf83..e8d98857c208 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3570,6 +3570,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
+static uint8_t intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+{
+ uint8_t enabled_slices;
+
+ /* Slice 1 will always be enabled */
+ enabled_slices = 1;
+
+ /* Gen prior to GEN11 have only one DBuf slice */
+ if (INTEL_GEN(dev_priv) < 11)
+ return enabled_slices;
+
+ if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ enabled_slices++;
+
+ return enabled_slices;
+}
+
/*
* FIXME: We still don't have the proper code detect if we need to apply the WA,
* so assume we'll always need it in order to avoid underruns.
@@ -3828,6 +3845,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
memset(ddb, 0, sizeof(*ddb));
+ ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+
for_each_intel_crtc(&dev_priv->drm, crtc) {
enum intel_display_power_domain power_domain;
enum plane_id plane_id;
@@ -5049,6 +5068,7 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
sizeof(dst->ddb.y_plane[pipe]));
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
sizeof(dst->ddb.plane[pipe]));
+ dst->ddb.enabled_slices = src->ddb.enabled_slices;
}
static void
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a6ed01a528bd..13c8dad95b84 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2625,6 +2625,8 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
!(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power enable timeout\n");
+ else
+ dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -2638,6 +2640,8 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power disable timeout!\n");
+ else
+ dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (11 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 22:56 ` James Ausmus
2018-03-14 16:19 ` [PATCH 2/2] " Mahesh Kumar
2018-01-23 19:05 ` [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout Paulo Zanoni
` (9 subsequent siblings)
22 siblings, 2 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
ICL has two slices of DBuf, each slice of size 1024 blocks.
We should not always enable slice-2. It should be enabled only if
display total required BW is > 12GBps OR more than 1 pipes are enabled.
Changes since V1:
- typecast total_data_rate to u64 before multiplication to solve any
possible overflow (Rodrigo)
- fix where skl_wm_get_hw_state was memsetting ddb, resulting
enabled_slices to become zero
- Fix the logic of calculating ddb_size
Changes since V2:
- If no-crtc is part of commit required_slices will have value "0",
don't try to disable DBuf slice.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 12 +++++++
drivers/gpu/drm/i915/intel_drv.h | 6 ++++
drivers/gpu/drm/i915/intel_pm.c | 64 +++++++++++++++++++++++++--------
drivers/gpu/drm/i915/intel_runtime_pm.c | 47 +++++++++++++++++++++---
4 files changed, 110 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bad3b112ac3e..3eb2359c221b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12117,6 +12117,8 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
bool progress;
enum pipe pipe;
int i;
+ uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ uint8_t required_slices = intel_state->wm_results.ddb.enabled_slices;
const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
@@ -12125,6 +12127,11 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
if (new_crtc_state->active)
entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
+ /* If 2nd DBuf slice required, enable it here */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
+ required_slices > hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
@@ -12175,6 +12182,11 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
progress = true;
}
} while (progress);
+
+ /* If 2nd DBuf slice is no more required disable it */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
+ required_slices < hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
}
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c5d6092aca41..d4639a161fe3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -140,6 +140,10 @@
#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
+#define KBps(x) (1000 * (x))
+#define MBps(x) KBps(1000 * (x))
+#define GBps(x) ((uint64_t) 1000 * MBps((x)))
+
/*
* Display related stuff
*/
@@ -1890,6 +1894,8 @@ bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
+void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+ uint8_t req_slices);
static inline void
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e8d98857c208..d4cd631377da 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3767,9 +3767,42 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
return true;
}
+static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *cstate,
+ const unsigned int total_data_rate,
+ const int num_active,
+ struct skl_ddb_allocation *ddb)
+{
+ const struct drm_display_mode *adjusted_mode;
+ u64 total_data_bw;
+ u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+
+ WARN_ON(ddb_size == 0);
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return ddb_size - 4; /* 4 blocks for bypass path allocation */
+
+ adjusted_mode = &cstate->base.adjusted_mode;
+ total_data_bw = (u64)total_data_rate * drm_mode_vrefresh(adjusted_mode);
+
+ /*
+ * 12GB/s is maximum BW supported by single DBuf slice.
+ */
+ if (total_data_bw >= GBps(12) || num_active > 1)
+ ddb->enabled_slices = 2;
+ else {
+ ddb->enabled_slices = 1;
+ ddb_size /= 2;
+ }
+
+ return ddb_size;
+}
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
const struct intel_crtc_state *cstate,
+ const unsigned int total_data_rate,
+ struct skl_ddb_allocation *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
@@ -3792,11 +3825,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
- ddb_size = INTEL_INFO(dev_priv)->ddb_size;
- WARN_ON(ddb_size == 0);
-
- if (INTEL_GEN(dev_priv) < 11)
- ddb_size -= 4; /* 4 blocks for bypass path allocation */
+ ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,
+ *num_active, ddb);
/*
* If the state doesn't change the active CRTC's, then there's
@@ -4235,7 +4265,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
return 0;
}
- skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
+ total_data_rate = skl_get_total_relative_data_rate(cstate,
+ plane_data_rate,
+ plane_y_data_rate);
+ if (total_data_rate == 0)
+ return 0;
+
+ skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,
+ alloc, &num_active);
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0)
return 0;
@@ -4270,12 +4307,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*
* FIXME: we may not allocate every single block here.
*/
- total_data_rate = skl_get_total_relative_data_rate(cstate,
- plane_data_rate,
- plane_y_data_rate);
- if (total_data_rate == 0)
- return 0;
-
start = alloc->start;
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
unsigned int data_rate, y_data_rate;
@@ -5068,7 +5099,6 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
sizeof(dst->ddb.y_plane[pipe]));
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
sizeof(dst->ddb.plane[pipe]));
- dst->ddb.enabled_slices = src->ddb.enabled_slices;
}
static void
@@ -5381,8 +5411,12 @@ void skl_wm_get_hw_state(struct drm_device *dev)
/* Fully recompute DDB on first atomic commit */
dev_priv->wm.distrust_bios_wm = true;
} else {
- /* Easy/common case; just sanitize DDB now if everything off */
- memset(ddb, 0, sizeof(*ddb));
+ /*
+ * Easy/common case; just sanitize DDB now if everything off
+ * Keep dbuf slice info intact
+ */
+ memset(ddb->plane, 0, sizeof(ddb->plane));
+ memset(ddb->y_plane, 0, sizeof(ddb->y_plane));
}
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 13c8dad95b84..a67a57738740 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2610,10 +2610,49 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
DRM_ERROR("DBuf power disable timeout!\n");
}
-/*
- * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
- * needed and keep it disabled as much as possible.
- */
+static uint8_t intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_GEN(dev_priv) < 11)
+ return 1;
+ return 2;
+}
+
+void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+ uint8_t req_slices)
+{
+ uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ u32 val;
+
+ if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+ DRM_ERROR("Invalid number of dbuf slices requested\n");
+ return;
+ }
+
+ if (req_slices == hw_enabled_slices)
+ return;
+
+ val = I915_READ(DBUF_CTL_S2);
+ if (req_slices > hw_enabled_slices) {
+ I915_WRITE(DBUF_CTL_S2, val | DBUF_POWER_REQUEST);
+ POSTING_READ(DBUF_CTL_S2);
+
+ udelay(10);
+ if (!(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
+ DRM_ERROR("DBuf power enable timeout\n");
+ else
+ dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
+ } else {
+ I915_WRITE(DBUF_CTL_S2, val & ~DBUF_POWER_REQUEST);
+ POSTING_READ(DBUF_CTL_S2);
+
+ udelay(10);
+ if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ DRM_ERROR("DBuf power disable timeout!\n");
+ else
+ dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
+ }
+}
+
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (12 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 23:00 ` James Ausmus
2018-01-23 19:05 ` [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
` (8 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
11 bits. This patch make changes to use proper mask for ICL+ during
hardware ddb value readout.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d4cd631377da..84a5b13fdee2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3860,10 +3860,18 @@ static unsigned int skl_cursor_allocation(int num_active)
return 8;
}
-static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
+static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
+ struct skl_ddb_entry *entry, u32 reg)
{
- entry->start = reg & 0x3ff;
- entry->end = (reg >> 16) & 0x3ff;
+ uint16_t mask;
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ mask = 0x7ff;
+ else
+ mask = 0x3ff;
+ entry->start = reg & mask;
+ entry->end = (reg >> 16) & mask;
+
if (entry->end)
entry->end += 1;
}
@@ -3894,7 +3902,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
else
val = I915_READ(CUR_BUF_CFG(pipe));
- skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+ skl_ddb_entry_init_from_hw(dev_priv,
+ &ddb->plane[pipe][plane_id],
+ val);
}
intel_display_power_put(dev_priv, power_domain);
--
2.14.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (13 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 23:09 ` James Ausmus
2018-01-23 19:05 ` [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform Paulo Zanoni
` (7 subsequent siblings)
22 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
It's 10us for gen 11.
Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84a5b13fdee2..1edd1445ab5b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3711,11 +3711,18 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
struct intel_crtc_state *cstate;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
+ int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
+ if (IS_GEN9(dev_priv))
+ sagv_block_time_us = 30;
+ else if (IS_GEN10(dev_priv))
+ sagv_block_time_us = 20;
+ else
+ sagv_block_time_us = 10;
+
/*
* SKL+ workaround: bspec recommends we disable the SAGV when we have
* more then one pipe enabled
--
2.14.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (14 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-25 23:09 ` James Ausmus
2018-01-29 22:07 ` Paulo Zanoni
2018-01-23 19:05 ` [PATCH 17/17] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field Paulo Zanoni
` (6 subsequent siblings)
22 siblings, 2 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Enable SAGV for ICL platform.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1edd1445ab5b..dedc76781524 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3605,7 +3605,7 @@ static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
- IS_CANNONLAKE(dev_priv))
+ IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv))
return true;
if (IS_SKYLAKE(dev_priv) &&
--
2.14.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 17/17] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (15 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform Paulo Zanoni
@ 2018-01-23 19:05 ` Paulo Zanoni
2018-01-23 19:32 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits Patchwork
` (5 subsequent siblings)
22 siblings, 0 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-23 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: James Ausmus <james.ausmus@intel.com>
ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values. Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.
v2: No changes
v3: Change new definition name, drop comment (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_display.c | 5 ++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cb77cd18cdb..1218a6a88cd8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6372,6 +6372,11 @@ enum {
#define _PLANE_CTL_3_A 0x70380
#define PLANE_CTL_ENABLE (1 << 31)
#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
#define PLANE_CTL_FORMAT_MASK (0xf << 24)
#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
@@ -6381,6 +6386,7 @@ enum {
#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
+#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3eb2359c221b..7d5362e8bc3d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8516,7 +8516,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
val = I915_READ(PLANE_CTL(pipe, plane_id));
- pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ if (INTEL_GEN(dev_priv) >= 11)
+ pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+ else
+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (16 preceding siblings ...)
2018-01-23 19:05 ` [PATCH 17/17] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field Paulo Zanoni
@ 2018-01-23 19:32 ` Patchwork
2018-01-23 20:32 ` Patchwork
` (4 subsequent siblings)
22 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-01-23 19:32 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL display initialization and some plane bits
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v1 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a-frame-sequence:
pass -> FAIL (fi-skl-6700k2) fdo#103191 +2
Subgroup suspend-read-crc-pipe-a:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6700hq) fdo#101144 +2
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
Subgroup suspend-read-crc-pipe-b:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-6260u) fdo#104108 +3
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:429s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:428s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:370s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:482s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s
fi-bxt-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:479s
fi-bxt-j4205 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:29 time:486s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:470s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:463s
fi-elk-e7500 total:224 pass:168 dwarn:9 dfail:1 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:280s
fi-glk-1 total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:517s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:390s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:412s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:414s
fi-kbl-7500u total:288 pass:260 dwarn:1 dfail:0 fail:3 skip:24 time:456s
fi-kbl-7560u total:288 pass:266 dwarn:0 dfail:0 fail:3 skip:19 time:510s
fi-kbl-7567u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:11 time:449s
fi-kbl-r total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:506s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:575s
fi-skl-6260u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:427s
fi-skl-6600u total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:519s
fi-skl-6700hq total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:547s
fi-skl-6700k2 total:288 pass:260 dwarn:0 dfail:0 fail:4 skip:24 time:498s
fi-skl-6770hq total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:477s
fi-skl-guc total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:410s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:536s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:577s
fi-glk-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:473s
5e022f5f329c7909cb9aa938364072329f694fb2 drm-tip: 2018y-01m-23d-17h-29m-20s UTC integration manifest
b987150d1f3a drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
6ddb0e0a1b4d drm/i915/icl: enable SAGV for ICL platform
68909575c48e drm/i915/gen11: fix the SAGV block time for gen11
c495336199d8 drm/i915/icl: update ddb entry start/end mask during hw ddb readout
7d2419d11d88 drm/i915/icl: Enable 2nd DBuf slice only when needed
3ad2d2caa7f7 drm/i915/icl: track dbuf slice-2 status
7cf166c9cea0 drm/i915/icl: program mbus during pipe enable
22402be7f70b drm/i915/icl: initialize MBus during display init
e51c30ccb9c6 drm/i915/icl: Introduce MBus related registers
7c3d4d4a12be drm/i915/icl: NV12 y-plane ddb is not in same plane
8f654f544cdd drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
640cf35c24f2 drm/i915/icl: Do not fix dbuf block size to 512
17c9c1e34a3f drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
da74d1f015d4 drm/i915/icl: Enable both DBuf slices during init
c1fff61cf0ce drm/i915/icl: implement the display init/uninit sequences
62c283412f33 drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
01d8f0d2a637 drm/i915/icl: add the main CDCLK functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7756/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (17 preceding siblings ...)
2018-01-23 19:32 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits Patchwork
@ 2018-01-23 20:32 ` Patchwork
2018-01-29 23:27 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev2) Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-01-23 20:32 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL display initialization and some plane bits
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v1 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6700hq) fdo#101144 +2
pass -> FAIL (fi-skl-6700k2) fdo#103191 +1
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
Subgroup suspend-read-crc-pipe-b:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-6260u) fdo#104108 +3
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:418s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:424s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:371s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:486s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:480s
fi-bxt-j4205 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:29 time:486s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:469s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:454s
fi-elk-e7500 total:224 pass:168 dwarn:9 dfail:1 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:279s
fi-glk-1 total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:520s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:390s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:459s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:413s
fi-kbl-7500u total:288 pass:260 dwarn:1 dfail:0 fail:3 skip:24 time:455s
fi-kbl-7560u total:288 pass:266 dwarn:0 dfail:0 fail:3 skip:19 time:514s
fi-kbl-7567u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:11 time:447s
fi-kbl-r total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:516s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:594s
fi-skl-6260u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:429s
fi-skl-6600u total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:518s
fi-skl-6700hq total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:542s
fi-skl-6700k2 total:288 pass:261 dwarn:0 dfail:0 fail:3 skip:24 time:480s
fi-skl-6770hq total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:474s
fi-skl-guc total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:415s
fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:394s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:583s
fi-glk-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:469s
5e022f5f329c7909cb9aa938364072329f694fb2 drm-tip: 2018y-01m-23d-17h-29m-20s UTC integration manifest
df84cb2f24e1 drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
8b02c1cd070c drm/i915/icl: enable SAGV for ICL platform
ae6bfdf93539 drm/i915/gen11: fix the SAGV block time for gen11
974235ea9e66 drm/i915/icl: update ddb entry start/end mask during hw ddb readout
4d1c57f9c4a4 drm/i915/icl: Enable 2nd DBuf slice only when needed
2624a7ea4c39 drm/i915/icl: track dbuf slice-2 status
2a75b35da2dc drm/i915/icl: program mbus during pipe enable
a36f380a965f drm/i915/icl: initialize MBus during display init
867c7d7b04b3 drm/i915/icl: Introduce MBus related registers
f6961a6c4ecc drm/i915/icl: NV12 y-plane ddb is not in same plane
7bc0e65734a0 drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
817debbe5b68 drm/i915/icl: Do not fix dbuf block size to 512
e921a3f9fbfc drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
5a3b1075b2dd drm/i915/icl: Enable both DBuf slices during init
d37e59efc8ee drm/i915/icl: implement the display init/uninit sequences
0334952bb6d4 drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
ab5f7b82abf7 drm/i915/icl: add the main CDCLK functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7758/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
2018-01-23 19:05 ` [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Paulo Zanoni
@ 2018-01-24 0:32 ` James Ausmus
2018-01-26 20:24 ` Paulo Zanoni
2018-01-26 20:33 ` Ville Syrjälä
2018-02-02 16:23 ` Paulo Zanoni
2 siblings, 1 reply; 59+ messages in thread
From: James Ausmus @ 2018-01-24 0:32 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> On ICL we have two sets of registers: one for port A and another for
> port B. The set of port A registers is the same as the CNL registers.
>
> Since the procmon table on ICL is the same we want to reuse the CNL
> function. To do that we add a port argument and make CNL always call
> the function passing port A. This way, we'll be able to easily reuse
> the function on ICL when we add icl_display_core_init().
>
> v2: Don't use _PICK() when you can use a ternary operator.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++++++++++++++-------
> 2 files changed, 40 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d72e206b2b9f..ebf6261d30fd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2102,6 +2102,32 @@ enum i915_power_well_id {
> #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
>
> +#define _ICL_PORT_COMP_DW0_A 0x162100
> +#define _ICL_PORT_COMP_DW0_B 0x6C100
> +#define ICL_PORT_COMP_DW0(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW0_A : \
> + _ICL_PORT_COMP_DW0_B)
> +#define _ICL_PORT_COMP_DW1_A 0x162104
> +#define _ICL_PORT_COMP_DW1_B 0x6C104
> +#define ICL_PORT_COMP_DW1(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW1_A : \
> + _ICL_PORT_COMP_DW1_B)
> +#define _ICL_PORT_COMP_DW3_A 0x16210C
> +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> +#define ICL_PORT_COMP_DW3(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW3_A : \
> + _ICL_PORT_COMP_DW3_B)
> +#define _ICL_PORT_COMP_DW9_A 0x162124
> +#define _ICL_PORT_COMP_DW9_B 0x6C124
> +#define ICL_PORT_COMP_DW9(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW9_A : \
> + _ICL_PORT_COMP_DW9_B)
> +#define _ICL_PORT_COMP_DW10_A 0x162128
> +#define _ICL_PORT_COMP_DW10_B 0x6C128
> +#define ICL_PORT_COMP_DW10(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW10_A : \
> + _ICL_PORT_COMP_DW10_B)
> +
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
> #define _PORT_REF_DW3_BC 0x6C18C
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5b1aa4b9c72c..73dd525d241a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
> { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> };
>
> -static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> +/*
> + * CNL has just one set of registers, while ICL has two sets: one for port A and
> + * the other for port B. The CNL registers are equivalent to the ICL port A
> + * registers, that's why we call the ICL macros even though the function has CNL
> + * on its name.
> + */
> +static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
> + enum port port)
> {
> const struct cnl_procmon *procmon;
> u32 val;
>
> - val = I915_READ(CNL_PORT_COMP_DW3);
> + val = I915_READ(ICL_PORT_COMP_DW3(port));
> switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> default:
> MISSING_CASE(val);
> @@ -2784,13 +2791,13 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> break;
> }
>
> - val = I915_READ(CNL_PORT_COMP_DW1);
> + val = I915_READ(ICL_PORT_COMP_DW1(port));
> val &= ~((0xff << 16) | 0xff);
> val |= procmon->dw1;
> - I915_WRITE(CNL_PORT_COMP_DW1, val);
> + I915_WRITE(ICL_PORT_COMP_DW1(port), val);
>
> - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> }
>
> static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> @@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> val &= ~CNL_COMP_PWR_DOWN;
> I915_WRITE(CHICKEN_MISC_2, val);
>
> - cnl_set_procmon_ref_values(dev_priv);
> + cnl_set_procmon_ref_values(dev_priv, PORT_A);
Maybe worth a one-line comment here about why we're passing PORT_A so
drive-by readings don't get confused on why we're only setting PORT_A?
Maybe something like
/* Dummy PORT_A to get the correct CNL register from the ICL macro */
Either way:
Reviewed-by: James Ausmus <james.ausmus@intel.com>
>
> val = I915_READ(CNL_PORT_COMP_DW0);
> val |= COMP_INIT;
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init
2018-01-23 19:05 ` [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init Paulo Zanoni
@ 2018-01-24 0:49 ` James Ausmus
2018-01-26 20:50 ` Paulo Zanoni
0 siblings, 1 reply; 59+ messages in thread
From: James Ausmus @ 2018-01-24 0:49 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> ICL has 2 slices of DBuf, enable both the slices during display init.
>
> Ideally we should only enable the second slice when needed in order to
> save power, but while we're not there yet, adopt the simpler solution
> to keep us bug-free.
>
> v2 (from Paulo):
> - Add the TODO comment.
> - Reorganize where things are defined.
> - Fix indentation.
> - Remove unnecessary POSTING_READ() calls.
> - Improve the commit message.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++++++++++++++++--
> 2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 979bc06a59f4..1746df9a263d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7122,6 +7122,8 @@ enum {
> #define DISP_DATA_PARTITION_5_6 (1<<6)
> #define DISP_IPC_ENABLE (1<<3)
> #define DBUF_CTL _MMIO(0x45008)
> +#define DBUF_CTL_S1 _MMIO(0x45008)
Since it's the exact same register, is it really worth duplicating, or
should we just use the existing DBUF_CTL instead of adding DBUF_CTL_S1?
> +#define DBUF_CTL_S2 _MMIO(0x44FE8)
> #define DBUF_POWER_REQUEST (1<<31)
> #define DBUF_POWER_STATE (1<<30)
> #define GEN7_MSG_CTL _MMIO(0x45010)
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 2556db16c76a..7801a425398f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> DRM_ERROR("DBuf power disable timeout!\n");
> }
>
> +/*
> + * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
> + * needed and keep it disabled as much as possible.
> + */
> +static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> +{
> + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
> + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);
BSpec says to poll, and timeout/fail after 10 uS, rather than
unconditionally busy wait - worth making more complex to potentially
save a few uS of busy wait?
> +
> + if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> + !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> + DRM_ERROR("DBuf power enable timeout\n");
> +}
> +
> +static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> +{
> + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
> + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);
> +
> + if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> + (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> + DRM_ERROR("DBuf power disable timeout!\n");
> +}
> +
> static void skl_display_core_init(struct drm_i915_private *dev_priv,
> bool resume)
> {
> @@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> icl_init_cdclk(dev_priv);
>
> /* 6. Enable DBUF. */
> - gen9_dbuf_enable(dev_priv);
> + icl_dbuf_enable(dev_priv);
>
> /* 7. Setup MBUS. */
> /* FIXME: MBUS code not here yet. */
> @@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> /* 1. Disable all display engine functions -> aready done */
>
> /* 2. Disable DBUF */
> - gen9_dbuf_disable(dev_priv);
> + icl_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> icl_uninit_cdclk(dev_priv);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
2018-01-23 19:05 ` [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
@ 2018-01-24 0:58 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-24 0:58 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:24PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> GEN9 onwards bypass path allocation of 4 blocks was needed, as per
> hardware design. ICL doesn't require bypass path allocation of 4 DDB
> blocks, handling the same in this patch.
>
> v2 (from Paulo):
> - No need for a comment that says what the code already says.
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0b92ea1dbd40..11aac65d1543 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3778,7 +3778,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> WARN_ON(ddb_size == 0);
>
> - ddb_size -= 4; /* 4 blocks for bypass path allocation */
> + if (INTEL_GEN(dev_priv) < 11)
> + ddb_size -= 4; /* 4 blocks for bypass path allocation */
>
> /*
> * If the state doesn't change the active CRTC's, then there's
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512
2018-01-23 19:05 ` [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
@ 2018-01-24 1:14 ` James Ausmus
2018-01-29 23:07 ` Paulo Zanoni
1 sibling, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-24 1:14 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:25PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
> fixed number anymore in GEN11, it varies according to bits per pixel
> and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
> size = 512
>
> This patch addresses the same.
>
> v2 (from Paulo):
> - Make it compile.
> - Fix a few coding style issues.
> v3
> - Rebase on top of upstream patches
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++-------
> 2 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..cc5ac327f267 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1460,6 +1460,7 @@ struct skl_wm_params {
> uint_fixed_16_16_t plane_blocks_per_line;
> uint_fixed_16_16_t y_tile_minimum;
> uint32_t linetime_us;
> + uint32_t dbuf_block_size;
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 11aac65d1543..44d952a3d9a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> */
> static uint_fixed_16_16_t
> skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> - uint8_t cpp, uint32_t latency)
> + uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
> {
> uint32_t wm_intermediate_val;
> uint_fixed_16_16_t ret;
> @@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> return FP_16_16_MAX;
>
> wm_intermediate_val = latency * pixel_rate * cpp;
> - ret = div_fixed16(wm_intermediate_val, 1000 * 512);
> + ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>
> if (INTEL_GEN(dev_priv) >= 10)
> ret = add_fixed16_u32(ret, 1);
> @@ -4431,6 +4431,15 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
> intel_pstate);
>
> + if (INTEL_GEN(dev_priv) >= 11) {
> + if (fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
> + wp->dbuf_block_size = 256;
> + else
> + wp->dbuf_block_size = 512;
> + } else {
> + wp->dbuf_block_size = 512;
> + }
This could be simplified as (approximately)
wp->dbuf_block_size = 512;
if (INTEL_GEN(dev_priv) >= 11 && fb->modifier == I915_FORMAT_MOD_Yf_TILED &&
wp->cpp == 8)
wp->dbuf_block_size = 256;
> +
> if (drm_rotation_90_or_270(pstate->rotation)) {
>
> switch (wp->cpp) {
> @@ -4457,7 +4466,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->plane_bytes_per_line = wp->width * wp->cpp;
> if (wp->y_tiled) {
> interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
> - wp->y_min_scanlines, 512);
> + wp->y_min_scanlines,
> + wp->dbuf_block_size);
>
> if (INTEL_GEN(dev_priv) >= 10)
> interm_pbpl++;
> @@ -4465,10 +4475,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
> wp->y_min_scanlines);
> } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> + wp->dbuf_block_size);
> wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> } else {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> + wp->dbuf_block_size) + 1;
> wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> }
>
> @@ -4515,7 +4527,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> latency += 15;
>
> method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> - wp->cpp, latency);
> + wp->cpp, latency, wp->dbuf_block_size);
> method2 = skl_wm_method2(wp->plane_pixel_rate,
> cstate->base.adjusted_mode.crtc_htotal,
> latency,
> @@ -4525,7 +4537,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> selected_result = max_fixed16(method2, wp->y_tile_minimum);
> } else {
> if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
> - 512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
> + wp->dbuf_block_size < 1) &&
> + (wp->plane_bytes_per_line / wp->dbuf_block_size < 1))
> selected_result = method2;
> else if (ddb_allocation >=
> fixed16_to_u32_round_up(wp->plane_blocks_per_line))
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane
2018-01-23 19:05 ` [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
@ 2018-01-25 22:31 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 22:31 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:27PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> We don't have planar pixel format support implemented for ICL yet.
> ICL require 2 display planes to be allocated for Planar formats unlike
> previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
> NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in ICL.
>
> This patch removes the PLANE_NV12_BUF_CFG write for ICL.
>
> Changes Since V1:
> - Improve commit message as per Paulo's comment
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c6d31a5075ad..0237362ccf83 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4832,8 +4832,10 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
>
> skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> &ddb->plane[pipe][plane_id]);
> - skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
> - &ddb->y_plane[pipe][plane_id]);
> + if (INTEL_GEN(dev_priv) < 11)
> + skl_ddb_entry_write(dev_priv,
> + PLANE_NV12_BUF_CFG(pipe, plane_id),
> + &ddb->y_plane[pipe][plane_id]);
> }
>
> static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 09/17] drm/i915/icl: Introduce MBus related registers
2018-01-23 19:05 ` [PATCH 09/17] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
@ 2018-01-25 22:38 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 22:38 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:28PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This patch introduce MBus control registers and their bit-fields
> MBUS_ABOX_CTL
> MBUS_BBOX_CTL
> MBUS_DBOX_CTL
> MBUS_UBOX_CTL
>
> Changes Since V1:
> - Use function like macros (Paulo)
> - fix copy-paste error (Paulo)
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1746df9a263d..0cb77cd18cdb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2679,6 +2679,31 @@ enum i915_power_well_id {
> #define LM_FIFO_WATERMARK 0x0000001F
> #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
>
> +#define MBUS_ABOX_CTL _MMIO(0x45038)
> +#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
> +#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
> +#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
> +#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
> +#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
> +#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
> +#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
> +#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
> +
> +#define _PIPEA_MBUS_DBOX_CTL 0x7003C
> +#define _PIPEB_MBUS_DBOX_CTL 0x7103C
> +#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
> + _PIPEB_MBUS_DBOX_CTL)
> +#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
> +#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
> +#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
> +#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
> +#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
> +#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
> +
> +#define MBUS_UBOX_CTL _MMIO(0x4503C)
> +#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
> +#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
> +
> /* Make render/texture TLB fetches lower priorty than associated data
> * fetches. This is not turned on by default
> */
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 10/17] drm/i915/icl: initialize MBus during display init
2018-01-23 19:05 ` [PATCH 10/17] drm/i915/icl: initialize MBus during display init Paulo Zanoni
@ 2018-01-25 22:39 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 22:39 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:29PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This patch initializes MBus during display initialization.
>
> Changes since V2 (from Paulo):
> - Don't forget to remove the WARN_ON(1) call.
> Changes since V1:
> - Rebase to use function like Macros
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 7801a425398f..a6ed01a528bd 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2640,6 +2640,18 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> DRM_ERROR("DBuf power disable timeout!\n");
> }
>
> +static void icl_mbus_init(struct drm_i915_private *dev_priv)
> +{
> + uint32_t val;
> +
> + val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
> + MBUS_ABOX_BT_CREDIT_POOL2(16) |
> + MBUS_ABOX_B_CREDIT(1) |
> + MBUS_ABOX_BW_CREDIT(1);
> +
> + I915_WRITE(MBUS_ABOX_CTL, val);
> +}
> +
> static void skl_display_core_init(struct drm_i915_private *dev_priv,
> bool resume)
> {
> @@ -2953,7 +2965,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> icl_dbuf_enable(dev_priv);
>
> /* 7. Setup MBUS. */
> - /* FIXME: MBUS code not here yet. */
> + icl_mbus_init(dev_priv);
>
> /* 8. CHICKEN_DCPR_1 */
> I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> --
> 2.14.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 11/17] drm/i915/icl: program mbus during pipe enable
2018-01-23 19:05 ` [PATCH 11/17] drm/i915/icl: program mbus during pipe enable Paulo Zanoni
@ 2018-01-25 22:42 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 22:42 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:30PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This patch program default values of MBus credit during pipe enable.
>
> Changes since V2:
> - We don't need to do anything when disabling the pipe
> Changes Since V1:
> - Add WARN_ON (Paulo)
> - Remove TODO comment
> - Program 0 during pipe disable
> - Rebase
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d585ce4c8732..0dc4ef6cd46e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5380,6 +5380,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
> I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
> }
>
> +static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + uint32_t val;
> +
> + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
> + return;
> +
> + val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
> +
> + /* Program B credit equally to all pipes */
> + val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
> +
> + I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> +}
> +
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct drm_atomic_state *old_state)
> {
> @@ -5457,6 +5474,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (dev_priv->display.initial_watermarks != NULL)
> dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_pipe_mbus_enable(intel_crtc);
> +
> /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_enable_pipe(pipe_config);
> --
> 2.14.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed
2018-01-23 19:05 ` [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed Paulo Zanoni
@ 2018-01-25 22:56 ` James Ausmus
2018-03-14 16:19 ` [PATCH 2/2] " Mahesh Kumar
1 sibling, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 22:56 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:32PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> ICL has two slices of DBuf, each slice of size 1024 blocks.
> We should not always enable slice-2. It should be enabled only if
> display total required BW is > 12GBps OR more than 1 pipes are enabled.
>
> Changes since V1:
> - typecast total_data_rate to u64 before multiplication to solve any
> possible overflow (Rodrigo)
> - fix where skl_wm_get_hw_state was memsetting ddb, resulting
> enabled_slices to become zero
> - Fix the logic of calculating ddb_size
> Changes since V2:
> - If no-crtc is part of commit required_slices will have value "0",
> don't try to disable DBuf slice.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 +++++++
> drivers/gpu/drm/i915/intel_drv.h | 6 ++++
> drivers/gpu/drm/i915/intel_pm.c | 64 +++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_runtime_pm.c | 47 +++++++++++++++++++++---
> 4 files changed, 110 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bad3b112ac3e..3eb2359c221b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12117,6 +12117,8 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
> bool progress;
> enum pipe pipe;
> int i;
> + uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> + uint8_t required_slices = intel_state->wm_results.ddb.enabled_slices;
>
> const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
>
> @@ -12125,6 +12127,11 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
> if (new_crtc_state->active)
> entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
>
> + /* If 2nd DBuf slice required, enable it here */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
> + required_slices > hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
> +
> /*
> * Whenever the number of active pipes changes, we need to make sure we
> * update the pipes in the right order so that their ddb allocations
> @@ -12175,6 +12182,11 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
> progress = true;
> }
> } while (progress);
> +
> + /* If 2nd DBuf slice is no more required disable it */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
> + required_slices < hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
> }
>
> static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c5d6092aca41..d4639a161fe3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -140,6 +140,10 @@
> #define KHz(x) (1000 * (x))
> #define MHz(x) KHz(1000 * (x))
>
> +#define KBps(x) (1000 * (x))
> +#define MBps(x) KBps(1000 * (x))
> +#define GBps(x) ((uint64_t) 1000 * MBps((x)))
> +
> /*
> * Display related stuff
> */
> @@ -1890,6 +1894,8 @@ bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
> enum intel_display_power_domain domain);
> void intel_display_power_put(struct drm_i915_private *dev_priv,
> enum intel_display_power_domain domain);
> +void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> + uint8_t req_slices);
>
> static inline void
> assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e8d98857c208..d4cd631377da 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3767,9 +3767,42 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
> return true;
> }
>
> +static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
> + const struct intel_crtc_state *cstate,
> + const unsigned int total_data_rate,
> + const int num_active,
> + struct skl_ddb_allocation *ddb)
> +{
> + const struct drm_display_mode *adjusted_mode;
> + u64 total_data_bw;
> + u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> +
> + WARN_ON(ddb_size == 0);
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return ddb_size - 4; /* 4 blocks for bypass path allocation */
> +
> + adjusted_mode = &cstate->base.adjusted_mode;
> + total_data_bw = (u64)total_data_rate * drm_mode_vrefresh(adjusted_mode);
> +
> + /*
> + * 12GB/s is maximum BW supported by single DBuf slice.
> + */
> + if (total_data_bw >= GBps(12) || num_active > 1)
> + ddb->enabled_slices = 2;
> + else {
> + ddb->enabled_slices = 1;
> + ddb_size /= 2;
> + }
> +
> + return ddb_size;
> +}
> +
> static void
> skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> const struct intel_crtc_state *cstate,
> + const unsigned int total_data_rate,
> + struct skl_ddb_allocation *ddb,
> struct skl_ddb_entry *alloc, /* out */
> int *num_active /* out */)
> {
> @@ -3792,11 +3825,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> else
> *num_active = hweight32(dev_priv->active_crtcs);
>
> - ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> - WARN_ON(ddb_size == 0);
> -
> - if (INTEL_GEN(dev_priv) < 11)
> - ddb_size -= 4; /* 4 blocks for bypass path allocation */
> + ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,
> + *num_active, ddb);
>
> /*
> * If the state doesn't change the active CRTC's, then there's
> @@ -4235,7 +4265,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> return 0;
> }
>
> - skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
> + total_data_rate = skl_get_total_relative_data_rate(cstate,
> + plane_data_rate,
> + plane_y_data_rate);
> + if (total_data_rate == 0)
> + return 0;
> +
> + skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,
> + alloc, &num_active);
> alloc_size = skl_ddb_entry_size(alloc);
> if (alloc_size == 0)
> return 0;
> @@ -4270,12 +4307,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> *
> * FIXME: we may not allocate every single block here.
> */
> - total_data_rate = skl_get_total_relative_data_rate(cstate,
> - plane_data_rate,
> - plane_y_data_rate);
> - if (total_data_rate == 0)
> - return 0;
> -
> start = alloc->start;
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> unsigned int data_rate, y_data_rate;
> @@ -5068,7 +5099,6 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
> sizeof(dst->ddb.y_plane[pipe]));
> memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
> sizeof(dst->ddb.plane[pipe]));
> - dst->ddb.enabled_slices = src->ddb.enabled_slices;
> }
>
> static void
> @@ -5381,8 +5411,12 @@ void skl_wm_get_hw_state(struct drm_device *dev)
> /* Fully recompute DDB on first atomic commit */
> dev_priv->wm.distrust_bios_wm = true;
> } else {
> - /* Easy/common case; just sanitize DDB now if everything off */
> - memset(ddb, 0, sizeof(*ddb));
> + /*
> + * Easy/common case; just sanitize DDB now if everything off
> + * Keep dbuf slice info intact
> + */
> + memset(ddb->plane, 0, sizeof(ddb->plane));
> + memset(ddb->y_plane, 0, sizeof(ddb->y_plane));
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 13c8dad95b84..a67a57738740 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2610,10 +2610,49 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> DRM_ERROR("DBuf power disable timeout!\n");
> }
>
> -/*
> - * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
> - * needed and keep it disabled as much as possible.
> - */
> +static uint8_t intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
> +{
> + if (INTEL_GEN(dev_priv) < 11)
> + return 1;
> + return 2;
> +}
> +
> +void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> + uint8_t req_slices)
> +{
> + uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> + u32 val;
> +
> + if (req_slices > intel_dbuf_max_slices(dev_priv)) {
> + DRM_ERROR("Invalid number of dbuf slices requested\n");
> + return;
> + }
> +
> + if (req_slices == hw_enabled_slices)
> + return;
> +
> + val = I915_READ(DBUF_CTL_S2);
> + if (req_slices > hw_enabled_slices) {
> + I915_WRITE(DBUF_CTL_S2, val | DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);
> + if (!(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> + DRM_ERROR("DBuf power enable timeout\n");
> + else
> + dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
> + } else {
> + I915_WRITE(DBUF_CTL_S2, val & ~DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);
> + if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
> + DRM_ERROR("DBuf power disable timeout!\n");
> + else
> + dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
It feels a little ugly to be duplicating the Write->Posting
Read->Wait->Read->Error pattern across this function and
icl_dbuf_enable/disable below - not to mention that we have the same
pattern up above in gen9_dbuf_enable/disable. Maybe we should refactor
the gen9 versions in to helpers that take a slice number, and then reuse
those for ICL as well?
> + }
> +}
> +
> static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> {
> I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout
2018-01-23 19:05 ` [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout Paulo Zanoni
@ 2018-01-25 23:00 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 23:00 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:33PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
> 11 bits. This patch make changes to use proper mask for ICL+ during
> hardware ddb value readout.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d4cd631377da..84a5b13fdee2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3860,10 +3860,18 @@ static unsigned int skl_cursor_allocation(int num_active)
> return 8;
> }
>
> -static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> +static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> + struct skl_ddb_entry *entry, u32 reg)
> {
> - entry->start = reg & 0x3ff;
> - entry->end = (reg >> 16) & 0x3ff;
> + uint16_t mask;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + mask = 0x7ff;
> + else
> + mask = 0x3ff;
> + entry->start = reg & mask;
> + entry->end = (reg >> 16) & mask;
Should these be turned in to _MASK and _SHIFT defines?
> +
> if (entry->end)
> entry->end += 1;
> }
> @@ -3894,7 +3902,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> else
> val = I915_READ(CUR_BUF_CFG(pipe));
>
> - skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> + skl_ddb_entry_init_from_hw(dev_priv,
> + &ddb->plane[pipe][plane_id],
> + val);
> }
>
> intel_display_power_put(dev_priv, power_domain);
> --
> 2.14.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status
2018-01-23 19:05 ` [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status Paulo Zanoni
@ 2018-01-25 23:08 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 23:08 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:31PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This patch adds support to start tracking status of DBUF slices.
> This is foundation to introduce support for enabling/disabling second
> DBUF slice dynamically for ICL.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 5 +++++
> drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++++
> 4 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cc5ac327f267..eae18661eaec 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1435,6 +1435,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
> struct skl_ddb_allocation {
> struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
> struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> + uint8_t enabled_slices; /* GEN11 has configurable 2 slices */
> };
>
> struct skl_wm_values {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0dc4ef6cd46e..bad3b112ac3e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11302,6 +11302,11 @@ static void verify_wm_state(struct drm_crtc *crtc,
> skl_ddb_get_hw_state(dev_priv, &hw_ddb);
> sw_ddb = &dev_priv->wm.skl_hw.ddb;
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
> + DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
> + sw_ddb->enabled_slices,
> + hw_ddb.enabled_slices);
> /* planes */
> for_each_universal_plane(dev_priv, pipe, plane) {
> hw_plane_wm = &hw_wm.planes[plane];
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0237362ccf83..e8d98857c208 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3570,6 +3570,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
> return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
> }
>
> +static uint8_t intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
> +{
> + uint8_t enabled_slices;
> +
> + /* Slice 1 will always be enabled */
> + enabled_slices = 1;
> +
> + /* Gen prior to GEN11 have only one DBuf slice */
> + if (INTEL_GEN(dev_priv) < 11)
> + return enabled_slices;
> +
> + if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
> + enabled_slices++;
> +
> + return enabled_slices;
> +}
> +
> /*
> * FIXME: We still don't have the proper code detect if we need to apply the WA,
> * so assume we'll always need it in order to avoid underruns.
> @@ -3828,6 +3845,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>
> memset(ddb, 0, sizeof(*ddb));
>
> + ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> +
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> enum intel_display_power_domain power_domain;
> enum plane_id plane_id;
> @@ -5049,6 +5068,7 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
> sizeof(dst->ddb.y_plane[pipe]));
> memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
> sizeof(dst->ddb.plane[pipe]));
> + dst->ddb.enabled_slices = src->ddb.enabled_slices;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index a6ed01a528bd..13c8dad95b84 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2625,6 +2625,8 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> DRM_ERROR("DBuf power enable timeout\n");
> + else
> + dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
> }
>
> static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> @@ -2638,6 +2640,8 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> DRM_ERROR("DBuf power disable timeout!\n");
> + else
> + dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
> }
>
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11
2018-01-23 19:05 ` [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
@ 2018-01-25 23:09 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 23:09 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:34PM -0200, Paulo Zanoni wrote:
> It's 10us for gen 11.
>
> Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 84a5b13fdee2..1edd1445ab5b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3711,11 +3711,18 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
> struct intel_crtc_state *cstate;
> enum pipe pipe;
> int level, latency;
> - int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
> + int sagv_block_time_us;
>
> if (!intel_has_sagv(dev_priv))
> return false;
>
> + if (IS_GEN9(dev_priv))
> + sagv_block_time_us = 30;
> + else if (IS_GEN10(dev_priv))
> + sagv_block_time_us = 20;
> + else
> + sagv_block_time_us = 10;
> +
> /*
> * SKL+ workaround: bspec recommends we disable the SAGV when we have
> * more then one pipe enabled
> --
> 2.14.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform
2018-01-23 19:05 ` [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform Paulo Zanoni
@ 2018-01-25 23:09 ` James Ausmus
2018-01-29 22:07 ` Paulo Zanoni
1 sibling, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-25 23:09 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:35PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> Enable SAGV for ICL platform.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1edd1445ab5b..dedc76781524 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3605,7 +3605,7 @@ static bool
> intel_has_sagv(struct drm_i915_private *dev_priv)
> {
> if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> - IS_CANNONLAKE(dev_priv))
> + IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv))
> return true;
>
> if (IS_SKYLAKE(dev_priv) &&
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
2018-01-24 0:32 ` James Ausmus
@ 2018-01-26 20:24 ` Paulo Zanoni
2018-01-26 20:47 ` James Ausmus
0 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-26 20:24 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
Em Ter, 2018-01-23 às 16:32 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> > On ICL we have two sets of registers: one for port A and another
> > for
> > port B. The set of port A registers is the same as the CNL
> > registers.
> >
> > Since the procmon table on ICL is the same we want to reuse the CNL
> > function. To do that we add a port argument and make CNL always
> > call
> > the function passing port A. This way, we'll be able to easily
> > reuse
> > the function on ICL when we add icl_display_core_init().
> >
> > v2: Don't use _PICK() when you can use a ternary operator.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 26
> > ++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++++++++++++++-------
> > 2 files changed, 40 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index d72e206b2b9f..ebf6261d30fd 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2102,6 +2102,32 @@ enum i915_power_well_id {
> > #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> > #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
> >
> > +#define _ICL_PORT_COMP_DW0_A 0x162100
> > +#define _ICL_PORT_COMP_DW0_B 0x6C100
> > +#define ICL_PORT_COMP_DW0(port) _MMIO((port ==
> > PORT_A) ? \
> > + _ICL_PORT_COMP_DW0_A
> > : \
> > + _ICL_PORT_COMP_DW0_B
> > )
> > +#define _ICL_PORT_COMP_DW1_A 0x162104
> > +#define _ICL_PORT_COMP_DW1_B 0x6C104
> > +#define ICL_PORT_COMP_DW1(port) _MMIO((port ==
> > PORT_A) ? \
> > + _ICL_PORT_COMP_DW1_A
> > : \
> > + _ICL_PORT_COMP_DW1_B
> > )
> > +#define _ICL_PORT_COMP_DW3_A 0x16210C
> > +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> > +#define ICL_PORT_COMP_DW3(port) _MMIO((port ==
> > PORT_A) ? \
> > + _ICL_PORT_COMP_DW3_A
> > : \
> > + _ICL_PORT_COMP_DW3_B
> > )
> > +#define _ICL_PORT_COMP_DW9_A 0x162124
> > +#define _ICL_PORT_COMP_DW9_B 0x6C124
> > +#define ICL_PORT_COMP_DW9(port) _MMIO((port ==
> > PORT_A) ? \
> > + _ICL_PORT_COMP_DW9_A
> > : \
> > + _ICL_PORT_COMP_DW9_B
> > )
> > +#define _ICL_PORT_COMP_DW10_A 0x162128
> > +#define _ICL_PORT_COMP_DW10_B 0x6C128
> > +#define ICL_PORT_COMP_DW10(port) _MMIO((port == PORT_A) ?
> > \
> > + _ICL_PORT_COMP_DW10_
> > A : \
> > + _ICL_PORT_COMP_DW10_
> > B)
> > +
> > /* BXT PHY Ref registers */
> > #define _PORT_REF_DW3_A 0x16218C
> > #define _PORT_REF_DW3_BC 0x6C18C
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 5b1aa4b9c72c..73dd525d241a 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
> > { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 =
> > 0x8AE38FF1, },
> > };
> >
> > -static void cnl_set_procmon_ref_values(struct drm_i915_private
> > *dev_priv)
> > +/*
> > + * CNL has just one set of registers, while ICL has two sets: one
> > for port A and
> > + * the other for port B. The CNL registers are equivalent to the
> > ICL port A
> > + * registers, that's why we call the ICL macros even though the
> > function has CNL
> > + * on its name.
> > + */
My reply below refers to this comment here ^.
> > +static void cnl_set_procmon_ref_values(struct drm_i915_private
> > *dev_priv,
> > + enum port port)
> > {
> > const struct cnl_procmon *procmon;
> > u32 val;
> >
> > - val = I915_READ(CNL_PORT_COMP_DW3);
> > + val = I915_READ(ICL_PORT_COMP_DW3(port));
> > switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> > default:
> > MISSING_CASE(val);
> > @@ -2784,13 +2791,13 @@ static void
> > cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> > break;
> > }
> >
> > - val = I915_READ(CNL_PORT_COMP_DW1);
> > + val = I915_READ(ICL_PORT_COMP_DW1(port));
> > val &= ~((0xff << 16) | 0xff);
> > val |= procmon->dw1;
> > - I915_WRITE(CNL_PORT_COMP_DW1, val);
> > + I915_WRITE(ICL_PORT_COMP_DW1(port), val);
> >
> > - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> > - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> > + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> > + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> > }
> >
> > static void cnl_display_core_init(struct drm_i915_private
> > *dev_priv, bool resume)
> > @@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct
> > drm_i915_private *dev_priv, bool resume
> > val &= ~CNL_COMP_PWR_DOWN;
> > I915_WRITE(CHICKEN_MISC_2, val);
> >
> > - cnl_set_procmon_ref_values(dev_priv);
> > + cnl_set_procmon_ref_values(dev_priv, PORT_A);
>
> Maybe worth a one-line comment here about why we're passing PORT_A so
> drive-by readings don't get confused on why we're only setting
> PORT_A?
>
> Maybe something like
>
> /* Dummy PORT_A to get the correct CNL register from the ICL macro */
I put such comment at the beginning of the function. See above. Is that
enough or you think we also need this extra comment?
>
> Either way:
>
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
Thanks!
>
> >
> > val = I915_READ(CNL_PORT_COMP_DW0);
> > val |= COMP_INIT;
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
2018-01-23 19:05 ` [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Paulo Zanoni
2018-01-24 0:32 ` James Ausmus
@ 2018-01-26 20:33 ` Ville Syrjälä
2018-02-02 16:23 ` Paulo Zanoni
2 siblings, 0 replies; 59+ messages in thread
From: Ville Syrjälä @ 2018-01-26 20:33 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> On ICL we have two sets of registers: one for port A and another for
> port B. The set of port A registers is the same as the CNL registers.
>
> Since the procmon table on ICL is the same we want to reuse the CNL
> function. To do that we add a port argument and make CNL always call
> the function passing port A. This way, we'll be able to easily reuse
> the function on ICL when we add icl_display_core_init().
>
> v2: Don't use _PICK() when you can use a ternary operator.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++++++++++++++-------
> 2 files changed, 40 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d72e206b2b9f..ebf6261d30fd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2102,6 +2102,32 @@ enum i915_power_well_id {
> #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
>
> +#define _ICL_PORT_COMP_DW0_A 0x162100
> +#define _ICL_PORT_COMP_DW0_B 0x6C100
> +#define ICL_PORT_COMP_DW0(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW0_A : \
> + _ICL_PORT_COMP_DW0_B)
Why not just _MMIO_PORT() ?
> +#define _ICL_PORT_COMP_DW1_A 0x162104
> +#define _ICL_PORT_COMP_DW1_B 0x6C104
> +#define ICL_PORT_COMP_DW1(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW1_A : \
> + _ICL_PORT_COMP_DW1_B)
> +#define _ICL_PORT_COMP_DW3_A 0x16210C
> +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> +#define ICL_PORT_COMP_DW3(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW3_A : \
> + _ICL_PORT_COMP_DW3_B)
> +#define _ICL_PORT_COMP_DW9_A 0x162124
> +#define _ICL_PORT_COMP_DW9_B 0x6C124
> +#define ICL_PORT_COMP_DW9(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW9_A : \
> + _ICL_PORT_COMP_DW9_B)
> +#define _ICL_PORT_COMP_DW10_A 0x162128
> +#define _ICL_PORT_COMP_DW10_B 0x6C128
> +#define ICL_PORT_COMP_DW10(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_COMP_DW10_A : \
> + _ICL_PORT_COMP_DW10_B)
> +
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
> #define _PORT_REF_DW3_BC 0x6C18C
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5b1aa4b9c72c..73dd525d241a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
> { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> };
>
> -static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> +/*
> + * CNL has just one set of registers, while ICL has two sets: one for port A and
> + * the other for port B. The CNL registers are equivalent to the ICL port A
> + * registers, that's why we call the ICL macros even though the function has CNL
> + * on its name.
> + */
> +static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
> + enum port port)
> {
> const struct cnl_procmon *procmon;
> u32 val;
>
> - val = I915_READ(CNL_PORT_COMP_DW3);
> + val = I915_READ(ICL_PORT_COMP_DW3(port));
> switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> default:
> MISSING_CASE(val);
> @@ -2784,13 +2791,13 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> break;
> }
>
> - val = I915_READ(CNL_PORT_COMP_DW1);
> + val = I915_READ(ICL_PORT_COMP_DW1(port));
> val &= ~((0xff << 16) | 0xff);
> val |= procmon->dw1;
> - I915_WRITE(CNL_PORT_COMP_DW1, val);
> + I915_WRITE(ICL_PORT_COMP_DW1(port), val);
>
> - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> }
>
> static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> @@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> val &= ~CNL_COMP_PWR_DOWN;
> I915_WRITE(CHICKEN_MISC_2, val);
>
> - cnl_set_procmon_ref_values(dev_priv);
> + cnl_set_procmon_ref_values(dev_priv, PORT_A);
>
> val = I915_READ(CNL_PORT_COMP_DW0);
> val |= COMP_INIT;
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
2018-01-26 20:24 ` Paulo Zanoni
@ 2018-01-26 20:47 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-26 20:47 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Fri, Jan 26, 2018 at 06:24:32PM -0200, Paulo Zanoni wrote:
> Em Ter, 2018-01-23 às 16:32 -0800, James Ausmus escreveu:
> > On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> > > On ICL we have two sets of registers: one for port A and another
> > > for
> > > port B. The set of port A registers is the same as the CNL
> > > registers.
> > >
> > > Since the procmon table on ICL is the same we want to reuse the CNL
> > > function. To do that we add a port argument and make CNL always
> > > call
> > > the function passing port A. This way, we'll be able to easily
> > > reuse
> > > the function on ICL when we add icl_display_core_init().
> > >
> > > v2: Don't use _PICK() when you can use a ternary operator.
> > >
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 26
> > > ++++++++++++++++++++++++++
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++++++++++++++-------
> > > 2 files changed, 40 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index d72e206b2b9f..ebf6261d30fd 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -2102,6 +2102,32 @@ enum i915_power_well_id {
> > > #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> > > #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
> > >
> > > +#define _ICL_PORT_COMP_DW0_A 0x162100
> > > +#define _ICL_PORT_COMP_DW0_B 0x6C100
> > > +#define ICL_PORT_COMP_DW0(port) _MMIO((port ==
> > > PORT_A) ? \
> > > + _ICL_PORT_COMP_DW0_A
> > > : \
> > > + _ICL_PORT_COMP_DW0_B
> > > )
> > > +#define _ICL_PORT_COMP_DW1_A 0x162104
> > > +#define _ICL_PORT_COMP_DW1_B 0x6C104
> > > +#define ICL_PORT_COMP_DW1(port) _MMIO((port ==
> > > PORT_A) ? \
> > > + _ICL_PORT_COMP_DW1_A
> > > : \
> > > + _ICL_PORT_COMP_DW1_B
> > > )
> > > +#define _ICL_PORT_COMP_DW3_A 0x16210C
> > > +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> > > +#define ICL_PORT_COMP_DW3(port) _MMIO((port ==
> > > PORT_A) ? \
> > > + _ICL_PORT_COMP_DW3_A
> > > : \
> > > + _ICL_PORT_COMP_DW3_B
> > > )
> > > +#define _ICL_PORT_COMP_DW9_A 0x162124
> > > +#define _ICL_PORT_COMP_DW9_B 0x6C124
> > > +#define ICL_PORT_COMP_DW9(port) _MMIO((port ==
> > > PORT_A) ? \
> > > + _ICL_PORT_COMP_DW9_A
> > > : \
> > > + _ICL_PORT_COMP_DW9_B
> > > )
> > > +#define _ICL_PORT_COMP_DW10_A 0x162128
> > > +#define _ICL_PORT_COMP_DW10_B 0x6C128
> > > +#define ICL_PORT_COMP_DW10(port) _MMIO((port == PORT_A) ?
> > > \
> > > + _ICL_PORT_COMP_DW10_
> > > A : \
> > > + _ICL_PORT_COMP_DW10_
> > > B)
> > > +
> > > /* BXT PHY Ref registers */
> > > #define _PORT_REF_DW3_A 0x16218C
> > > #define _PORT_REF_DW3_BC 0x6C18C
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 5b1aa4b9c72c..73dd525d241a 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
> > > { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 =
> > > 0x8AE38FF1, },
> > > };
> > >
> > > -static void cnl_set_procmon_ref_values(struct drm_i915_private
> > > *dev_priv)
> > > +/*
> > > + * CNL has just one set of registers, while ICL has two sets: one
> > > for port A and
> > > + * the other for port B. The CNL registers are equivalent to the
> > > ICL port A
> > > + * registers, that's why we call the ICL macros even though the
> > > function has CNL
> > > + * on its name.
> > > + */
>
> My reply below refers to this comment here ^.
>
>
>
>
> > > +static void cnl_set_procmon_ref_values(struct drm_i915_private
> > > *dev_priv,
> > > + enum port port)
> > > {
> > > const struct cnl_procmon *procmon;
> > > u32 val;
> > >
> > > - val = I915_READ(CNL_PORT_COMP_DW3);
> > > + val = I915_READ(ICL_PORT_COMP_DW3(port));
> > > switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> > > default:
> > > MISSING_CASE(val);
> > > @@ -2784,13 +2791,13 @@ static void
> > > cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> > > break;
> > > }
> > >
> > > - val = I915_READ(CNL_PORT_COMP_DW1);
> > > + val = I915_READ(ICL_PORT_COMP_DW1(port));
> > > val &= ~((0xff << 16) | 0xff);
> > > val |= procmon->dw1;
> > > - I915_WRITE(CNL_PORT_COMP_DW1, val);
> > > + I915_WRITE(ICL_PORT_COMP_DW1(port), val);
> > >
> > > - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> > > - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> > > + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> > > + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> > > }
> > >
> > > static void cnl_display_core_init(struct drm_i915_private
> > > *dev_priv, bool resume)
> > > @@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct
> > > drm_i915_private *dev_priv, bool resume
> > > val &= ~CNL_COMP_PWR_DOWN;
> > > I915_WRITE(CHICKEN_MISC_2, val);
> > >
> > > - cnl_set_procmon_ref_values(dev_priv);
> > > + cnl_set_procmon_ref_values(dev_priv, PORT_A);
> >
> > Maybe worth a one-line comment here about why we're passing PORT_A so
> > drive-by readings don't get confused on why we're only setting
> > PORT_A?
> >
> > Maybe something like
> >
> > /* Dummy PORT_A to get the correct CNL register from the ICL macro */
>
> I put such comment at the beginning of the function. See above. Is that
> enough or you think we also need this extra comment?
Yeah, I saw the above comment - just figured that a quick one-liner here
would prevent confusion of anyone that was skimming through this code,
without diving in to each individual call. A marginal improvement at
best, considering all it takes to grok is to not be lazy and look at the
comment you already provided above. :D
>
> >
> > Either way:
> >
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
>
> Thanks!
>
> >
> > >
> > > val = I915_READ(CNL_PORT_COMP_DW0);
> > > val |= COMP_INIT;
> > > --
> > > 2.14.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init
2018-01-24 0:49 ` James Ausmus
@ 2018-01-26 20:50 ` Paulo Zanoni
2018-01-29 17:47 ` Paulo Zanoni
0 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-26 20:50 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
Em Ter, 2018-01-23 às 16:49 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> > From: Mahesh Kumar <mahesh1.kumar@intel.com>
> >
> > ICL has 2 slices of DBuf, enable both the slices during display
> > init.
> >
> > Ideally we should only enable the second slice when needed in order
> > to
> > save power, but while we're not there yet, adopt the simpler
> > solution
> > to keep us bug-free.
> >
> > v2 (from Paulo):
> > - Add the TODO comment.
> > - Reorganize where things are defined.
> > - Fix indentation.
> > - Remove unnecessary POSTING_READ() calls.
> > - Improve the commit message.
> >
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 34
> > +++++++++++++++++++++++++++++++--
> > 2 files changed, 34 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 979bc06a59f4..1746df9a263d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7122,6 +7122,8 @@ enum {
> > #define DISP_DATA_PARTITION_5_6 (1<<6)
> > #define DISP_IPC_ENABLE (1<<3)
> > #define DBUF_CTL _MMIO(0x45008)
> > +#define DBUF_CTL_S1 _MMIO(0x45008)
>
> Since it's the exact same register, is it really worth duplicating,
> or
> should we just use the existing DBUF_CTL instead of adding
> DBUF_CTL_S1?
I like it: it's just a single extra line on i915_reg.h and adds clarity
to the code that uses it. But I have nothing against removing it too.
>
>
> > +#define DBUF_CTL_S2 _MMIO(0x44FE8)
> > #define DBUF_POWER_REQUEST (1<<31)
> > #define DBUF_POWER_STATE (1<<30)
> > #define GEN7_MSG_CTL _MMIO(0x45010)
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 2556db16c76a..7801a425398f 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct
> > drm_i915_private *dev_priv)
> > DRM_ERROR("DBuf power disable timeout!\n");
> > }
> >
> > +/*
> > + * TODO: we shouldn't always enable DBUF_CTL_S2, we should only
> > enable it when
> > + * needed and keep it disabled as much as possible.
> > + */
> > +static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> > +{
> > + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) |
> > DBUF_POWER_REQUEST);
> > + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) |
> > DBUF_POWER_REQUEST);
> > + POSTING_READ(DBUF_CTL_S2);
> > +
> > + udelay(10);
>
> BSpec says to poll, and timeout/fail after 10 uS, rather than
> unconditionally busy wait - worth making more complex to potentially
> save a few uS of busy wait?
Yeah, good points. We have intel_wait_for_register() to help avoid the
complexity here.
>
> > +
> > + if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> > + !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > + DRM_ERROR("DBuf power enable timeout\n");
> > +}
> > +
> > +static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> > +{
> > + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) &
> > ~DBUF_POWER_REQUEST);
> > + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) &
> > ~DBUF_POWER_REQUEST);
> > + POSTING_READ(DBUF_CTL_S2);
> > +
> > + udelay(10);
> > +
> > + if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> > + (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > + DRM_ERROR("DBuf power disable timeout!\n");
> > +}
> > +
> > static void skl_display_core_init(struct drm_i915_private
> > *dev_priv,
> > bool resume)
> > {
> > @@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct
> > drm_i915_private *dev_priv,
> > icl_init_cdclk(dev_priv);
> >
> > /* 6. Enable DBUF. */
> > - gen9_dbuf_enable(dev_priv);
> > + icl_dbuf_enable(dev_priv);
> >
> > /* 7. Setup MBUS. */
> > /* FIXME: MBUS code not here yet. */
> > @@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct
> > drm_i915_private *dev_priv)
> > /* 1. Disable all display engine functions -> aready done
> > */
> >
> > /* 2. Disable DBUF */
> > - gen9_dbuf_disable(dev_priv);
> > + icl_dbuf_disable(dev_priv);
> >
> > /* 3. Disable CD clock */
> > icl_uninit_cdclk(dev_priv);
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
@ 2018-01-26 23:14 ` James Ausmus
2018-02-01 20:09 ` Paulo Zanoni
2018-01-29 10:51 ` Imre Deak
2018-02-02 19:57 ` Paulo Zanoni
2 siblings, 1 reply; 59+ messages in thread
From: James Ausmus @ 2018-01-26 23:14 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
>
> v2:
> - Implement the voltage levels.
> - Rebase.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +-
> drivers/gpu/drm/i915/intel_cdclk.c | 253 ++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 261 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index abd9ee876186..d72e206b2b9f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7113,8 +7113,12 @@ enum {
> #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
>
> -#define SKL_DSSM _MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define SKL_DSSM _MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
>
> #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> @@ -8760,6 +8764,8 @@ enum skl_power_gate {
> #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> +#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
This isn't right - pipe A is (0 << 19), but pipe B is (2 << 19), and C
is (6 << 19).
> +#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
>
> /* LCPLL_CTL */
> #define LCPLL1_CTL _MMIO(0x46010)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index c4392ea34a3d..d867956d5a9f 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco = -1;
> }
>
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> + int ranges_24[] = { 312000, 552000, 648000 };
> + int ranges_19_38[] = { 307200, 556800, 652800 };
> + int *ranges;
> +
> + switch (ref) {
> + default:
> + MISSING_CASE(ref);
> + case 24000:
> + ranges = ranges_24;
> + break;
> + case 19200:
> + case 38400:
> + ranges = ranges_19_38;
> + break;
> + }
> +
> + if (min_cdclk > ranges[1])
> + return ranges[2];
> + else if (min_cdclk > ranges[0])
> + return ranges[1];
> + else
> + return ranges[0];
> +}
> +
> +static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> + int ratio;
> +
> + /* 50MHz == CDCLK PLL disabled. */
> + if (cdclk == 50000)
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case 307200:
> + case 556800:
> + case 652800:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400);
> + break;
> + case 312000:
> + case 552000:
> + case 648000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + }
> +
> + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> +
> + return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_state *cdclk_state)
> +{
> + unsigned int cdclk = cdclk_state->cdclk;
> + unsigned int vco = cdclk_state->vco;
> + int ret;
> + u32 voltage_level;
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + mutex_unlock(&dev_priv->pcu_lock);
> + if (ret) {
> + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> + ret);
> + return;
> + }
> +
> + /* FIXME: We should also consider the DDI clock here. */
> + switch (cdclk) {
> + case 307200:
> + case 312000:
> + voltage_level = 0;
> + break;
> + case 556800:
> + case 552000:
> + voltage_level = 1;
> + break;
> + default:
> + MISSING_CASE(cdclk);
> + case 652800:
> + case 648000:
> + voltage_level = 2;
> + break;
> + }
> +
> + if (dev_priv->cdclk.hw.vco != 0 &&
> + dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_disable(dev_priv);
> +
> + if (dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_enable(dev_priv, vco);
> +
> + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> + skl_cdclk_decimal(cdclk));
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + voltage_level);
> + mutex_unlock(&dev_priv->pcu_lock);
> +
> + intel_update_cdclk(dev_priv);
> +}
> +
> +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> + struct intel_cdclk_state *cdclk_state)
> +{
> + u32 val;
> +
> + val = I915_READ(SKL_DSSM);
> + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> + default:
> + MISSING_CASE(val);
> + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> + cdclk_state->ref = 24000;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> + cdclk_state->ref = 19200;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> + cdclk_state->ref = 38400;
> + break;
> + }
> +
> + val = I915_READ(BXT_DE_PLL_ENABLE);
> + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> + (val & BXT_DE_PLL_LOCK) == 0) {
> + /* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> + * setting it to zero is a way to signal that. */
> + cdclk_state->vco = 0;
> + cdclk_state->cdclk = 50000;
> + return;
> + }
> +
> + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> +
> + val = I915_READ(CDCLK_CTL);
> + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> +
> + cdclk_state->cdclk = cdclk_state->vco / 2;
> +}
> +
> +/**
> + * icl_init_cdclk - Initialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Initialize CDCLK for ICL. This consists mainly of initializing
> + * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
> + * is generally done only during the display core initialization sequence, after
> + * which the DMC will take care of turning CDCLK off/on as needed.
> + */
> +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state cdclk_state;
> + u32 val;
> +
> + /* This sets dev_priv->cdclk.hw. */
> + intel_update_cdclk(dev_priv);
> +
> + cdclk_state = dev_priv->cdclk.hw;
> +
> + /* This means CDCLK disabled. */
> + if (cdclk_state.cdclk == 50000)
> + goto sanitize;
> +
> + val = I915_READ(CDCLK_CTL);
> +
> + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> + goto sanitize;
> +
> + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> + skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> + goto sanitize;
> +
> + return;
> +
> +sanitize:
> + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> +
> + cdclk_state.ref = dev_priv->cdclk.hw.ref;
> + cdclk_state.cdclk = icl_calc_cdclk(0, cdclk_state.ref);
> + cdclk_state.vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> +
> + icl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
> +/**
> + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Uninitialize CDCLK for ICL. This is done only during the display core
> + * uninitialization sequence.
> + */
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> + cdclk_state.cdclk = cdclk_state.ref;
> + cdclk_state.vco = 0;
> +
> + icl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
> /**
> * cnl_init_cdclk - Initialize CDCLK on CNL
> * @dev_priv: i915 device
> @@ -2204,6 +2413,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> return 0;
> }
>
> +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + unsigned int ref = intel_state->cdclk.logical.ref;
> + int min_cdclk, cdclk, vco;
> +
> + min_cdclk = intel_compute_min_cdclk(state);
> + if (min_cdclk < 0)
> + return min_cdclk;
> +
> + cdclk = icl_calc_cdclk(min_cdclk, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.logical.vco = vco;
> + intel_state->cdclk.logical.cdclk = cdclk;
> +
> + if (!intel_state->active_crtcs) {
> + cdclk = icl_calc_cdclk(0, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.actual.vco = vco;
> + intel_state->cdclk.actual.cdclk = cdclk;
> + } else {
> + intel_state->cdclk.actual = intel_state->cdclk.logical;
> + }
> +
> + return 0;
> +}
> +
> static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> {
> int max_cdclk_freq = dev_priv->max_cdclk_freq;
> @@ -2237,7 +2476,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> */
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + if (dev_priv->cdclk.hw.ref == 24000)
> + dev_priv->max_cdclk_freq = 648000;
> + else
> + dev_priv->max_cdclk_freq = 652800;
> + } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 528000;
> } else if (IS_GEN9_BC(dev_priv)) {
> u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> @@ -2461,9 +2705,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.set_cdclk = cnl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> cnl_modeset_calc_cdclk;
> + } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.set_cdclk = icl_set_cdclk;
> + dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> }
>
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.get_cdclk = icl_get_cdclk;
> + else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.get_cdclk = cnl_get_cdclk;
> else if (IS_GEN9_BC(dev_priv))
> dev_priv->display.get_cdclk = skl_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3cee54bc0352..c5d6092aca41 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
> void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences
2018-01-23 19:05 ` [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences Paulo Zanoni
@ 2018-01-26 23:25 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-26 23:25 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:22PM -0200, Paulo Zanoni wrote:
> This code is similar enough to the CNL code that I considered just
> adding ICL support to the CNL function, but I think it's still
> different enough, and having a function specific to ICL allows us to
> more easily adapt code in case the spec changes more later.
>
> We're still missing the power wells and the mbus code, so leave those
> pieces with a FIXME comment while they're not here yet.
>
> v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 82 ++++++++++++++++++++++++++++++++-
> 2 files changed, 94 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ebf6261d30fd..979bc06a59f4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1904,6 +1904,11 @@ enum i915_power_well_id {
> #define CL_POWER_DOWN_ENABLE (1 << 4)
> #define SUS_CLOCK_CONFIG (3 << 0)
>
> +#define _ICL_PORT_CL_DW5_A 0x162014
> +#define _ICL_PORT_CL_DW5_B 0x6C014
> +#define ICL_PORT_CL_DW5(port) _MMIO((port == PORT_A) ? \
> + _ICL_PORT_CL_DW5_A : _ICL_PORT_CL_DW5_B)
> +
> #define _PORT_CL1CM_DW9_A 0x162024
> #define _PORT_CL1CM_DW9_BC 0x6C024
> #define IREF0RC_OFFSET_SHIFT 8
> @@ -7126,8 +7131,9 @@ enum {
> #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
>
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> -#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
> -#define MASK_WAKEMEM (1<<13)
> +#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
> +#define MASK_WAKEMEM (1 << 13)
> +#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
>
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> @@ -9696,4 +9702,10 @@ enum skl_power_gate {
> #define MMCD_PCLA (1 << 31)
> #define MMCD_HOTSPOT_EN (1 << 27)
>
> +#define _ICL_PHY_MISC_A 0x64C00
> +#define _ICL_PHY_MISC_B 0x64C04
> +#define ICL_PHY_MISC(port) _MMIO((port == PORT_A) ? \
> + _ICL_PHY_MISC_A : _ICL_PHY_MISC_B)
> +#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 73dd525d241a..2556db16c76a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2882,6 +2882,80 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> +static void icl_display_core_init(struct drm_i915_private *dev_priv,
> + bool resume)
> +{
> + enum port port;
> + u32 val;
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> + /* 1. Enable PCH reset handshake. */
> + val = I915_READ(HSW_NDE_RSTWRN_OPT);
> + val |= RESET_PCH_HANDSHAKE_ENABLE;
> + I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +
> + for (port = PORT_A; port <= PORT_B; port++) {
> + /* 2. Enable DDI combo PHY comp. */
> + val = I915_READ(ICL_PHY_MISC(port));
> + val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> + I915_WRITE(ICL_PHY_MISC(port), val);
> +
> + cnl_set_procmon_ref_values(dev_priv, port);
> +
> + val = I915_READ(ICL_PORT_COMP_DW0(port));
> + val |= COMP_INIT;
> + I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> +
> + /* 3. Set power down enable. */
> + val = I915_READ(ICL_PORT_CL_DW5(port));
> + val |= CL_POWER_DOWN_ENABLE;
> + I915_WRITE(ICL_PORT_CL_DW5(port), val);
> + }
> +
> + /* 4. Enable power well 1 (PG1) and aux IO power. */
> + /* FIXME: ICL power wells code not here yet. */
> +
> + /* 5. Enable CDCLK. */
> + icl_init_cdclk(dev_priv);
> +
> + /* 6. Enable DBUF. */
> + gen9_dbuf_enable(dev_priv);
> +
> + /* 7. Setup MBUS. */
> + /* FIXME: MBUS code not here yet. */
> +
> + /* 8. CHICKEN_DCPR_1 */
> + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> + CNL_DDI_CLOCK_REG_ACCESS_ON);
> +}
> +
> +static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> +{
> + enum port port;
> + u32 val;
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> + /* 1. Disable all display engine functions -> aready done */
> +
> + /* 2. Disable DBUF */
> + gen9_dbuf_disable(dev_priv);
> +
> + /* 3. Disable CD clock */
> + icl_uninit_cdclk(dev_priv);
> +
> + /* 4. Disable Power Well 1 (PG1) and Aux IO Power */
> + /* FIXME: ICL power wells code not here yet. */
> +
> + /* 5. Disable Comp */
> + for (port = PORT_A; port <= PORT_B; port++) {
> + val = I915_READ(ICL_PHY_MISC(port));
> + val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> + I915_WRITE(ICL_PHY_MISC(port), val);
> + }
> +}
> +
> static void chv_phy_control_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_well *cmn_bc =
> @@ -3014,7 +3088,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>
> power_domains->initializing = true;
>
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + icl_display_core_init(dev_priv, resume);
> + } else if (IS_CANNONLAKE(dev_priv)) {
> cnl_display_core_init(dev_priv, resume);
> } else if (IS_GEN9_BC(dev_priv)) {
> skl_display_core_init(dev_priv, resume);
> @@ -3055,7 +3131,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
> if (!i915_modparams.disable_power_well)
> intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
>
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + icl_display_core_uninit(dev_priv);
> + else if (IS_CANNONLAKE(dev_priv))
> cnl_display_core_uninit(dev_priv);
> else if (IS_GEN9_BC(dev_priv))
> skl_display_core_uninit(dev_priv);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
2018-01-23 19:05 ` [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
@ 2018-01-26 23:50 ` James Ausmus
2018-01-29 18:16 ` Paulo Zanoni
2018-01-29 23:08 ` [PATCH 07/13] " Paulo Zanoni
1 sibling, 1 reply; 59+ messages in thread
From: James Ausmus @ 2018-01-26 23:50 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:26PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> ICL require DDB allocation of plane to be more than "minimum display
> buffer needed" for each level in order to enable WM level.
>
> This patch implements and consider the same while allocating DDB
> and enabling WM.
>
> Changes Since V1:
> - rebase
> Changes Since V2:
> - Remove extra parentheses
> - Use FP16.16 only when absolutely necessary (Paulo)
> Changes Since V3:
> - Rebase
> Changes since v4 (from Paulo)
> - Coding style issue.
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 30 +++++++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 44d952a3d9a6..c6d31a5075ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> struct intel_atomic_state *state =
> to_intel_atomic_state(cstate->base.state);
> bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
> + uint32_t min_disp_buf_needed;
>
> if (latency == 0 ||
> !intel_wm_plane_visible(cstate, intel_pstate)) {
> @@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> }
> }
>
> - if (res_blocks >= ddb_allocation || res_lines > 31) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + if (wp->y_tiled) {
> + uint32_t extra_lines;
> + uint_fixed_16_16_t fp_min_disp_buf_needed;
> +
> + if (res_lines % wp->y_min_scanlines == 0)
> + extra_lines = wp->y_min_scanlines;
> + else
> + extra_lines = wp->y_min_scanlines * 2 -
> + res_lines % wp->y_min_scanlines;
> +
> + fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
> + extra_lines,
> + wp->plane_blocks_per_line);
> + min_disp_buf_needed = fixed16_to_u32_round_up(
> + fp_min_disp_buf_needed);
> + } else {
> + min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
> + }
> + } else {
> + /*
> + * To enable a WM level ddb_allocation should be
> + * greater than result blocks for GEN-9/10.
> + */
> + min_disp_buf_needed = res_blocks + 1;
> + }
> +
> + if (min_disp_buf_needed > ddb_allocation || res_lines > 31) {
> *enabled = false;
>
> /*
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
2018-01-26 23:14 ` James Ausmus
@ 2018-01-29 10:51 ` Imre Deak
2018-02-01 20:08 ` Paulo Zanoni
2018-02-02 19:57 ` Paulo Zanoni
2 siblings, 1 reply; 59+ messages in thread
From: Imre Deak @ 2018-01-29 10:51 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
>
> v2:
> - Implement the voltage levels.
> - Rebase.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +-
> drivers/gpu/drm/i915/intel_cdclk.c | 253 ++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 261 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index abd9ee876186..d72e206b2b9f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7113,8 +7113,12 @@ enum {
> #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
>
> -#define SKL_DSSM _MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define SKL_DSSM _MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
>
> #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> @@ -8760,6 +8764,8 @@ enum skl_power_gate {
> #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> +#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
> +#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
>
> /* LCPLL_CTL */
> #define LCPLL1_CTL _MMIO(0x46010)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index c4392ea34a3d..d867956d5a9f 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco = -1;
> }
>
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> + int ranges_24[] = { 312000, 552000, 648000 };
> + int ranges_19_38[] = { 307200, 556800, 652800 };
> + int *ranges;
> +
> + switch (ref) {
> + default:
> + MISSING_CASE(ref);
> + case 24000:
> + ranges = ranges_24;
> + break;
> + case 19200:
> + case 38400:
> + ranges = ranges_19_38;
> + break;
> + }
> +
> + if (min_cdclk > ranges[1])
> + return ranges[2];
> + else if (min_cdclk > ranges[0])
> + return ranges[1];
> + else
> + return ranges[0];
> +}
> +
> +static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> + int ratio;
> +
> + /* 50MHz == CDCLK PLL disabled. */
> + if (cdclk == 50000)
Here and everywhere else cdclk.hw.bypass should be used instead of hard
coding it.
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case 307200:
> + case 556800:
> + case 652800:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400);
> + break;
> + case 312000:
> + case 552000:
> + case 648000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + }
> +
> + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> +
> + return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_state *cdclk_state)
> +{
> + unsigned int cdclk = cdclk_state->cdclk;
> + unsigned int vco = cdclk_state->vco;
> + int ret;
> + u32 voltage_level;
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + mutex_unlock(&dev_priv->pcu_lock);
> + if (ret) {
> + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> + ret);
> + return;
> + }
> +
> + /* FIXME: We should also consider the DDI clock here. */
> + switch (cdclk) {
> + case 307200:
> + case 312000:
> + voltage_level = 0;
> + break;
> + case 556800:
> + case 552000:
> + voltage_level = 1;
> + break;
> + default:
> + MISSING_CASE(cdclk);
> + case 652800:
> + case 648000:
> + voltage_level = 2;
> + break;
> + }
> +
> + if (dev_priv->cdclk.hw.vco != 0 &&
> + dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_disable(dev_priv);
> +
> + if (dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_enable(dev_priv, vco);
> +
> + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> + skl_cdclk_decimal(cdclk));
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + voltage_level);
> + mutex_unlock(&dev_priv->pcu_lock);
> +
> + intel_update_cdclk(dev_priv);
> +}
> +
> +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> + struct intel_cdclk_state *cdclk_state)
> +{
> + u32 val;
> +
> + val = I915_READ(SKL_DSSM);
> + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> + default:
> + MISSING_CASE(val);
> + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> + cdclk_state->ref = 24000;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> + cdclk_state->ref = 19200;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> + cdclk_state->ref = 38400;
> + break;
> + }
> +
> + val = I915_READ(BXT_DE_PLL_ENABLE);
> + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> + (val & BXT_DE_PLL_LOCK) == 0) {
> + /* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> + * setting it to zero is a way to signal that. */
> + cdclk_state->vco = 0;
> + cdclk_state->cdclk = 50000;
> + return;
> + }
> +
> + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> +
> + val = I915_READ(CDCLK_CTL);
> + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> +
> + cdclk_state->cdclk = cdclk_state->vco / 2;
> +}
> +
> +/**
> + * icl_init_cdclk - Initialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Initialize CDCLK for ICL. This consists mainly of initializing
> + * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
> + * is generally done only during the display core initialization sequence, after
> + * which the DMC will take care of turning CDCLK off/on as needed.
> + */
> +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state cdclk_state;
> + u32 val;
> +
> + /* This sets dev_priv->cdclk.hw. */
> + intel_update_cdclk(dev_priv);
> +
> + cdclk_state = dev_priv->cdclk.hw;
> +
> + /* This means CDCLK disabled. */
> + if (cdclk_state.cdclk == 50000)
> + goto sanitize;
> +
> + val = I915_READ(CDCLK_CTL);
> +
> + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> + goto sanitize;
> +
> + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> + skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> + goto sanitize;
> +
> + return;
> +
> +sanitize:
> + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> +
> + cdclk_state.ref = dev_priv->cdclk.hw.ref;
> + cdclk_state.cdclk = icl_calc_cdclk(0, cdclk_state.ref);
> + cdclk_state.vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> +
> + icl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
> +/**
> + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Uninitialize CDCLK for ICL. This is done only during the display core
> + * uninitialization sequence.
> + */
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> + cdclk_state.cdclk = cdclk_state.ref;
On ICL it's the slow clock (croclock) used for the bypass clock source,
so have to set cdclk_state.bypass here.
> + cdclk_state.vco = 0;
> +
> + icl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
> /**
> * cnl_init_cdclk - Initialize CDCLK on CNL
> * @dev_priv: i915 device
> @@ -2204,6 +2413,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> return 0;
> }
>
> +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + unsigned int ref = intel_state->cdclk.logical.ref;
> + int min_cdclk, cdclk, vco;
> +
> + min_cdclk = intel_compute_min_cdclk(state);
> + if (min_cdclk < 0)
> + return min_cdclk;
> +
> + cdclk = icl_calc_cdclk(min_cdclk, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.logical.vco = vco;
> + intel_state->cdclk.logical.cdclk = cdclk;
> +
> + if (!intel_state->active_crtcs) {
> + cdclk = icl_calc_cdclk(0, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.actual.vco = vco;
> + intel_state->cdclk.actual.cdclk = cdclk;
> + } else {
> + intel_state->cdclk.actual = intel_state->cdclk.logical;
> + }
> +
> + return 0;
> +}
> +
> static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> {
> int max_cdclk_freq = dev_priv->max_cdclk_freq;
> @@ -2237,7 +2476,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> */
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + if (dev_priv->cdclk.hw.ref == 24000)
> + dev_priv->max_cdclk_freq = 648000;
> + else
> + dev_priv->max_cdclk_freq = 652800;
> + } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 528000;
> } else if (IS_GEN9_BC(dev_priv)) {
> u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> @@ -2461,9 +2705,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.set_cdclk = cnl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> cnl_modeset_calc_cdclk;
> + } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.set_cdclk = icl_set_cdclk;
> + dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> }
>
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.get_cdclk = icl_get_cdclk;
> + else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.get_cdclk = cnl_get_cdclk;
> else if (IS_GEN9_BC(dev_priv))
> dev_priv->display.get_cdclk = skl_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3cee54bc0352..c5d6092aca41 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
> void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init
2018-01-26 20:50 ` Paulo Zanoni
@ 2018-01-29 17:47 ` Paulo Zanoni
0 siblings, 0 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-29 17:47 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
Em Sex, 2018-01-26 às 18:50 -0200, Paulo Zanoni escreveu:
> Em Ter, 2018-01-23 às 16:49 -0800, James Ausmus escreveu:
> > On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> > > From: Mahesh Kumar <mahesh1.kumar@intel.com>
> > >
> > > ICL has 2 slices of DBuf, enable both the slices during display
> > > init.
> > >
> > > Ideally we should only enable the second slice when needed in
> > > order
> > > to
> > > save power, but while we're not there yet, adopt the simpler
> > > solution
> > > to keep us bug-free.
> > >
> > > v2 (from Paulo):
> > > - Add the TODO comment.
> > > - Reorganize where things are defined.
> > > - Fix indentation.
> > > - Remove unnecessary POSTING_READ() calls.
> > > - Improve the commit message.
> > >
> > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 34
> > > +++++++++++++++++++++++++++++++--
> > > 2 files changed, 34 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 979bc06a59f4..1746df9a263d 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7122,6 +7122,8 @@ enum {
> > > #define DISP_DATA_PARTITION_5_6 (1<<6)
> > > #define DISP_IPC_ENABLE (1<<3)
> > > #define DBUF_CTL _MMIO(0x45008)
> > > +#define DBUF_CTL_S1 _MMIO(0x45008)
> >
> > Since it's the exact same register, is it really worth duplicating,
> > or
> > should we just use the existing DBUF_CTL instead of adding
> > DBUF_CTL_S1?
>
> I like it: it's just a single extra line on i915_reg.h and adds
> clarity
> to the code that uses it. But I have nothing against removing it too.
>
>
> >
> >
> > > +#define DBUF_CTL_S2 _MMIO(0x44FE8)
> > > #define DBUF_POWER_REQUEST (1<<31)
> > > #define DBUF_POWER_STATE (1<<30)
> > > #define GEN7_MSG_CTL _MMIO(0x45010)
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 2556db16c76a..7801a425398f 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct
> > > drm_i915_private *dev_priv)
> > > DRM_ERROR("DBuf power disable timeout!\n");
> > > }
> > >
> > > +/*
> > > + * TODO: we shouldn't always enable DBUF_CTL_S2, we should only
> > > enable it when
> > > + * needed and keep it disabled as much as possible.
> > > + */
> > > +static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> > > +{
> > > + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) |
> > > DBUF_POWER_REQUEST);
> > > + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) |
> > > DBUF_POWER_REQUEST);
> > > + POSTING_READ(DBUF_CTL_S2);
> > > +
> > > + udelay(10);
> >
> > BSpec says to poll, and timeout/fail after 10 uS, rather than
> > unconditionally busy wait - worth making more complex to
> > potentially
> > save a few uS of busy wait?
>
> Yeah, good points. We have intel_wait_for_register() to help avoid
> the
> complexity here.
Oops, I realized this is just 10us. Our wait macros aren't helpful
here, the sleep is too small.
Also, these functions are modeled after skl_dbuf_{dis,en}enable, which
uses udelay too. We probably want to keep the same coding style for the
gen9 and the icl one.
So I think the best course is to keep the udelay, and if we come up
with a better solution we apply to the skl functions too.
With all that said, I guess my r-b patch on the patch stands.
>
>
> >
> > > +
> > > + if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> > > + !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > > + DRM_ERROR("DBuf power enable timeout\n");
> > > +}
> > > +
> > > +static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> > > +{
> > > + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) &
> > > ~DBUF_POWER_REQUEST);
> > > + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) &
> > > ~DBUF_POWER_REQUEST);
> > > + POSTING_READ(DBUF_CTL_S2);
> > > +
> > > + udelay(10);
> > > +
> > > + if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> > > + (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > > + DRM_ERROR("DBuf power disable timeout!\n");
> > > +}
> > > +
> > > static void skl_display_core_init(struct drm_i915_private
> > > *dev_priv,
> > > bool resume)
> > > {
> > > @@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct
> > > drm_i915_private *dev_priv,
> > > icl_init_cdclk(dev_priv);
> > >
> > > /* 6. Enable DBUF. */
> > > - gen9_dbuf_enable(dev_priv);
> > > + icl_dbuf_enable(dev_priv);
> > >
> > > /* 7. Setup MBUS. */
> > > /* FIXME: MBUS code not here yet. */
> > > @@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct
> > > drm_i915_private *dev_priv)
> > > /* 1. Disable all display engine functions -> aready
> > > done
> > > */
> > >
> > > /* 2. Disable DBUF */
> > > - gen9_dbuf_disable(dev_priv);
> > > + icl_dbuf_disable(dev_priv);
> > >
> > > /* 3. Disable CD clock */
> > > icl_uninit_cdclk(dev_priv);
> > > --
> > > 2.14.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
2018-01-26 23:50 ` James Ausmus
@ 2018-01-29 18:16 ` Paulo Zanoni
0 siblings, 0 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-29 18:16 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
Em Sex, 2018-01-26 às 15:50 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:26PM -0200, Paulo Zanoni wrote:
> > From: Mahesh Kumar <mahesh1.kumar@intel.com>
> >
> > ICL require DDB allocation of plane to be more than "minimum
> > display
> > buffer needed" for each level in order to enable WM level.
> >
> > This patch implements and consider the same while allocating DDB
> > and enabling WM.
> >
> > Changes Since V1:
> > - rebase
> > Changes Since V2:
> > - Remove extra parentheses
> > - Use FP16.16 only when absolutely necessary (Paulo)
> > Changes Since V3:
> > - Rebase
> > Changes since v4 (from Paulo)
> > - Coding style issue.
> >
> > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 30
> > +++++++++++++++++++++++++++++-
> > 1 file changed, 29 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 44d952a3d9a6..c6d31a5075ad 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> > struct intel_atomic_state *state =
> > to_intel_atomic_state(cstate->base.state);
> > bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
> > + uint32_t min_disp_buf_needed;
> >
> > if (latency == 0 ||
> > !intel_wm_plane_visible(cstate, intel_pstate)) {
> > @@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> > }
> > }
> >
> > - if (res_blocks >= ddb_allocation || res_lines > 31) {
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > + if (wp->y_tiled) {
> > + uint32_t extra_lines;
> > + uint_fixed_16_16_t fp_min_disp_buf_needed;
> > +
> > + if (res_lines % wp->y_min_scanlines == 0)
> > + extra_lines = wp->y_min_scanlines;
> > + else
> > + extra_lines = wp->y_min_scanlines
> > * 2 -
> > + res_lines % wp-
> > >y_min_scanlines;
> > +
> > + fp_min_disp_buf_needed =
> > mul_u32_fixed16(res_lines +
> > + extra_lines,
> > + wp-
> > >plane_blocks_per_line);
> > + min_disp_buf_needed =
> > fixed16_to_u32_round_up(
> > + fp_min_disp_buf_ne
> > eded);
> > + } else {
> > + min_disp_buf_needed =
> > DIV_ROUND_UP(res_blocks * 11, 10);
> > + }
> > + } else {
> > + /*
> > + * To enable a WM level ddb_allocation should be
> > + * greater than result blocks for GEN-9/10.
> > + */
> > + min_disp_buf_needed = res_blocks + 1;
> > + }
> > +
> > + if (min_disp_buf_needed > ddb_allocation || res_lines >
BSpec says that if min_disp_buf_needed == ddb_allocation we should also
fail, as weird as it sounds.
> > 31) {
> > *enabled = false;
> >
> > /*
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform
2018-01-23 19:05 ` [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform Paulo Zanoni
2018-01-25 23:09 ` James Ausmus
@ 2018-01-29 22:07 ` Paulo Zanoni
1 sibling, 0 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-29 22:07 UTC (permalink / raw)
To: intel-gfx
Em Ter, 2018-01-23 às 17:05 -0200, Paulo Zanoni escreveu:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> Enable SAGV for ICL platform.
The requirements for enabling SAGV on ICL are different. We need to
implement them. While we don't have them, perhaps the best option is to
add ICL to intel_has_sagv() but then always return false on
can_enable_sagv().
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 1edd1445ab5b..dedc76781524 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3605,7 +3605,7 @@ static bool
> intel_has_sagv(struct drm_i915_private *dev_priv)
> {
> if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> - IS_CANNONLAKE(dev_priv))
> + IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv))
> return true;
>
> if (IS_SKYLAKE(dev_priv) &&
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512
2018-01-23 19:05 ` [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
2018-01-24 1:14 ` James Ausmus
@ 2018-01-29 23:07 ` Paulo Zanoni
2018-01-29 23:32 ` James Ausmus
1 sibling, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-29 23:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512
This patch addresses the same.
v2 (from Paulo):
- Make it compile.
- Fix a few coding style issues.
v3:
- Rebase on top of upstream patches
v4 (from Paulo):
- Bikeshed if statements (James).
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++-------
2 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 454d8f937fae..d93e784c3f14 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1460,6 +1460,7 @@ struct skl_wm_params {
uint_fixed_16_16_t plane_blocks_per_line;
uint_fixed_16_16_t y_tile_minimum;
uint32_t linetime_us;
+ uint32_t dbuf_block_size;
};
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 11aac65d1543..985642cf1c9a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
static uint_fixed_16_16_t
skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
- uint8_t cpp, uint32_t latency)
+ uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
{
uint32_t wm_intermediate_val;
uint_fixed_16_16_t ret;
@@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
return FP_16_16_MAX;
wm_intermediate_val = latency * pixel_rate * cpp;
- ret = div_fixed16(wm_intermediate_val, 1000 * 512);
+ ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
if (INTEL_GEN(dev_priv) >= 10)
ret = add_fixed16_u32(ret, 1);
@@ -4431,6 +4431,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
+ wp->dbuf_block_size = 256;
+ else
+ wp->dbuf_block_size = 512;
+
if (drm_rotation_90_or_270(pstate->rotation)) {
switch (wp->cpp) {
@@ -4457,7 +4463,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_bytes_per_line = wp->width * wp->cpp;
if (wp->y_tiled) {
interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
- wp->y_min_scanlines, 512);
+ wp->y_min_scanlines,
+ wp->dbuf_block_size);
if (INTEL_GEN(dev_priv) >= 10)
interm_pbpl++;
@@ -4465,10 +4472,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
wp->y_min_scanlines);
} else if (wp->x_tiled && IS_GEN9(dev_priv)) {
- interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
+ interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+ wp->dbuf_block_size);
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
} else {
- interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
+ interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
+ wp->dbuf_block_size) + 1;
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
}
@@ -4515,7 +4524,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
latency += 15;
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
- wp->cpp, latency);
+ wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
cstate->base.adjusted_mode.crtc_htotal,
latency,
@@ -4525,7 +4534,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
selected_result = max_fixed16(method2, wp->y_tile_minimum);
} else {
if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
- 512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
+ wp->dbuf_block_size < 1) &&
+ (wp->plane_bytes_per_line / wp->dbuf_block_size < 1))
selected_result = method2;
else if (ddb_allocation >=
fixed16_to_u32_round_up(wp->plane_blocks_per_line))
--
2.14.3
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 07/13] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
2018-01-23 19:05 ` [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
2018-01-26 23:50 ` James Ausmus
@ 2018-01-29 23:08 ` Paulo Zanoni
1 sibling, 0 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-01-29 23:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mahesh Kumar <mahesh1.kumar@intel.com>
ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.
This patch implements and consider the same while allocating DDB
and enabling WM.
Changes Since V1:
- rebase
Changes Since V2:
- Remove extra parentheses
- Use FP16.16 only when absolutely necessary (Paulo)
Changes Since V3:
- Rebase
Changes since v4 (from Paulo):
- Coding style issue.
Changes since v5 (from Paulo):
- Do the final checks according to BSpec.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 985642cf1c9a..24421603e605 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4507,6 +4507,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+ uint32_t min_disp_buf_needed;
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
@@ -4565,7 +4566,31 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
- if (res_blocks >= ddb_allocation || res_lines > 31) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if (wp->y_tiled) {
+ uint32_t extra_lines;
+ uint_fixed_16_16_t fp_min_disp_buf_needed;
+
+ if (res_lines % wp->y_min_scanlines == 0)
+ extra_lines = wp->y_min_scanlines;
+ else
+ extra_lines = wp->y_min_scanlines * 2 -
+ res_lines % wp->y_min_scanlines;
+
+ fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
+ extra_lines,
+ wp->plane_blocks_per_line);
+ min_disp_buf_needed = fixed16_to_u32_round_up(
+ fp_min_disp_buf_needed);
+ } else {
+ min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
+ }
+ } else {
+ min_disp_buf_needed = res_blocks;
+ }
+
+ if (res_blocks >= ddb_allocation || res_lines > 31 ||
+ min_disp_buf_needed >= ddb_allocation) {
*enabled = false;
/*
--
2.14.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev2)
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (18 preceding siblings ...)
2018-01-23 20:32 ` Patchwork
@ 2018-01-29 23:27 ` Patchwork
2018-02-02 17:10 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev4) Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-01-29 23:27 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL display initialization and some plane bits (rev2)
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v2 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/2/mbox/
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6700hq) fdo#101144 +2
pass -> FAIL (fi-skl-6700k2) fdo#103191 +1
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2)
Subgroup suspend-read-crc-pipe-b:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2) k.org#197971 +1
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-6260u) fdo#104108 +4
pass -> FAIL (fi-skl-guc)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
k.org#197971 https://bugzilla.kernel.org/show_bug.cgi?id=197971
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:423s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:370s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:485s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s
fi-bxt-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:484s
fi-bxt-j4205 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:29 time:485s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:457s
fi-cfl-s2 total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:579s
fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:277s
fi-glk-1 total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:525s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:391s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:419s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:412s
fi-kbl-7500u total:288 pass:260 dwarn:1 dfail:0 fail:3 skip:24 time:457s
fi-kbl-7560u total:288 pass:266 dwarn:0 dfail:0 fail:3 skip:19 time:512s
fi-kbl-7567u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:456s
fi-kbl-r total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:510s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:583s
fi-skl-6260u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:433s
fi-skl-6600u total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:519s
fi-skl-6700hq total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:543s
fi-skl-6700k2 total:288 pass:261 dwarn:0 dfail:0 fail:3 skip:24 time:492s
fi-skl-6770hq total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:483s
fi-skl-guc total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:414s
fi-skl-gvtdvm total:288 pass:262 dwarn:0 dfail:0 fail:3 skip:23 time:429s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:531s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:395s
Blacklisted hosts:
fi-cnl-y2 total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:539s
fi-glk-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:476s
9afefca72cf89d53e114f3974c5afea1d663d3e1 drm-tip: 2018y-01m-29d-22h-12m-08s UTC integration manifest
a9ee4f23c23b drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
94325c7e126b drm/i915/icl: enable SAGV for ICL platform
462ab6bcb6b0 drm/i915/gen11: fix the SAGV block time for gen11
ac5d8840f289 drm/i915/icl: update ddb entry start/end mask during hw ddb readout
bd683961eddf drm/i915/icl: Enable 2nd DBuf slice only when needed
30701d8f58a9 drm/i915/icl: track dbuf slice-2 status
fce797b73ecd drm/i915/icl: program mbus during pipe enable
40237ae77de5 drm/i915/icl: initialize MBus during display init
21b9265bcffb drm/i915/icl: Introduce MBus related registers
00b53925a048 drm/i915/icl: NV12 y-plane ddb is not in same plane
498323cdfc43 drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed
ed89cfce6dcb drm/i915/icl: Do not fix dbuf block size to 512
31861a2bec35 drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
cd87c063e74a drm/i915/icl: Enable both DBuf slices during init
49ebf8046690 drm/i915/icl: implement the display init/uninit sequences
0764d6d669ce drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
d8bd43cd0047 drm/i915/icl: add the main CDCLK functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7811/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512
2018-01-29 23:07 ` Paulo Zanoni
@ 2018-01-29 23:32 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-01-29 23:32 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Mon, Jan 29, 2018 at 09:07:30PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
> fixed number anymore in GEN11, it varies according to bits per pixel
> and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
> size = 512
>
> This patch addresses the same.
>
> v2 (from Paulo):
> - Make it compile.
> - Fix a few coding style issues.
> v3:
> - Rebase on top of upstream patches
> v4 (from Paulo):
> - Bikeshed if statements (James).
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++-------
> 2 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 454d8f937fae..d93e784c3f14 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1460,6 +1460,7 @@ struct skl_wm_params {
> uint_fixed_16_16_t plane_blocks_per_line;
> uint_fixed_16_16_t y_tile_minimum;
> uint32_t linetime_us;
> + uint32_t dbuf_block_size;
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 11aac65d1543..985642cf1c9a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> */
> static uint_fixed_16_16_t
> skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> - uint8_t cpp, uint32_t latency)
> + uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
> {
> uint32_t wm_intermediate_val;
> uint_fixed_16_16_t ret;
> @@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> return FP_16_16_MAX;
>
> wm_intermediate_val = latency * pixel_rate * cpp;
> - ret = div_fixed16(wm_intermediate_val, 1000 * 512);
> + ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>
> if (INTEL_GEN(dev_priv) >= 10)
> ret = add_fixed16_u32(ret, 1);
> @@ -4431,6 +4431,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
> intel_pstate);
>
> + if (INTEL_GEN(dev_priv) >= 11 &&
> + fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
> + wp->dbuf_block_size = 256;
> + else
> + wp->dbuf_block_size = 512;
> +
> if (drm_rotation_90_or_270(pstate->rotation)) {
>
> switch (wp->cpp) {
> @@ -4457,7 +4463,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->plane_bytes_per_line = wp->width * wp->cpp;
> if (wp->y_tiled) {
> interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
> - wp->y_min_scanlines, 512);
> + wp->y_min_scanlines,
> + wp->dbuf_block_size);
>
> if (INTEL_GEN(dev_priv) >= 10)
> interm_pbpl++;
> @@ -4465,10 +4472,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
> wp->y_min_scanlines);
> } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> + wp->dbuf_block_size);
> wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> } else {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> + wp->dbuf_block_size) + 1;
> wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> }
>
> @@ -4515,7 +4524,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> latency += 15;
>
> method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> - wp->cpp, latency);
> + wp->cpp, latency, wp->dbuf_block_size);
> method2 = skl_wm_method2(wp->plane_pixel_rate,
> cstate->base.adjusted_mode.crtc_htotal,
> latency,
> @@ -4525,7 +4534,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> selected_result = max_fixed16(method2, wp->y_tile_minimum);
> } else {
> if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
> - 512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
> + wp->dbuf_block_size < 1) &&
> + (wp->plane_bytes_per_line / wp->dbuf_block_size < 1))
> selected_result = method2;
> else if (ddb_allocation >=
> fixed16_to_u32_round_up(wp->plane_blocks_per_line))
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-01-29 10:51 ` Imre Deak
@ 2018-02-01 20:08 ` Paulo Zanoni
2018-02-01 20:40 ` Imre Deak
0 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-02-01 20:08 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
Em Seg, 2018-01-29 às 12:51 +0200, Imre Deak escreveu:
> On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> >
> > v2:
> > - Implement the voltage levels.
> > - Rebase.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 10 +-
> > drivers/gpu/drm/i915/intel_cdclk.c | 253
> > ++++++++++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/intel_drv.h | 2 +
> > 3 files changed, 261 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index abd9ee876186..d72e206b2b9f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7113,8 +7113,12 @@ enum {
> > #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> >
> > -#define SKL_DSSM _MMIO(0x51004)
> > -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define SKL_DSSM _MMIO(0x51004)
> > +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> >
> > #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> > #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> > @@ -8760,6 +8764,8 @@ enum skl_power_gate {
> > #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> > #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> > #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> > +#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
> > +#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
> >
> > /* LCPLL_CTL */
> > #define LCPLL1_CTL _MMIO(0x46010)
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index c4392ea34a3d..d867956d5a9f 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct
> > drm_i915_private *dev_priv)
> > dev_priv->cdclk.hw.vco = -1;
> > }
> >
> > +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> > +{
> > + int ranges_24[] = { 312000, 552000, 648000 };
> > + int ranges_19_38[] = { 307200, 556800, 652800 };
> > + int *ranges;
> > +
> > + switch (ref) {
> > + default:
> > + MISSING_CASE(ref);
> > + case 24000:
> > + ranges = ranges_24;
> > + break;
> > + case 19200:
> > + case 38400:
> > + ranges = ranges_19_38;
> > + break;
> > + }
> > +
> > + if (min_cdclk > ranges[1])
> > + return ranges[2];
> > + else if (min_cdclk > ranges[0])
> > + return ranges[1];
> > + else
> > + return ranges[0];
> > +}
> > +
> > +static int icl_calc_cdclk_pll_vco(struct drm_i915_private
> > *dev_priv, int cdclk)
> > +{
> > + int ratio;
> > +
> > + /* 50MHz == CDCLK PLL disabled. */
> > + if (cdclk == 50000)
>
> Here and everywhere else cdclk.hw.bypass should be used instead of
> hard
> coding it.
I really don't understand your comment, and I also looked at "drm/i915:
Add tracking for CDCLK bypass frequency" and don't understand it
either.
On our documentation I can't find anything named "bypass clock", and
there's no explanation in our code nor the commit message. The 50MHz is
the CDCLK value (not "bypass clock") when the CDCLK PLL is disabled.
In the driver, I see the "bypass" clock is set to the refclk we read
from the hardware, and that has nothing to do with the 50MHz we're
talking about at that point. We can't even read that 50MHz value from
the hardware. On ICL, the refclk is either 24, 19.2 or 38.4, we can't
read the 50 anywhere.
I'll really need a better explanation on what exactly you meant with
this "bypass" clock thing if I need to implement it on ICL. I just
can't see those "50000" references going away. I can't see what's wrong
with this code.
>
> > + return 0;
> > +
> > + switch (cdclk) {
> > + default:
> > + MISSING_CASE(cdclk);
> > + case 307200:
> > + case 556800:
> > + case 652800:
> > + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> > + dev_priv->cdclk.hw.ref != 38400);
> > + break;
> > + case 312000:
> > + case 552000:
> > + case 648000:
> > + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> > + }
> > +
> > + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> > +
> > + return dev_priv->cdclk.hw.ref * ratio;
> > +}
> > +
> > +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> > + const struct intel_cdclk_state
> > *cdclk_state)
> > +{
> > + unsigned int cdclk = cdclk_state->cdclk;
> > + unsigned int vco = cdclk_state->vco;
> > + int ret;
> > + u32 voltage_level;
> > +
> > + mutex_lock(&dev_priv->pcu_lock);
> > + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> > + SKL_CDCLK_PREPARE_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE, 3);
> > + mutex_unlock(&dev_priv->pcu_lock);
> > + if (ret) {
> > + DRM_ERROR("Failed to inform PCU about cdclk change
> > (%d)\n",
> > + ret);
> > + return;
> > + }
> > +
> > + /* FIXME: We should also consider the DDI clock here. */
> > + switch (cdclk) {
> > + case 307200:
> > + case 312000:
> > + voltage_level = 0;
> > + break;
> > + case 556800:
> > + case 552000:
> > + voltage_level = 1;
> > + break;
> > + default:
> > + MISSING_CASE(cdclk);
> > + case 652800:
> > + case 648000:
> > + voltage_level = 2;
> > + break;
> > + }
> > +
> > + if (dev_priv->cdclk.hw.vco != 0 &&
> > + dev_priv->cdclk.hw.vco != vco)
> > + cnl_cdclk_pll_disable(dev_priv);
> > +
> > + if (dev_priv->cdclk.hw.vco != vco)
> > + cnl_cdclk_pll_enable(dev_priv, vco);
> > +
> > + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> > + skl_cdclk_decimal(cdclk));
> > +
> > + mutex_lock(&dev_priv->pcu_lock);
> > + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> > + voltage_level);
> > + mutex_unlock(&dev_priv->pcu_lock);
> > +
> > + intel_update_cdclk(dev_priv);
> > +}
> > +
> > +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> > + struct intel_cdclk_state *cdclk_state)
> > +{
> > + u32 val;
> > +
> > + val = I915_READ(SKL_DSSM);
> > + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> > + default:
> > + MISSING_CASE(val);
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> > + cdclk_state->ref = 24000;
> > + break;
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> > + cdclk_state->ref = 19200;
> > + break;
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> > + cdclk_state->ref = 38400;
> > + break;
> > + }
> > +
> > + val = I915_READ(BXT_DE_PLL_ENABLE);
> > + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> > + (val & BXT_DE_PLL_LOCK) == 0) {
> > + /* CDCLK PLL is disabled, the VCO/ratio doesn't
> > matter, but
> > + * setting it to zero is a way to signal that. */
> > + cdclk_state->vco = 0;
> > + cdclk_state->cdclk = 50000;
> > + return;
> > + }
> > +
> > + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) *
> > cdclk_state->ref;
> > +
> > + val = I915_READ(CDCLK_CTL);
> > + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> > +
> > + cdclk_state->cdclk = cdclk_state->vco / 2;
> > +}
> > +
> > +/**
> > + * icl_init_cdclk - Initialize CDCLK on ICL
> > + * @dev_priv: i915 device
> > + *
> > + * Initialize CDCLK for ICL. This consists mainly of initializing
> > + * dev_priv->cdclk.hw and sanitizing the state of the hardware if
> > needed. This
> > + * is generally done only during the display core initialization
> > sequence, after
> > + * which the DMC will take care of turning CDCLK off/on as needed.
> > + */
> > +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_cdclk_state cdclk_state;
> > + u32 val;
> > +
> > + /* This sets dev_priv->cdclk.hw. */
> > + intel_update_cdclk(dev_priv);
> > +
> > + cdclk_state = dev_priv->cdclk.hw;
> > +
> > + /* This means CDCLK disabled. */
> > + if (cdclk_state.cdclk == 50000)
> > + goto sanitize;
> > +
> > + val = I915_READ(CDCLK_CTL);
> > +
> > + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> > + goto sanitize;
> > +
> > + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> > + skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> > + goto sanitize;
> > +
> > + return;
> > +
> > +sanitize:
> > + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> > +
> > + cdclk_state.ref = dev_priv->cdclk.hw.ref;
> > + cdclk_state.cdclk = icl_calc_cdclk(0, cdclk_state.ref);
> > + cdclk_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> > cdclk_state.cdclk);
> > +
> > + icl_set_cdclk(dev_priv, &cdclk_state);
> > +}
> > +
> > +/**
> > + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> > + * @dev_priv: i915 device
> > + *
> > + * Uninitialize CDCLK for ICL. This is done only during the
> > display core
> > + * uninitialization sequence.
> > + */
> > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> > +
> > + cdclk_state.cdclk = cdclk_state.ref;
>
> On ICL it's the slow clock (croclock) used for the bypass clock
> source,
> so have to set cdclk_state.bypass here.
>
> > + cdclk_state.vco = 0;
> > +
> > + icl_set_cdclk(dev_priv, &cdclk_state);
> > +}
> > +
> > /**
> > * cnl_init_cdclk - Initialize CDCLK on CNL
> > * @dev_priv: i915 device
> > @@ -2204,6 +2413,36 @@ static int cnl_modeset_calc_cdclk(struct
> > drm_atomic_state *state)
> > return 0;
> > }
> >
> > +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->dev);
> > + struct intel_atomic_state *intel_state =
> > to_intel_atomic_state(state);
> > + unsigned int ref = intel_state->cdclk.logical.ref;
> > + int min_cdclk, cdclk, vco;
> > +
> > + min_cdclk = intel_compute_min_cdclk(state);
> > + if (min_cdclk < 0)
> > + return min_cdclk;
> > +
> > + cdclk = icl_calc_cdclk(min_cdclk, ref);
> > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > +
> > + intel_state->cdclk.logical.vco = vco;
> > + intel_state->cdclk.logical.cdclk = cdclk;
> > +
> > + if (!intel_state->active_crtcs) {
> > + cdclk = icl_calc_cdclk(0, ref);
> > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > +
> > + intel_state->cdclk.actual.vco = vco;
> > + intel_state->cdclk.actual.cdclk = cdclk;
> > + } else {
> > + intel_state->cdclk.actual = intel_state-
> > >cdclk.logical;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int intel_compute_max_dotclk(struct drm_i915_private
> > *dev_priv)
> > {
> > int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > @@ -2237,7 +2476,12 @@ static int intel_compute_max_dotclk(struct
> > drm_i915_private *dev_priv)
> > */
> > void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> > {
> > - if (IS_CANNONLAKE(dev_priv)) {
> > + if (IS_ICELAKE(dev_priv)) {
> > + if (dev_priv->cdclk.hw.ref == 24000)
> > + dev_priv->max_cdclk_freq = 648000;
> > + else
> > + dev_priv->max_cdclk_freq = 652800;
> > + } else if (IS_CANNONLAKE(dev_priv)) {
> > dev_priv->max_cdclk_freq = 528000;
> > } else if (IS_GEN9_BC(dev_priv)) {
> > u32 limit = I915_READ(SKL_DFSM) &
> > SKL_DFSM_CDCLK_LIMIT_MASK;
> > @@ -2461,9 +2705,14 @@ void intel_init_cdclk_hooks(struct
> > drm_i915_private *dev_priv)
> > dev_priv->display.set_cdclk = cnl_set_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > cnl_modeset_calc_cdclk;
> > + } else if (IS_ICELAKE(dev_priv)) {
> > + dev_priv->display.set_cdclk = icl_set_cdclk;
> > + dev_priv->display.modeset_calc_cdclk =
> > icl_modeset_calc_cdclk;
> > }
> >
> > - if (IS_CANNONLAKE(dev_priv))
> > + if (IS_ICELAKE(dev_priv))
> > + dev_priv->display.get_cdclk = icl_get_cdclk;
> > + else if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.get_cdclk = cnl_get_cdclk;
> > else if (IS_GEN9_BC(dev_priv))
> > dev_priv->display.get_cdclk = skl_get_cdclk;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 3cee54bc0352..c5d6092aca41 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private
> > *dev_priv);
> > void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> > void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> > +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> > void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> > void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-01-26 23:14 ` James Ausmus
@ 2018-02-01 20:09 ` Paulo Zanoni
0 siblings, 0 replies; 59+ messages in thread
From: Paulo Zanoni @ 2018-02-01 20:09 UTC (permalink / raw)
To: James Ausmus; +Cc: intel-gfx
Em Sex, 2018-01-26 às 15:14 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> >
> > v2:
> > - Implement the voltage levels.
> > - Rebase.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 10 +-
> > drivers/gpu/drm/i915/intel_cdclk.c | 253
> > ++++++++++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/intel_drv.h | 2 +
> > 3 files changed, 261 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index abd9ee876186..d72e206b2b9f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7113,8 +7113,12 @@ enum {
> > #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> >
> > -#define SKL_DSSM _MMIO(0x51004)
> > -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define SKL_DSSM _MMIO(0x51004)
> > +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> >
> > #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> > #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> > @@ -8760,6 +8764,8 @@ enum skl_power_gate {
> > #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> > #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> > #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> > +#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
>
> This isn't right - pipe A is (0 << 19), but pipe B is (2 << 19), and
> C
> is (6 << 19).
Right. I'll fix that once the other review comments on this patch are
clarified.
>
> > +#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
> >
> > /* LCPLL_CTL */
> > #define LCPLL1_CTL _MMIO(0x46010)
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index c4392ea34a3d..d867956d5a9f 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct
> > drm_i915_private *dev_priv)
> > dev_priv->cdclk.hw.vco = -1;
> > }
> >
> > +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> > +{
> > + int ranges_24[] = { 312000, 552000, 648000 };
> > + int ranges_19_38[] = { 307200, 556800, 652800 };
> > + int *ranges;
> > +
> > + switch (ref) {
> > + default:
> > + MISSING_CASE(ref);
> > + case 24000:
> > + ranges = ranges_24;
> > + break;
> > + case 19200:
> > + case 38400:
> > + ranges = ranges_19_38;
> > + break;
> > + }
> > +
> > + if (min_cdclk > ranges[1])
> > + return ranges[2];
> > + else if (min_cdclk > ranges[0])
> > + return ranges[1];
> > + else
> > + return ranges[0];
> > +}
> > +
> > +static int icl_calc_cdclk_pll_vco(struct drm_i915_private
> > *dev_priv, int cdclk)
> > +{
> > + int ratio;
> > +
> > + /* 50MHz == CDCLK PLL disabled. */
> > + if (cdclk == 50000)
> > + return 0;
> > +
> > + switch (cdclk) {
> > + default:
> > + MISSING_CASE(cdclk);
> > + case 307200:
> > + case 556800:
> > + case 652800:
> > + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> > + dev_priv->cdclk.hw.ref != 38400);
> > + break;
> > + case 312000:
> > + case 552000:
> > + case 648000:
> > + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> > + }
> > +
> > + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> > +
> > + return dev_priv->cdclk.hw.ref * ratio;
> > +}
> > +
> > +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> > + const struct intel_cdclk_state
> > *cdclk_state)
> > +{
> > + unsigned int cdclk = cdclk_state->cdclk;
> > + unsigned int vco = cdclk_state->vco;
> > + int ret;
> > + u32 voltage_level;
> > +
> > + mutex_lock(&dev_priv->pcu_lock);
> > + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> > + SKL_CDCLK_PREPARE_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE, 3);
> > + mutex_unlock(&dev_priv->pcu_lock);
> > + if (ret) {
> > + DRM_ERROR("Failed to inform PCU about cdclk change
> > (%d)\n",
> > + ret);
> > + return;
> > + }
> > +
> > + /* FIXME: We should also consider the DDI clock here. */
> > + switch (cdclk) {
> > + case 307200:
> > + case 312000:
> > + voltage_level = 0;
> > + break;
> > + case 556800:
> > + case 552000:
> > + voltage_level = 1;
> > + break;
> > + default:
> > + MISSING_CASE(cdclk);
> > + case 652800:
> > + case 648000:
> > + voltage_level = 2;
> > + break;
> > + }
> > +
> > + if (dev_priv->cdclk.hw.vco != 0 &&
> > + dev_priv->cdclk.hw.vco != vco)
> > + cnl_cdclk_pll_disable(dev_priv);
> > +
> > + if (dev_priv->cdclk.hw.vco != vco)
> > + cnl_cdclk_pll_enable(dev_priv, vco);
> > +
> > + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> > + skl_cdclk_decimal(cdclk));
> > +
> > + mutex_lock(&dev_priv->pcu_lock);
> > + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> > + voltage_level);
> > + mutex_unlock(&dev_priv->pcu_lock);
> > +
> > + intel_update_cdclk(dev_priv);
> > +}
> > +
> > +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> > + struct intel_cdclk_state *cdclk_state)
> > +{
> > + u32 val;
> > +
> > + val = I915_READ(SKL_DSSM);
> > + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> > + default:
> > + MISSING_CASE(val);
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> > + cdclk_state->ref = 24000;
> > + break;
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> > + cdclk_state->ref = 19200;
> > + break;
> > + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> > + cdclk_state->ref = 38400;
> > + break;
> > + }
> > +
> > + val = I915_READ(BXT_DE_PLL_ENABLE);
> > + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> > + (val & BXT_DE_PLL_LOCK) == 0) {
> > + /* CDCLK PLL is disabled, the VCO/ratio doesn't
> > matter, but
> > + * setting it to zero is a way to signal that. */
> > + cdclk_state->vco = 0;
> > + cdclk_state->cdclk = 50000;
> > + return;
> > + }
> > +
> > + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) *
> > cdclk_state->ref;
> > +
> > + val = I915_READ(CDCLK_CTL);
> > + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> > +
> > + cdclk_state->cdclk = cdclk_state->vco / 2;
> > +}
> > +
> > +/**
> > + * icl_init_cdclk - Initialize CDCLK on ICL
> > + * @dev_priv: i915 device
> > + *
> > + * Initialize CDCLK for ICL. This consists mainly of initializing
> > + * dev_priv->cdclk.hw and sanitizing the state of the hardware if
> > needed. This
> > + * is generally done only during the display core initialization
> > sequence, after
> > + * which the DMC will take care of turning CDCLK off/on as needed.
> > + */
> > +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_cdclk_state cdclk_state;
> > + u32 val;
> > +
> > + /* This sets dev_priv->cdclk.hw. */
> > + intel_update_cdclk(dev_priv);
> > +
> > + cdclk_state = dev_priv->cdclk.hw;
> > +
> > + /* This means CDCLK disabled. */
> > + if (cdclk_state.cdclk == 50000)
> > + goto sanitize;
> > +
> > + val = I915_READ(CDCLK_CTL);
> > +
> > + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> > + goto sanitize;
> > +
> > + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> > + skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> > + goto sanitize;
> > +
> > + return;
> > +
> > +sanitize:
> > + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> > +
> > + cdclk_state.ref = dev_priv->cdclk.hw.ref;
> > + cdclk_state.cdclk = icl_calc_cdclk(0, cdclk_state.ref);
> > + cdclk_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> > cdclk_state.cdclk);
> > +
> > + icl_set_cdclk(dev_priv, &cdclk_state);
> > +}
> > +
> > +/**
> > + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> > + * @dev_priv: i915 device
> > + *
> > + * Uninitialize CDCLK for ICL. This is done only during the
> > display core
> > + * uninitialization sequence.
> > + */
> > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> > +
> > + cdclk_state.cdclk = cdclk_state.ref;
> > + cdclk_state.vco = 0;
> > +
> > + icl_set_cdclk(dev_priv, &cdclk_state);
> > +}
> > +
> > /**
> > * cnl_init_cdclk - Initialize CDCLK on CNL
> > * @dev_priv: i915 device
> > @@ -2204,6 +2413,36 @@ static int cnl_modeset_calc_cdclk(struct
> > drm_atomic_state *state)
> > return 0;
> > }
> >
> > +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->dev);
> > + struct intel_atomic_state *intel_state =
> > to_intel_atomic_state(state);
> > + unsigned int ref = intel_state->cdclk.logical.ref;
> > + int min_cdclk, cdclk, vco;
> > +
> > + min_cdclk = intel_compute_min_cdclk(state);
> > + if (min_cdclk < 0)
> > + return min_cdclk;
> > +
> > + cdclk = icl_calc_cdclk(min_cdclk, ref);
> > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > +
> > + intel_state->cdclk.logical.vco = vco;
> > + intel_state->cdclk.logical.cdclk = cdclk;
> > +
> > + if (!intel_state->active_crtcs) {
> > + cdclk = icl_calc_cdclk(0, ref);
> > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > +
> > + intel_state->cdclk.actual.vco = vco;
> > + intel_state->cdclk.actual.cdclk = cdclk;
> > + } else {
> > + intel_state->cdclk.actual = intel_state-
> > >cdclk.logical;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int intel_compute_max_dotclk(struct drm_i915_private
> > *dev_priv)
> > {
> > int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > @@ -2237,7 +2476,12 @@ static int intel_compute_max_dotclk(struct
> > drm_i915_private *dev_priv)
> > */
> > void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> > {
> > - if (IS_CANNONLAKE(dev_priv)) {
> > + if (IS_ICELAKE(dev_priv)) {
> > + if (dev_priv->cdclk.hw.ref == 24000)
> > + dev_priv->max_cdclk_freq = 648000;
> > + else
> > + dev_priv->max_cdclk_freq = 652800;
> > + } else if (IS_CANNONLAKE(dev_priv)) {
> > dev_priv->max_cdclk_freq = 528000;
> > } else if (IS_GEN9_BC(dev_priv)) {
> > u32 limit = I915_READ(SKL_DFSM) &
> > SKL_DFSM_CDCLK_LIMIT_MASK;
> > @@ -2461,9 +2705,14 @@ void intel_init_cdclk_hooks(struct
> > drm_i915_private *dev_priv)
> > dev_priv->display.set_cdclk = cnl_set_cdclk;
> > dev_priv->display.modeset_calc_cdclk =
> > cnl_modeset_calc_cdclk;
> > + } else if (IS_ICELAKE(dev_priv)) {
> > + dev_priv->display.set_cdclk = icl_set_cdclk;
> > + dev_priv->display.modeset_calc_cdclk =
> > icl_modeset_calc_cdclk;
> > }
> >
> > - if (IS_CANNONLAKE(dev_priv))
> > + if (IS_ICELAKE(dev_priv))
> > + dev_priv->display.get_cdclk = icl_get_cdclk;
> > + else if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.get_cdclk = cnl_get_cdclk;
> > else if (IS_GEN9_BC(dev_priv))
> > dev_priv->display.get_cdclk = skl_get_cdclk;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 3cee54bc0352..c5d6092aca41 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private
> > *dev_priv);
> > void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> > void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> > +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> > void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> > void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-02-01 20:08 ` Paulo Zanoni
@ 2018-02-01 20:40 ` Imre Deak
0 siblings, 0 replies; 59+ messages in thread
From: Imre Deak @ 2018-02-01 20:40 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Thu, Feb 01, 2018 at 06:08:29PM -0200, Paulo Zanoni wrote:
> Em Seg, 2018-01-29 às 12:51 +0200, Imre Deak escreveu:
> > On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> > > This commit adds the basic CDCLK functions, but it's still missing
> > > pieces of the display initialization sequence.
> > >
> > > v2:
> > > - Implement the voltage levels.
> > > - Rebase.
> > >
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 10 +-
> > > drivers/gpu/drm/i915/intel_cdclk.c | 253
> > > ++++++++++++++++++++++++++++++++++++-
> > > drivers/gpu/drm/i915/intel_drv.h | 2 +
> > > 3 files changed, 261 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index abd9ee876186..d72e206b2b9f 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7113,8 +7113,12 @@ enum {
> > > #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > > #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> > >
> > > -#define SKL_DSSM _MMIO(0x51004)
> > > -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > > +#define SKL_DSSM _MMIO(0x51004)
> > > +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> > > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> > > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> > > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> > >
> > > #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> > > #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> > > @@ -8760,6 +8764,8 @@ enum skl_power_gate {
> > > #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> > > #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> > > #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> > > +#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
> > > +#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
> > >
> > > /* LCPLL_CTL */
> > > #define LCPLL1_CTL _MMIO(0x46010)
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index c4392ea34a3d..d867956d5a9f 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct
> > > drm_i915_private *dev_priv)
> > > dev_priv->cdclk.hw.vco = -1;
> > > }
> > >
> > > +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> > > +{
> > > + int ranges_24[] = { 312000, 552000, 648000 };
> > > + int ranges_19_38[] = { 307200, 556800, 652800 };
> > > + int *ranges;
> > > +
> > > + switch (ref) {
> > > + default:
> > > + MISSING_CASE(ref);
> > > + case 24000:
> > > + ranges = ranges_24;
> > > + break;
> > > + case 19200:
> > > + case 38400:
> > > + ranges = ranges_19_38;
> > > + break;
> > > + }
> > > +
> > > + if (min_cdclk > ranges[1])
> > > + return ranges[2];
> > > + else if (min_cdclk > ranges[0])
> > > + return ranges[1];
> > > + else
> > > + return ranges[0];
> > > +}
> > > +
> > > +static int icl_calc_cdclk_pll_vco(struct drm_i915_private
> > > *dev_priv, int cdclk)
> > > +{
> > > + int ratio;
> > > +
> > > + /* 50MHz == CDCLK PLL disabled. */
> > > + if (cdclk == 50000)
> >
> > Here and everywhere else cdclk.hw.bypass should be used instead of
> > hard
> > coding it.
>
> I really don't understand your comment, and I also looked at "drm/i915:
> Add tracking for CDCLK bypass frequency" and don't understand it
> either.
>
> On our documentation I can't find anything named "bypass clock", and
> there's no explanation in our code nor the commit message. The 50MHz is
> the CDCLK value (not "bypass clock") when the CDCLK PLL is disabled.
cdclk.hw.bypass is the CDCLK frequency when the CDCLK PLL is disabled.
The clock source for this has different names on different platforms, on
ICL it's called croclk or slow-clock by BSpec which is a 100MHz clock.
This is divided by 2, resulting in the 50MHz bypass frequency, as shown
under "Icelake Clocks"/"CD Clock" in BSpec.
> In the driver, I see the "bypass" clock is set to the refclk we read
> from the hardware, and that has nothing to do with the 50MHz we're
> talking about at that point. We can't even read that 50MHz value from
> the hardware. On ICL, the refclk is either 24, 19.2 or 38.4, we can't
> read the 50 anywhere.
Yes, on ICL the bypass frequency is not refclk based on the above, but
the croclk/2 or 50MHz, so that's what cdclk.hw.bypass needs to be set
to.
> I'll really need a better explanation on what exactly you meant with
> this "bypass" clock thing if I need to implement it on ICL. I just
> can't see those "50000" references going away. I can't see what's wrong
> with this code.
We want to handle this part of the code similarly to all other
platforms, that is by using cdclk.hw.bypass instead of a hard-coded
value. Note that on some platform this frequency can be selected that is
you will have to read it out from the HW the same way you read the
refclk value.
icl_uninit_cdclk() is also using refclk incorrectly, see my comment
below.
--Imre
>
> >
> > > + return 0;
> > > +
> > > + switch (cdclk) {
> > > + default:
> > > + MISSING_CASE(cdclk);
> > > + case 307200:
> > > + case 556800:
> > > + case 652800:
> > > + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> > > + dev_priv->cdclk.hw.ref != 38400);
> > > + break;
> > > + case 312000:
> > > + case 552000:
> > > + case 648000:
> > > + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> > > + }
> > > +
> > > + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> > > +
> > > + return dev_priv->cdclk.hw.ref * ratio;
> > > +}
> > > +
> > > +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> > > + const struct intel_cdclk_state
> > > *cdclk_state)
> > > +{
> > > + unsigned int cdclk = cdclk_state->cdclk;
> > > + unsigned int vco = cdclk_state->vco;
> > > + int ret;
> > > + u32 voltage_level;
> > > +
> > > + mutex_lock(&dev_priv->pcu_lock);
> > > + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> > > + SKL_CDCLK_PREPARE_FOR_CHANGE,
> > > + SKL_CDCLK_READY_FOR_CHANGE,
> > > + SKL_CDCLK_READY_FOR_CHANGE, 3);
> > > + mutex_unlock(&dev_priv->pcu_lock);
> > > + if (ret) {
> > > + DRM_ERROR("Failed to inform PCU about cdclk change
> > > (%d)\n",
> > > + ret);
> > > + return;
> > > + }
> > > +
> > > + /* FIXME: We should also consider the DDI clock here. */
> > > + switch (cdclk) {
> > > + case 307200:
> > > + case 312000:
> > > + voltage_level = 0;
> > > + break;
> > > + case 556800:
> > > + case 552000:
> > > + voltage_level = 1;
> > > + break;
> > > + default:
> > > + MISSING_CASE(cdclk);
> > > + case 652800:
> > > + case 648000:
> > > + voltage_level = 2;
> > > + break;
> > > + }
> > > +
> > > + if (dev_priv->cdclk.hw.vco != 0 &&
> > > + dev_priv->cdclk.hw.vco != vco)
> > > + cnl_cdclk_pll_disable(dev_priv);
> > > +
> > > + if (dev_priv->cdclk.hw.vco != vco)
> > > + cnl_cdclk_pll_enable(dev_priv, vco);
> > > +
> > > + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> > > + skl_cdclk_decimal(cdclk));
> > > +
> > > + mutex_lock(&dev_priv->pcu_lock);
> > > + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> > > + voltage_level);
> > > + mutex_unlock(&dev_priv->pcu_lock);
> > > +
> > > + intel_update_cdclk(dev_priv);
> > > +}
> > > +
> > > +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> > > + struct intel_cdclk_state *cdclk_state)
> > > +{
> > > + u32 val;
> > > +
> > > + val = I915_READ(SKL_DSSM);
> > > + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> > > + default:
> > > + MISSING_CASE(val);
> > > + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> > > + cdclk_state->ref = 24000;
> > > + break;
> > > + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> > > + cdclk_state->ref = 19200;
> > > + break;
> > > + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> > > + cdclk_state->ref = 38400;
> > > + break;
> > > + }
> > > +
> > > + val = I915_READ(BXT_DE_PLL_ENABLE);
> > > + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> > > + (val & BXT_DE_PLL_LOCK) == 0) {
> > > + /* CDCLK PLL is disabled, the VCO/ratio doesn't
> > > matter, but
> > > + * setting it to zero is a way to signal that. */
> > > + cdclk_state->vco = 0;
> > > + cdclk_state->cdclk = 50000;
> > > + return;
> > > + }
> > > +
> > > + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) *
> > > cdclk_state->ref;
> > > +
> > > + val = I915_READ(CDCLK_CTL);
> > > + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> > > +
> > > + cdclk_state->cdclk = cdclk_state->vco / 2;
> > > +}
> > > +
> > > +/**
> > > + * icl_init_cdclk - Initialize CDCLK on ICL
> > > + * @dev_priv: i915 device
> > > + *
> > > + * Initialize CDCLK for ICL. This consists mainly of initializing
> > > + * dev_priv->cdclk.hw and sanitizing the state of the hardware if
> > > needed. This
> > > + * is generally done only during the display core initialization
> > > sequence, after
> > > + * which the DMC will take care of turning CDCLK off/on as needed.
> > > + */
> > > +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_cdclk_state cdclk_state;
> > > + u32 val;
> > > +
> > > + /* This sets dev_priv->cdclk.hw. */
> > > + intel_update_cdclk(dev_priv);
> > > +
> > > + cdclk_state = dev_priv->cdclk.hw;
> > > +
> > > + /* This means CDCLK disabled. */
> > > + if (cdclk_state.cdclk == 50000)
> > > + goto sanitize;
> > > +
> > > + val = I915_READ(CDCLK_CTL);
> > > +
> > > + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> > > + goto sanitize;
> > > +
> > > + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> > > + skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> > > + goto sanitize;
> > > +
> > > + return;
> > > +
> > > +sanitize:
> > > + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> > > +
> > > + cdclk_state.ref = dev_priv->cdclk.hw.ref;
> > > + cdclk_state.cdclk = icl_calc_cdclk(0, cdclk_state.ref);
> > > + cdclk_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> > > cdclk_state.cdclk);
> > > +
> > > + icl_set_cdclk(dev_priv, &cdclk_state);
> > > +}
> > > +
> > > +/**
> > > + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> > > + * @dev_priv: i915 device
> > > + *
> > > + * Uninitialize CDCLK for ICL. This is done only during the
> > > display core
> > > + * uninitialization sequence.
> > > + */
> > > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> > > +
> > > + cdclk_state.cdclk = cdclk_state.ref;
> >
> > On ICL it's the slow clock (croclock) used for the bypass clock
> > source,
> > so have to set cdclk_state.bypass here.
> >
> > > + cdclk_state.vco = 0;
> > > +
> > > + icl_set_cdclk(dev_priv, &cdclk_state);
> > > +}
> > > +
> > > /**
> > > * cnl_init_cdclk - Initialize CDCLK on CNL
> > > * @dev_priv: i915 device
> > > @@ -2204,6 +2413,36 @@ static int cnl_modeset_calc_cdclk(struct
> > > drm_atomic_state *state)
> > > return 0;
> > > }
> > >
> > > +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(state->dev);
> > > + struct intel_atomic_state *intel_state =
> > > to_intel_atomic_state(state);
> > > + unsigned int ref = intel_state->cdclk.logical.ref;
> > > + int min_cdclk, cdclk, vco;
> > > +
> > > + min_cdclk = intel_compute_min_cdclk(state);
> > > + if (min_cdclk < 0)
> > > + return min_cdclk;
> > > +
> > > + cdclk = icl_calc_cdclk(min_cdclk, ref);
> > > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > > +
> > > + intel_state->cdclk.logical.vco = vco;
> > > + intel_state->cdclk.logical.cdclk = cdclk;
> > > +
> > > + if (!intel_state->active_crtcs) {
> > > + cdclk = icl_calc_cdclk(0, ref);
> > > + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> > > +
> > > + intel_state->cdclk.actual.vco = vco;
> > > + intel_state->cdclk.actual.cdclk = cdclk;
> > > + } else {
> > > + intel_state->cdclk.actual = intel_state-
> > > >cdclk.logical;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static int intel_compute_max_dotclk(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > > @@ -2237,7 +2476,12 @@ static int intel_compute_max_dotclk(struct
> > > drm_i915_private *dev_priv)
> > > */
> > > void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> > > {
> > > - if (IS_CANNONLAKE(dev_priv)) {
> > > + if (IS_ICELAKE(dev_priv)) {
> > > + if (dev_priv->cdclk.hw.ref == 24000)
> > > + dev_priv->max_cdclk_freq = 648000;
> > > + else
> > > + dev_priv->max_cdclk_freq = 652800;
> > > + } else if (IS_CANNONLAKE(dev_priv)) {
> > > dev_priv->max_cdclk_freq = 528000;
> > > } else if (IS_GEN9_BC(dev_priv)) {
> > > u32 limit = I915_READ(SKL_DFSM) &
> > > SKL_DFSM_CDCLK_LIMIT_MASK;
> > > @@ -2461,9 +2705,14 @@ void intel_init_cdclk_hooks(struct
> > > drm_i915_private *dev_priv)
> > > dev_priv->display.set_cdclk = cnl_set_cdclk;
> > > dev_priv->display.modeset_calc_cdclk =
> > > cnl_modeset_calc_cdclk;
> > > + } else if (IS_ICELAKE(dev_priv)) {
> > > + dev_priv->display.set_cdclk = icl_set_cdclk;
> > > + dev_priv->display.modeset_calc_cdclk =
> > > icl_modeset_calc_cdclk;
> > > }
> > >
> > > - if (IS_CANNONLAKE(dev_priv))
> > > + if (IS_ICELAKE(dev_priv))
> > > + dev_priv->display.get_cdclk = icl_get_cdclk;
> > > + else if (IS_CANNONLAKE(dev_priv))
> > > dev_priv->display.get_cdclk = cnl_get_cdclk;
> > > else if (IS_GEN9_BC(dev_priv))
> > > dev_priv->display.get_cdclk = skl_get_cdclk;
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 3cee54bc0352..c5d6092aca41 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private
> > > *dev_priv);
> > > void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > > void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> > > void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> > > +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> > > +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> > > void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> > > void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > > --
> > > 2.14.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
2018-01-23 19:05 ` [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Paulo Zanoni
2018-01-24 0:32 ` James Ausmus
2018-01-26 20:33 ` Ville Syrjälä
@ 2018-02-02 16:23 ` Paulo Zanoni
2018-02-02 18:17 ` James Ausmus
2 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-02-02 16:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
On ICL we have two sets of registers: one for port A and another for
port B. The set of port A registers is the same as the CNL registers.
Since the procmon table on ICL is the same we want to reuse the CNL
function. To do that we add a port argument and make CNL always call
the function passing port A. This way, we'll be able to easily reuse
the function on ICL when we add icl_display_core_init().
v2: Don't use _PICK() when you can use a ternary operator.
v3: Don't use a ternary operation when you can use _MMIO_PORT (Ville).
Add an extra comment about why we're passing PORT_A (James).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++++++-------
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65ba10ad1fe5..f6e1677e8211 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2104,6 +2104,28 @@ enum i915_power_well_id {
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
+#define _ICL_PORT_COMP_DW0_A 0x162100
+#define _ICL_PORT_COMP_DW0_B 0x6C100
+#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
+ _ICL_PORT_COMP_DW0_B)
+#define _ICL_PORT_COMP_DW1_A 0x162104
+#define _ICL_PORT_COMP_DW1_B 0x6C104
+#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
+ _ICL_PORT_COMP_DW1_B)
+#define _ICL_PORT_COMP_DW3_A 0x16210C
+#define _ICL_PORT_COMP_DW3_B 0x6C10C
+#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
+ _ICL_PORT_COMP_DW3_B)
+#define _ICL_PORT_COMP_DW9_A 0x162124
+#define _ICL_PORT_COMP_DW9_B 0x6C124
+#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
+ _ICL_PORT_COMP_DW9_B)
+#define _ICL_PORT_COMP_DW10_A 0x162128
+#define _ICL_PORT_COMP_DW10_B 0x6C128
+#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
+ _ICL_PORT_COMP_DW10_A, \
+ _ICL_PORT_COMP_DW10_B)
+
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 70e659772a7a..b4ef7875f055 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2794,12 +2794,19 @@ static const struct cnl_procmon {
{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
};
-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
+/*
+ * CNL has just one set of registers, while ICL has two sets: one for port A and
+ * the other for port B. The CNL registers are equivalent to the ICL port A
+ * registers, that's why we call the ICL macros even though the function has CNL
+ * on its name.
+ */
+static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
+ enum port port)
{
const struct cnl_procmon *procmon;
u32 val;
- val = I915_READ(CNL_PORT_COMP_DW3);
+ val = I915_READ(ICL_PORT_COMP_DW3(port));
switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
default:
MISSING_CASE(val);
@@ -2820,13 +2827,13 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
break;
}
- val = I915_READ(CNL_PORT_COMP_DW1);
+ val = I915_READ(ICL_PORT_COMP_DW1(port));
val &= ~((0xff << 16) | 0xff);
val |= procmon->dw1;
- I915_WRITE(CNL_PORT_COMP_DW1, val);
+ I915_WRITE(ICL_PORT_COMP_DW1(port), val);
- I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
- I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
+ I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
+ I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
}
static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
@@ -2847,7 +2854,8 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
val &= ~CNL_COMP_PWR_DOWN;
I915_WRITE(CHICKEN_MISC_2, val);
- cnl_set_procmon_ref_values(dev_priv);
+ /* Dummy PORT_A to get the correct CNL register from the ICL macro */
+ cnl_set_procmon_ref_values(dev_priv, PORT_A);
val = I915_READ(CNL_PORT_COMP_DW0);
val |= COMP_INIT;
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev4)
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (19 preceding siblings ...)
2018-01-29 23:27 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev2) Patchwork
@ 2018-02-02 17:10 ` Patchwork
2018-02-02 17:28 ` Patchwork
2018-02-02 20:22 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev5) Patchwork
22 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-02-02 17:10 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL display initialization and some plane bits (rev4)
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v4 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/4/mbox/
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test gem_exec_suspend:
Subgroup basic-s4-devices:
incomplete -> PASS (fi-bdw-5557u) fdo#104162
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
pass -> FAIL (fi-skl-6700k2) fdo#103191 +5
Subgroup suspend-read-crc-pipe-a:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6700hq) fdo#101144 +2
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2)
Subgroup suspend-read-crc-pipe-b:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2) k.org#197971 +1
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-6260u) fdo#104108 +4
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
k.org#197971 https://bugzilla.kernel.org/show_bug.cgi?id=197971
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:416s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:424s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:370s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:477s
fi-bxt-j4205 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:29 time:481s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:465s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:457s
fi-cfl-s2 total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:572s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:412s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:278s
fi-glk-1 total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:514s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:389s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:402s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:416s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:455s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:412s
fi-kbl-7500u total:288 pass:260 dwarn:1 dfail:0 fail:3 skip:24 time:450s
fi-kbl-7560u total:288 pass:266 dwarn:0 dfail:0 fail:3 skip:19 time:512s
fi-kbl-7567u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:448s
fi-kbl-r total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:506s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:583s
fi-skl-6260u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:427s
fi-skl-6600u total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:517s
fi-skl-6700hq total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:541s
fi-skl-6700k2 total:288 pass:260 dwarn:0 dfail:0 fail:4 skip:24 time:484s
fi-skl-6770hq total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:480s
fi-skl-guc total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:413s
fi-skl-gvtdvm total:288 pass:262 dwarn:0 dfail:0 fail:3 skip:23 time:431s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:512s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:396s
Blacklisted hosts:
fi-glk-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:468s
bde4e003ce549b8225142843e0d5aee19dd37d13 drm-tip: 2018y-02m-02d-15h-03m-15s UTC integration manifest
457c8d5b63a3 drm/i915/icl: enable SAGV for ICL platform
4528aab7937b drm/i915/icl: update ddb entry start/end mask during hw ddb readout
fe0bf72b3cb2 drm/i915/icl: Enable 2nd DBuf slice only when needed
0b9b9f5c4a5d drm/i915/icl: track dbuf slice-2 status
e64e780fa462 drm/i915/icl: program mbus during pipe enable
c86152701dc3 drm/i915/icl: initialize MBus during display init
d9978ee40fbb drm/i915/icl: Enable both DBuf slices during init
9c71a8f6a2d7 drm/i915/icl: implement the display init/uninit sequences
84b67d8cc654 drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
315088be6ac3 drm/i915/icl: add the main CDCLK functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7865/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev4)
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (20 preceding siblings ...)
2018-02-02 17:10 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev4) Patchwork
@ 2018-02-02 17:28 ` Patchwork
2018-02-02 20:22 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev5) Patchwork
22 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-02-02 17:28 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL display initialization and some plane bits (rev4)
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v4 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/4/mbox/
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test gem_exec_suspend:
Subgroup basic-s4-devices:
incomplete -> PASS (fi-bdw-5557u) fdo#104162
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6700hq) fdo#101144 +2
pass -> FAIL (fi-skl-6700k2) fdo#103191 +4
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2)
Subgroup suspend-read-crc-pipe-b:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2) k.org#197971 +1
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-6260u) fdo#104108 +4
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
k.org#197971 https://bugzilla.kernel.org/show_bug.cgi?id=197971
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:418s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:429s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:370s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:479s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:481s
fi-bxt-j4205 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:29 time:487s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:464s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:452s
fi-cfl-s2 total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:576s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:413s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:280s
fi-glk-1 total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:517s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:388s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:397s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:407s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:410s
fi-kbl-7500u total:288 pass:260 dwarn:1 dfail:0 fail:3 skip:24 time:455s
fi-kbl-7560u total:288 pass:266 dwarn:0 dfail:0 fail:3 skip:19 time:507s
fi-kbl-7567u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:451s
fi-kbl-r total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:507s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:577s
fi-skl-6260u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:424s
fi-skl-6600u total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:518s
fi-skl-6700hq total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:545s
fi-skl-6700k2 total:288 pass:261 dwarn:0 dfail:0 fail:3 skip:24 time:490s
fi-skl-6770hq total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:483s
fi-skl-guc total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:415s
fi-skl-gvtdvm total:288 pass:262 dwarn:0 dfail:0 fail:3 skip:23 time:427s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:521s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:394s
Blacklisted hosts:
fi-glk-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:467s
bde4e003ce549b8225142843e0d5aee19dd37d13 drm-tip: 2018y-02m-02d-15h-03m-15s UTC integration manifest
eb121a71cb8f drm/i915/icl: enable SAGV for ICL platform
b72857f8790c drm/i915/icl: update ddb entry start/end mask during hw ddb readout
868c65ca72e2 drm/i915/icl: Enable 2nd DBuf slice only when needed
5bd5d7ff1e4d drm/i915/icl: track dbuf slice-2 status
414fb336ac14 drm/i915/icl: program mbus during pipe enable
e6350c1048af drm/i915/icl: initialize MBus during display init
8f3238580058 drm/i915/icl: Enable both DBuf slices during init
dd03b2490169 drm/i915/icl: implement the display init/uninit sequences
9435e5ccf54e drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
b37442b576d0 drm/i915/icl: add the main CDCLK functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7866/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
2018-02-02 16:23 ` Paulo Zanoni
@ 2018-02-02 18:17 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-02-02 18:17 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Fri, Feb 02, 2018 at 02:23:04PM -0200, Paulo Zanoni wrote:
> On ICL we have two sets of registers: one for port A and another for
> port B. The set of port A registers is the same as the CNL registers.
>
> Since the procmon table on ICL is the same we want to reuse the CNL
> function. To do that we add a port argument and make CNL always call
> the function passing port A. This way, we'll be able to easily reuse
> the function on ICL when we add icl_display_core_init().
>
> v2: Don't use _PICK() when you can use a ternary operator.
> v3: Don't use a ternary operation when you can use _MMIO_PORT (Ville).
> Add an extra comment about why we're passing PORT_A (James).
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++++++-------
> 2 files changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 65ba10ad1fe5..f6e1677e8211 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2104,6 +2104,28 @@ enum i915_power_well_id {
> #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
>
> +#define _ICL_PORT_COMP_DW0_A 0x162100
> +#define _ICL_PORT_COMP_DW0_B 0x6C100
> +#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> + _ICL_PORT_COMP_DW0_B)
> +#define _ICL_PORT_COMP_DW1_A 0x162104
> +#define _ICL_PORT_COMP_DW1_B 0x6C104
> +#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> + _ICL_PORT_COMP_DW1_B)
> +#define _ICL_PORT_COMP_DW3_A 0x16210C
> +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> +#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> + _ICL_PORT_COMP_DW3_B)
> +#define _ICL_PORT_COMP_DW9_A 0x162124
> +#define _ICL_PORT_COMP_DW9_B 0x6C124
> +#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> + _ICL_PORT_COMP_DW9_B)
> +#define _ICL_PORT_COMP_DW10_A 0x162128
> +#define _ICL_PORT_COMP_DW10_B 0x6C128
> +#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
> + _ICL_PORT_COMP_DW10_A, \
> + _ICL_PORT_COMP_DW10_B)
> +
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
> #define _PORT_REF_DW3_BC 0x6C18C
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 70e659772a7a..b4ef7875f055 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2794,12 +2794,19 @@ static const struct cnl_procmon {
> { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> };
>
> -static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> +/*
> + * CNL has just one set of registers, while ICL has two sets: one for port A and
> + * the other for port B. The CNL registers are equivalent to the ICL port A
> + * registers, that's why we call the ICL macros even though the function has CNL
> + * on its name.
> + */
> +static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
> + enum port port)
> {
> const struct cnl_procmon *procmon;
> u32 val;
>
> - val = I915_READ(CNL_PORT_COMP_DW3);
> + val = I915_READ(ICL_PORT_COMP_DW3(port));
> switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> default:
> MISSING_CASE(val);
> @@ -2820,13 +2827,13 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> break;
> }
>
> - val = I915_READ(CNL_PORT_COMP_DW1);
> + val = I915_READ(ICL_PORT_COMP_DW1(port));
> val &= ~((0xff << 16) | 0xff);
> val |= procmon->dw1;
> - I915_WRITE(CNL_PORT_COMP_DW1, val);
> + I915_WRITE(ICL_PORT_COMP_DW1(port), val);
>
> - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> }
>
> static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> @@ -2847,7 +2854,8 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> val &= ~CNL_COMP_PWR_DOWN;
> I915_WRITE(CHICKEN_MISC_2, val);
>
> - cnl_set_procmon_ref_values(dev_priv);
> + /* Dummy PORT_A to get the correct CNL register from the ICL macro */
> + cnl_set_procmon_ref_values(dev_priv, PORT_A);
>
> val = I915_READ(CNL_PORT_COMP_DW0);
> val |= COMP_INIT;
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
2018-01-26 23:14 ` James Ausmus
2018-01-29 10:51 ` Imre Deak
@ 2018-02-02 19:57 ` Paulo Zanoni
2018-02-02 22:12 ` James Ausmus
2 siblings, 1 reply; 59+ messages in thread
From: Paulo Zanoni @ 2018-02-02 19:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.
v2:
- Implement the voltage levels.
- Rebase.
v3:
- Adjust to the new "bypass" clock (Imre).
- Call intel_dump_cdclk_state() too.
- Rename a variable to avoid confusion.
- Simplify the DVFS part.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
drivers/gpu/drm/i915/intel_cdclk.c | 235 ++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 243 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6e1677e8211..856e88c6ee97 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7182,8 +7182,12 @@ enum {
#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
-#define SKL_DSSM _MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
+#define SKL_DSSM _MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
@@ -8831,6 +8835,8 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
+#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
+#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
/* LCPLL_CTL */
#define LCPLL1_CTL _MMIO(0x46010)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ee788d5be5e3..52a15d0eaae9 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1778,6 +1778,197 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
dev_priv->cdclk.hw.vco = -1;
}
+static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
+{
+ int ranges_24[] = { 312000, 552000, 648000 };
+ int ranges_19_38[] = { 307200, 556800, 652800 };
+ int *ranges;
+
+ switch (ref) {
+ default:
+ MISSING_CASE(ref);
+ case 24000:
+ ranges = ranges_24;
+ break;
+ case 19200:
+ case 38400:
+ ranges = ranges_19_38;
+ break;
+ }
+
+ if (min_cdclk > ranges[1])
+ return ranges[2];
+ else if (min_cdclk > ranges[0])
+ return ranges[1];
+ else
+ return ranges[0];
+}
+
+static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+ int ratio;
+
+ if (cdclk == dev_priv->cdclk.hw.bypass)
+ return 0;
+
+ switch (cdclk) {
+ default:
+ MISSING_CASE(cdclk);
+ case 307200:
+ case 556800:
+ case 652800:
+ WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
+ dev_priv->cdclk.hw.ref != 38400);
+ break;
+ case 312000:
+ case 552000:
+ case 648000:
+ WARN_ON(dev_priv->cdclk.hw.ref != 24000);
+ }
+
+ ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
+
+ return dev_priv->cdclk.hw.ref * ratio;
+}
+
+static void icl_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *cdclk_state)
+{
+ unsigned int cdclk = cdclk_state->cdclk;
+ unsigned int vco = cdclk_state->vco;
+ int ret;
+
+ mutex_lock(&dev_priv->pcu_lock);
+ ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
+ mutex_unlock(&dev_priv->pcu_lock);
+ if (ret) {
+ DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+ ret);
+ return;
+ }
+
+ if (dev_priv->cdclk.hw.vco != 0 &&
+ dev_priv->cdclk.hw.vco != vco)
+ cnl_cdclk_pll_disable(dev_priv);
+
+ if (dev_priv->cdclk.hw.vco != vco)
+ cnl_cdclk_pll_enable(dev_priv, vco);
+
+ I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
+ skl_cdclk_decimal(cdclk));
+
+ mutex_lock(&dev_priv->pcu_lock);
+ /* TODO: add proper DVFS support. */
+ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
+ mutex_unlock(&dev_priv->pcu_lock);
+
+ intel_update_cdclk(dev_priv);
+}
+
+static void icl_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state *cdclk_state)
+{
+ u32 val;
+
+ cdclk_state->bypass = 50000;
+
+ val = I915_READ(SKL_DSSM);
+ switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
+ default:
+ MISSING_CASE(val);
+ case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
+ cdclk_state->ref = 24000;
+ break;
+ case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
+ cdclk_state->ref = 19200;
+ break;
+ case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
+ cdclk_state->ref = 38400;
+ break;
+ }
+
+ val = I915_READ(BXT_DE_PLL_ENABLE);
+ if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
+ (val & BXT_DE_PLL_LOCK) == 0) {
+ /* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
+ * setting it to zero is a way to signal that. */
+ cdclk_state->vco = 0;
+ cdclk_state->cdclk = cdclk_state->bypass;
+ return;
+ }
+
+ cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
+
+ val = I915_READ(CDCLK_CTL);
+ WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
+
+ cdclk_state->cdclk = cdclk_state->vco / 2;
+}
+
+/**
+ * icl_init_cdclk - Initialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Initialize CDCLK for ICL. This consists mainly of initializing
+ * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
+ * is generally done only during the display core initialization sequence, after
+ * which the DMC will take care of turning CDCLK off/on as needed.
+ */
+void icl_init_cdclk(struct drm_i915_private *dev_priv)
+{
+ struct intel_cdclk_state sanitized_state;
+ u32 val;
+
+ /* This sets dev_priv->cdclk.hw. */
+ intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+
+ /* This means CDCLK disabled. */
+ if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ goto sanitize;
+
+ val = I915_READ(CDCLK_CTL);
+
+ if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
+ goto sanitize;
+
+ if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
+ skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
+ goto sanitize;
+
+ return;
+
+sanitize:
+ DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
+
+ sanitized_state.ref = dev_priv->cdclk.hw.ref;
+ sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
+ sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
+ sanitized_state.cdclk);
+
+ icl_set_cdclk(dev_priv, &sanitized_state);
+}
+
+/**
+ * icl_uninit_cdclk - Uninitialize CDCLK on ICL
+ * @dev_priv: i915 device
+ *
+ * Uninitialize CDCLK for ICL. This is done only during the display core
+ * uninitialization sequence.
+ */
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
+{
+ struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+
+ cdclk_state.cdclk = cdclk_state.bypass;
+ cdclk_state.vco = 0;
+
+ icl_set_cdclk(dev_priv, &cdclk_state);
+}
+
/**
* cnl_init_cdclk - Initialize CDCLK on CNL
* @dev_priv: i915 device
@@ -2216,6 +2407,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
return 0;
}
+static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ unsigned int ref = intel_state->cdclk.logical.ref;
+ int min_cdclk, cdclk, vco;
+
+ min_cdclk = intel_compute_min_cdclk(state);
+ if (min_cdclk < 0)
+ return min_cdclk;
+
+ cdclk = icl_calc_cdclk(min_cdclk, ref);
+ vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+ intel_state->cdclk.logical.vco = vco;
+ intel_state->cdclk.logical.cdclk = cdclk;
+
+ if (!intel_state->active_crtcs) {
+ cdclk = icl_calc_cdclk(0, ref);
+ vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
+
+ intel_state->cdclk.actual.vco = vco;
+ intel_state->cdclk.actual.cdclk = cdclk;
+ } else {
+ intel_state->cdclk.actual = intel_state->cdclk.logical;
+ }
+
+ return 0;
+}
+
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
int max_cdclk_freq = dev_priv->max_cdclk_freq;
@@ -2249,7 +2470,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ if (dev_priv->cdclk.hw.ref == 24000)
+ dev_priv->max_cdclk_freq = 648000;
+ else
+ dev_priv->max_cdclk_freq = 652800;
+ } else if (IS_CANNONLAKE(dev_priv)) {
dev_priv->max_cdclk_freq = 528000;
} else if (IS_GEN9_BC(dev_priv)) {
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
@@ -2473,9 +2699,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.set_cdclk = cnl_set_cdclk;
dev_priv->display.modeset_calc_cdclk =
cnl_modeset_calc_cdclk;
+ } else if (IS_ICELAKE(dev_priv)) {
+ dev_priv->display.set_cdclk = icl_set_cdclk;
+ dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
}
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.get_cdclk = icl_get_cdclk;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.get_cdclk = cnl_get_cdclk;
else if (IS_GEN9_BC(dev_priv))
dev_priv->display.get_cdclk = skl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d6a808374dfb..cca7ecae5cce 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
+void icl_init_cdclk(struct drm_i915_private *dev_priv);
+void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
--
2.14.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev5)
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
` (21 preceding siblings ...)
2018-02-02 17:28 ` Patchwork
@ 2018-02-02 20:22 ` Patchwork
22 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-02-02 20:22 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: ICL display initialization and some plane bits (rev5)
URL : https://patchwork.freedesktop.org/series/36993/
State : failure
== Summary ==
Series 36993v5 ICL display initialization and some plane bits
https://patchwork.freedesktop.org/api/1.0/series/36993/revisions/5/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6700hq) fdo#101144 +2
pass -> FAIL (fi-skl-6700k2) fdo#103191 +3
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2)
Subgroup suspend-read-crc-pipe-b:
pass -> FAIL (fi-skl-6260u)
pass -> FAIL (fi-skl-6600u)
pass -> FAIL (fi-skl-6770hq)
pass -> FAIL (fi-skl-gvtdvm)
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
pass -> FAIL (fi-cfl-s2) k.org#197971 +1
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-6260u) fdo#104108 +4
pass -> FAIL (fi-bxt-dsi)
pass -> FAIL (fi-bxt-j4205)
pass -> FAIL (fi-kbl-7500u)
pass -> FAIL (fi-kbl-7560u)
pass -> FAIL (fi-kbl-7567u)
pass -> FAIL (fi-kbl-r)
pass -> FAIL (fi-glk-1)
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
k.org#197971 https://bugzilla.kernel.org/show_bug.cgi?id=197971
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:417s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:424s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:369s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:482s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:480s
fi-bxt-j4205 total:288 pass:256 dwarn:0 dfail:0 fail:3 skip:29 time:483s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:465s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:454s
fi-cfl-s2 total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:569s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:412s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:279s
fi-glk-1 total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:518s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:387s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:396s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:413s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:457s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:419s
fi-kbl-7500u total:288 pass:260 dwarn:1 dfail:0 fail:3 skip:24 time:460s
fi-kbl-7560u total:288 pass:266 dwarn:0 dfail:0 fail:3 skip:19 time:505s
fi-kbl-7567u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:452s
fi-kbl-r total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:512s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:568s
fi-skl-6260u total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:425s
fi-skl-6600u total:288 pass:258 dwarn:0 dfail:0 fail:3 skip:27 time:516s
fi-skl-6700hq total:288 pass:259 dwarn:0 dfail:0 fail:3 skip:26 time:540s
fi-skl-6700k2 total:288 pass:261 dwarn:0 dfail:0 fail:3 skip:24 time:484s
fi-skl-6770hq total:288 pass:265 dwarn:0 dfail:0 fail:3 skip:20 time:470s
fi-skl-guc total:288 pass:257 dwarn:0 dfail:0 fail:3 skip:28 time:414s
fi-skl-gvtdvm total:288 pass:262 dwarn:0 dfail:0 fail:3 skip:23 time:430s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:521s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:392s
Blacklisted hosts:
fi-glk-dsi total:288 pass:255 dwarn:0 dfail:0 fail:3 skip:30 time:465s
c051d09ed8f4b307b8d00076380e657759bd8eb5 drm-tip: 2018y-02m-02d-19h-34m-35s UTC integration manifest
c3f9403c6edf drm/i915/icl: enable SAGV for ICL platform
66bf28002026 drm/i915/icl: update ddb entry start/end mask during hw ddb readout
5cb8daf886fc drm/i915/icl: Enable 2nd DBuf slice only when needed
50c7e0af9eff drm/i915/icl: track dbuf slice-2 status
8231bcdf2ebd drm/i915/icl: program mbus during pipe enable
4bef42e6db7b drm/i915/icl: initialize MBus during display init
1d2db0973594 drm/i915/icl: Enable both DBuf slices during init
cb85f1cc1761 drm/i915/icl: implement the display init/uninit sequences
d64592b6fe36 drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
8dced1a345b7 drm/i915/icl: add the main CDCLK functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7868/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 01/17] drm/i915/icl: add the main CDCLK functions
2018-02-02 19:57 ` Paulo Zanoni
@ 2018-02-02 22:12 ` James Ausmus
0 siblings, 0 replies; 59+ messages in thread
From: James Ausmus @ 2018-02-02 22:12 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Fri, Feb 02, 2018 at 05:57:02PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
>
> v2:
> - Implement the voltage levels.
> - Rebase.
> v3:
> - Adjust to the new "bypass" clock (Imre).
> - Call intel_dump_cdclk_state() too.
> - Rename a variable to avoid confusion.
> - Simplify the DVFS part.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +-
> drivers/gpu/drm/i915/intel_cdclk.c | 235 ++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 243 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6e1677e8211..856e88c6ee97 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7182,8 +7182,12 @@ enum {
> #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
>
> -#define SKL_DSSM _MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define SKL_DSSM _MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
>
> #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
> @@ -8831,6 +8835,8 @@ enum skl_power_gate {
> #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
> #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> +#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
This is still wrong :)
> +#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
>
> /* LCPLL_CTL */
> #define LCPLL1_CTL _MMIO(0x46010)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ee788d5be5e3..52a15d0eaae9 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1778,6 +1778,197 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco = -1;
> }
>
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> + int ranges_24[] = { 312000, 552000, 648000 };
> + int ranges_19_38[] = { 307200, 556800, 652800 };
> + int *ranges;
> +
> + switch (ref) {
> + default:
> + MISSING_CASE(ref);
> + case 24000:
> + ranges = ranges_24;
> + break;
> + case 19200:
> + case 38400:
> + ranges = ranges_19_38;
> + break;
> + }
> +
> + if (min_cdclk > ranges[1])
> + return ranges[2];
> + else if (min_cdclk > ranges[0])
> + return ranges[1];
> + else
> + return ranges[0];
> +}
> +
> +static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> + int ratio;
> +
> + if (cdclk == dev_priv->cdclk.hw.bypass)
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case 307200:
> + case 556800:
> + case 652800:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400);
> + break;
> + case 312000:
> + case 552000:
> + case 648000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + }
> +
> + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> +
> + return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_state *cdclk_state)
> +{
> + unsigned int cdclk = cdclk_state->cdclk;
> + unsigned int vco = cdclk_state->vco;
> + int ret;
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + mutex_unlock(&dev_priv->pcu_lock);
> + if (ret) {
> + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> + ret);
> + return;
> + }
> +
> + if (dev_priv->cdclk.hw.vco != 0 &&
> + dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_disable(dev_priv);
> +
> + if (dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_enable(dev_priv, vco);
> +
> + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> + skl_cdclk_decimal(cdclk));
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + /* TODO: add proper DVFS support. */
> + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
> + mutex_unlock(&dev_priv->pcu_lock);
> +
> + intel_update_cdclk(dev_priv);
> +}
> +
> +static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> + struct intel_cdclk_state *cdclk_state)
> +{
> + u32 val;
> +
> + cdclk_state->bypass = 50000;
> +
> + val = I915_READ(SKL_DSSM);
> + switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> + default:
> + MISSING_CASE(val);
> + case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
> + cdclk_state->ref = 24000;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
> + cdclk_state->ref = 19200;
> + break;
> + case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
> + cdclk_state->ref = 38400;
> + break;
> + }
> +
> + val = I915_READ(BXT_DE_PLL_ENABLE);
> + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> + (val & BXT_DE_PLL_LOCK) == 0) {
> + /* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
> + * setting it to zero is a way to signal that. */
> + cdclk_state->vco = 0;
> + cdclk_state->cdclk = cdclk_state->bypass;
> + return;
> + }
> +
> + cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> +
> + val = I915_READ(CDCLK_CTL);
> + WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
> +
> + cdclk_state->cdclk = cdclk_state->vco / 2;
> +}
> +
> +/**
> + * icl_init_cdclk - Initialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Initialize CDCLK for ICL. This consists mainly of initializing
> + * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
> + * is generally done only during the display core initialization sequence, after
> + * which the DMC will take care of turning CDCLK off/on as needed.
> + */
> +void icl_init_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state sanitized_state;
> + u32 val;
> +
> + /* This sets dev_priv->cdclk.hw. */
> + intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> +
> + /* This means CDCLK disabled. */
> + if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> + goto sanitize;
> +
> + val = I915_READ(CDCLK_CTL);
> +
> + if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
> + goto sanitize;
> +
> + if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
> + skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
> + goto sanitize;
> +
> + return;
> +
> +sanitize:
> + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> +
> + sanitized_state.ref = dev_priv->cdclk.hw.ref;
> + sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> + sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> + sanitized_state.cdclk);
> +
> + icl_set_cdclk(dev_priv, &sanitized_state);
> +}
> +
> +/**
> + * icl_uninit_cdclk - Uninitialize CDCLK on ICL
> + * @dev_priv: i915 device
> + *
> + * Uninitialize CDCLK for ICL. This is done only during the display core
> + * uninitialization sequence.
> + */
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> + cdclk_state.cdclk = cdclk_state.bypass;
> + cdclk_state.vco = 0;
> +
> + icl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
> /**
> * cnl_init_cdclk - Initialize CDCLK on CNL
> * @dev_priv: i915 device
> @@ -2216,6 +2407,36 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> return 0;
> }
>
> +static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + unsigned int ref = intel_state->cdclk.logical.ref;
> + int min_cdclk, cdclk, vco;
> +
> + min_cdclk = intel_compute_min_cdclk(state);
> + if (min_cdclk < 0)
> + return min_cdclk;
> +
> + cdclk = icl_calc_cdclk(min_cdclk, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.logical.vco = vco;
> + intel_state->cdclk.logical.cdclk = cdclk;
> +
> + if (!intel_state->active_crtcs) {
> + cdclk = icl_calc_cdclk(0, ref);
> + vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> +
> + intel_state->cdclk.actual.vco = vco;
> + intel_state->cdclk.actual.cdclk = cdclk;
> + } else {
> + intel_state->cdclk.actual = intel_state->cdclk.logical;
> + }
> +
> + return 0;
> +}
> +
> static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> {
> int max_cdclk_freq = dev_priv->max_cdclk_freq;
> @@ -2249,7 +2470,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> */
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + if (dev_priv->cdclk.hw.ref == 24000)
> + dev_priv->max_cdclk_freq = 648000;
> + else
> + dev_priv->max_cdclk_freq = 652800;
> + } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 528000;
> } else if (IS_GEN9_BC(dev_priv)) {
> u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> @@ -2473,9 +2699,14 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.set_cdclk = cnl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> cnl_modeset_calc_cdclk;
> + } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.set_cdclk = icl_set_cdclk;
> + dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> }
>
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + dev_priv->display.get_cdclk = icl_get_cdclk;
> + else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.get_cdclk = cnl_get_cdclk;
> else if (IS_GEN9_BC(dev_priv))
> dev_priv->display.get_cdclk = skl_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d6a808374dfb..cca7ecae5cce 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1403,6 +1403,8 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
> void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void icl_init_cdclk(struct drm_i915_private *dev_priv);
> +void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> --
> 2.14.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 2/2] drm/i915/icl: Enable 2nd DBuf slice only when needed
2018-01-23 19:05 ` [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed Paulo Zanoni
2018-01-25 22:56 ` James Ausmus
@ 2018-03-14 16:19 ` Mahesh Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Mahesh Kumar @ 2018-03-14 16:19 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
ICL has two slices of DBuf, each slice of size 1024 blocks.
We should not always enable slice-2. It should be enabled only if
display total required BW is > 12GBps OR more than 1 pipes are enabled.
Changes since V1:
- typecast total_data_rate to u64 before multiplication to solve any
possible overflow (Rodrigo)
- fix where skl_wm_get_hw_state was memsetting ddb, resulting
enabled_slices to become zero
- Fix the logic of calculating ddb_size
Changes since V2:
- If no-crtc is part of commit required_slices will have value "0",
don't try to disable DBuf slice.
Changes since V3:
- Create a generic helper to enable/disable slice
- don't return early if total_data_rate is 0, it may be cursor only
commit, or atomic modeset without any plane.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 +++++
drivers/gpu/drm/i915/intel_drv.h | 6 +++
drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++++++++++++++++------
drivers/gpu/drm/i915/intel_runtime_pm.c | 65 ++++++++++++++++++++++++++-------
4 files changed, 113 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e1771cac75d3..f7e606db239d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12198,6 +12198,8 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
bool progress;
enum pipe pipe;
int i;
+ uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ uint8_t required_slices = intel_state->wm_results.ddb.enabled_slices;
const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
@@ -12206,6 +12208,10 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
if (new_crtc_state->active)
entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
+ /* If 2nd DBuf slice required, enable it here */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
@@ -12256,6 +12262,10 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
progress = true;
}
} while (progress);
+
+ /* If 2nd DBuf slice is no more required disable it */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
}
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a215aa78b0be..dfb6b5665031 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -140,6 +140,10 @@
#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
+#define KBps(x) (1000 * (x))
+#define MBps(x) KBps(1000 * (x))
+#define GBps(x) ((uint64_t) 1000 * MBps((x)))
+
/*
* Display related stuff
*/
@@ -1910,6 +1914,8 @@ bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
+void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+ uint8_t req_slices);
static inline void
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1d331f505f44..bb304c019163 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3771,9 +3771,42 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
return true;
}
+static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *cstate,
+ const unsigned int total_data_rate,
+ const int num_active,
+ struct skl_ddb_allocation *ddb)
+{
+ const struct drm_display_mode *adjusted_mode;
+ u64 total_data_bw;
+ u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+
+ WARN_ON(ddb_size == 0);
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return ddb_size - 4; /* 4 blocks for bypass path allocation */
+
+ adjusted_mode = &cstate->base.adjusted_mode;
+ total_data_bw = (u64)total_data_rate * drm_mode_vrefresh(adjusted_mode);
+
+ /*
+ * 12GB/s is maximum BW supported by single DBuf slice.
+ */
+ if (total_data_bw >= GBps(12) || num_active > 1)
+ ddb->enabled_slices = 2;
+ else {
+ ddb->enabled_slices = 1;
+ ddb_size /= 2;
+ }
+
+ return ddb_size;
+}
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
const struct intel_crtc_state *cstate,
+ const unsigned int total_data_rate,
+ struct skl_ddb_allocation *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
@@ -3796,11 +3829,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
- ddb_size = INTEL_INFO(dev_priv)->ddb_size;
- WARN_ON(ddb_size == 0);
-
- if (INTEL_GEN(dev_priv) < 11)
- ddb_size -= 4; /* 4 blocks for bypass path allocation */
+ ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,
+ *num_active, ddb);
/*
* If the state doesn't change the active CRTC's, then there's
@@ -4239,7 +4269,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
return 0;
}
- skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
+ total_data_rate = skl_get_total_relative_data_rate(cstate,
+ plane_data_rate,
+ plane_y_data_rate);
+ skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,
+ alloc, &num_active);
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0)
return 0;
@@ -4274,9 +4308,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*
* FIXME: we may not allocate every single block here.
*/
- total_data_rate = skl_get_total_relative_data_rate(cstate,
- plane_data_rate,
- plane_y_data_rate);
if (total_data_rate == 0)
return 0;
@@ -5069,7 +5100,6 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
sizeof(dst->ddb.y_plane[pipe]));
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
sizeof(dst->ddb.plane[pipe]));
- dst->ddb.enabled_slices = src->ddb.enabled_slices;
}
static void
@@ -5382,8 +5412,12 @@ void skl_wm_get_hw_state(struct drm_device *dev)
/* Fully recompute DDB on first atomic commit */
dev_priv->wm.distrust_bios_wm = true;
} else {
- /* Easy/common case; just sanitize DDB now if everything off */
- memset(ddb, 0, sizeof(*ddb));
+ /*
+ * Easy/common case; just sanitize DDB now if everything off
+ * Keep dbuf slice info intact
+ */
+ memset(ddb->plane, 0, sizeof(ddb->plane));
+ memset(ddb->y_plane, 0, sizeof(ddb->y_plane));
}
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 58be542d660b..56cdec06e6b2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2627,32 +2627,69 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
mutex_unlock(&power_domains->lock);
}
-static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
+static inline
+bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
+ i915_reg_t reg, bool enable)
{
- I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL);
+ u32 val, status;
+ val = I915_READ(reg);
+ val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST);
+ I915_WRITE(reg, val);
+ POSTING_READ(reg);
udelay(10);
- if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power enable timeout\n");
+ status = I915_READ(reg) & DBUF_POWER_STATE;
+ if ((enable && !status) || (!enable && status)) {
+ DRM_ERROR("DBus power %s timeout!\n",
+ enable ? "enable" : "disable");
+ return false;
+ }
+ return true;
+}
+
+static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
+{
+ intel_dbuf_slice_set(dev_priv, DBUF_CTL, true);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL);
+ intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
+}
- udelay(10);
+static uint8_t intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_GEN(dev_priv) < 11)
+ return 1;
+ return 2;
+}
- if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
- DRM_ERROR("DBuf power disable timeout!\n");
+void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+ uint8_t req_slices)
+{
+ uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ u32 val;
+ bool ret;
+
+ if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+ DRM_ERROR("Invalid number of dbuf slices requested\n");
+ return;
+ }
+
+ if (req_slices == hw_enabled_slices || req_slices == 0)
+ return;
+
+ val = I915_READ(DBUF_CTL_S2);
+ if (req_slices > hw_enabled_slices)
+ ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
+ else
+ ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+
+ if (ret)
+ dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
}
-/*
- * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
- * needed and keep it disabled as much as possible.
- */
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
end of thread, other threads:[~2018-03-14 16:18 UTC | newest]
Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
2018-01-26 23:14 ` James Ausmus
2018-02-01 20:09 ` Paulo Zanoni
2018-01-29 10:51 ` Imre Deak
2018-02-01 20:08 ` Paulo Zanoni
2018-02-01 20:40 ` Imre Deak
2018-02-02 19:57 ` Paulo Zanoni
2018-02-02 22:12 ` James Ausmus
2018-01-23 19:05 ` [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Paulo Zanoni
2018-01-24 0:32 ` James Ausmus
2018-01-26 20:24 ` Paulo Zanoni
2018-01-26 20:47 ` James Ausmus
2018-01-26 20:33 ` Ville Syrjälä
2018-02-02 16:23 ` Paulo Zanoni
2018-02-02 18:17 ` James Ausmus
2018-01-23 19:05 ` [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences Paulo Zanoni
2018-01-26 23:25 ` James Ausmus
2018-01-23 19:05 ` [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init Paulo Zanoni
2018-01-24 0:49 ` James Ausmus
2018-01-26 20:50 ` Paulo Zanoni
2018-01-29 17:47 ` Paulo Zanoni
2018-01-23 19:05 ` [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
2018-01-24 0:58 ` James Ausmus
2018-01-23 19:05 ` [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
2018-01-24 1:14 ` James Ausmus
2018-01-29 23:07 ` Paulo Zanoni
2018-01-29 23:32 ` James Ausmus
2018-01-23 19:05 ` [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
2018-01-26 23:50 ` James Ausmus
2018-01-29 18:16 ` Paulo Zanoni
2018-01-29 23:08 ` [PATCH 07/13] " Paulo Zanoni
2018-01-23 19:05 ` [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
2018-01-25 22:31 ` James Ausmus
2018-01-23 19:05 ` [PATCH 09/17] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
2018-01-25 22:38 ` James Ausmus
2018-01-23 19:05 ` [PATCH 10/17] drm/i915/icl: initialize MBus during display init Paulo Zanoni
2018-01-25 22:39 ` James Ausmus
2018-01-23 19:05 ` [PATCH 11/17] drm/i915/icl: program mbus during pipe enable Paulo Zanoni
2018-01-25 22:42 ` James Ausmus
2018-01-23 19:05 ` [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status Paulo Zanoni
2018-01-25 23:08 ` James Ausmus
2018-01-23 19:05 ` [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed Paulo Zanoni
2018-01-25 22:56 ` James Ausmus
2018-03-14 16:19 ` [PATCH 2/2] " Mahesh Kumar
2018-01-23 19:05 ` [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout Paulo Zanoni
2018-01-25 23:00 ` James Ausmus
2018-01-23 19:05 ` [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
2018-01-25 23:09 ` James Ausmus
2018-01-23 19:05 ` [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform Paulo Zanoni
2018-01-25 23:09 ` James Ausmus
2018-01-29 22:07 ` Paulo Zanoni
2018-01-23 19:05 ` [PATCH 17/17] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field Paulo Zanoni
2018-01-23 19:32 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits Patchwork
2018-01-23 20:32 ` Patchwork
2018-01-29 23:27 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev2) Patchwork
2018-02-02 17:10 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev4) Patchwork
2018-02-02 17:28 ` Patchwork
2018-02-02 20:22 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev5) Patchwork
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