* [PATCH v4 2/2] x86/apic: Replace common tools with new ones
2018-02-26 2:39 [PATCH v4 1/2] x86/apic: Move pending intr check code into it's own function Dou Liyang
@ 2018-02-26 2:39 ` Dou Liyang
2018-02-26 11:50 ` Andy Shevchenko
2018-02-28 14:13 ` [tip:x86/apic] " tip-bot for Dou Liyang
2018-02-26 14:52 ` [PATCH v4 1/2] x86/apic: Move pending intr check code into it's own function Andy Shevchenko
2018-02-28 14:12 ` [tip:x86/apic] " tip-bot for Dou Liyang
2 siblings, 2 replies; 6+ messages in thread
From: Dou Liyang @ 2018-02-26 2:39 UTC (permalink / raw)
To: linux-kernel, x86; +Cc: tglx, mingo, ebiederm, bhe, andy.shevchenko, Dou Liyang
The pending interrupt check code is old, update the following.
-Replace for-if pair with for_each_set_bit()
-Replace printk() with pr_err()
Also merge the printk's code in one line and make curly braces balanced
Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
---
changlog:
v3 --> v4:
-Fix the wrong check for bit 0 suggested by Andy
arch/x86/kernel/apic/apic.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index be223ebd1bb3..81db2aab257b 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1412,7 +1412,8 @@ static void apic_pending_intr_clear(void)
{
long long max_loops = cpu_khz ? cpu_khz : 1000000;
unsigned long long tsc = 0, ntsc;
- unsigned int value, queued;
+ unsigned int queued;
+ unsigned long value;
int i, j, acked = 0;
if (boot_cpu_has(X86_FEATURE_TSC))
@@ -1435,24 +1436,22 @@ static void apic_pending_intr_clear(void)
for (i = APIC_ISR_NR - 1; i >= 0; i--) {
value = apic_read(APIC_ISR + i*0x10);
- for (j = 31; j >= 0; j--) {
- if (value & (1<<j)) {
- ack_APIC_irq();
- acked++;
- }
+ for_each_set_bit(j, &value, 32) {
+ ack_APIC_irq();
+ acked++;
}
}
if (acked > 256) {
- printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
- acked);
+ pr_err("LAPIC pending interrupts after %d EOI\n", acked);
break;
}
if (queued) {
if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
ntsc = rdtsc();
max_loops = (cpu_khz << 10) - (ntsc - tsc);
- } else
+ } else {
max_loops--;
+ }
}
} while (queued && max_loops > 0);
WARN_ON(max_loops <= 0);
--
2.14.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v4 2/2] x86/apic: Replace common tools with new ones
2018-02-26 2:39 ` [PATCH v4 2/2] x86/apic: Replace common tools with new ones Dou Liyang
@ 2018-02-26 11:50 ` Andy Shevchenko
2018-02-28 14:13 ` [tip:x86/apic] " tip-bot for Dou Liyang
1 sibling, 0 replies; 6+ messages in thread
From: Andy Shevchenko @ 2018-02-26 11:50 UTC (permalink / raw)
To: Dou Liyang
Cc: Linux Kernel Mailing List, x86, Thomas Gleixner, Ingo Molnar,
ebiederm, Baoquan He
On Mon, Feb 26, 2018 at 4:39 AM, Dou Liyang <douly.fnst@cn.fujitsu.com> wrote:
> The pending interrupt check code is old, update the following.
>
> -Replace for-if pair with for_each_set_bit()
> -Replace printk() with pr_err()
>
> Also merge the printk's code in one line and make curly braces balanced
>
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
> ---
> changlog:
> v3 --> v4:
> -Fix the wrong check for bit 0 suggested by Andy
>
> arch/x86/kernel/apic/apic.c | 17 ++++++++---------
> 1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index be223ebd1bb3..81db2aab257b 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -1412,7 +1412,8 @@ static void apic_pending_intr_clear(void)
> {
> long long max_loops = cpu_khz ? cpu_khz : 1000000;
> unsigned long long tsc = 0, ntsc;
> - unsigned int value, queued;
> + unsigned int queued;
> + unsigned long value;
> int i, j, acked = 0;
>
> if (boot_cpu_has(X86_FEATURE_TSC))
> @@ -1435,24 +1436,22 @@ static void apic_pending_intr_clear(void)
>
> for (i = APIC_ISR_NR - 1; i >= 0; i--) {
> value = apic_read(APIC_ISR + i*0x10);
> - for (j = 31; j >= 0; j--) {
> - if (value & (1<<j)) {
> - ack_APIC_irq();
> - acked++;
> - }
> + for_each_set_bit(j, &value, 32) {
> + ack_APIC_irq();
> + acked++;
> }
> }
> if (acked > 256) {
> - printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
> - acked);
> + pr_err("LAPIC pending interrupts after %d EOI\n", acked);
> break;
> }
> if (queued) {
> if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
> ntsc = rdtsc();
> max_loops = (cpu_khz << 10) - (ntsc - tsc);
> - } else
> + } else {
> max_loops--;
> + }
> }
> } while (queued && max_loops > 0);
> WARN_ON(max_loops <= 0);
> --
> 2.14.3
>
>
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 6+ messages in thread* [tip:x86/apic] x86/apic: Replace common tools with new ones
2018-02-26 2:39 ` [PATCH v4 2/2] x86/apic: Replace common tools with new ones Dou Liyang
2018-02-26 11:50 ` Andy Shevchenko
@ 2018-02-28 14:13 ` tip-bot for Dou Liyang
1 sibling, 0 replies; 6+ messages in thread
From: tip-bot for Dou Liyang @ 2018-02-28 14:13 UTC (permalink / raw)
To: linux-tip-commits
Cc: andy.shevchenko, hpa, mingo, linux-kernel, tglx, douly.fnst
Commit-ID: ea5dfef5a890c9e6e47bdddfc23c4a4ba0c1bea1
Gitweb: https://git.kernel.org/tip/ea5dfef5a890c9e6e47bdddfc23c4a4ba0c1bea1
Author: Dou Liyang <douly.fnst@cn.fujitsu.com>
AuthorDate: Mon, 26 Feb 2018 10:39:57 +0800
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 28 Feb 2018 15:09:11 +0100
x86/apic: Replace common tools with new ones
The pending interrupt check code is old, update the following.
-Replace for-if pair with for_each_set_bit()
-Replace printk() with pr_err()
Also merge the printk's code in one line and make curly braces balanced
Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: bhe@redhat.com
Cc: ebiederm@xmission.com
Link: https://lkml.kernel.org/r/20180226023957.22861-2-douly.fnst@cn.fujitsu.com
---
arch/x86/kernel/apic/apic.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 3fda9734db25..4704a3541b11 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1412,7 +1412,8 @@ static void apic_pending_intr_clear(void)
{
long long max_loops = cpu_khz ? cpu_khz : 1000000;
unsigned long long tsc = 0, ntsc;
- unsigned int value, queued;
+ unsigned int queued;
+ unsigned long value;
int i, j, acked = 0;
if (boot_cpu_has(X86_FEATURE_TSC))
@@ -1435,24 +1436,22 @@ static void apic_pending_intr_clear(void)
for (i = APIC_ISR_NR - 1; i >= 0; i--) {
value = apic_read(APIC_ISR + i*0x10);
- for (j = 31; j >= 0; j--) {
- if (value & (1<<j)) {
- ack_APIC_irq();
- acked++;
- }
+ for_each_set_bit(j, &value, 32) {
+ ack_APIC_irq();
+ acked++;
}
}
if (acked > 256) {
- printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
- acked);
+ pr_err("LAPIC pending interrupts after %d EOI\n", acked);
break;
}
if (queued) {
if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
ntsc = rdtsc();
max_loops = (cpu_khz << 10) - (ntsc - tsc);
- } else
+ } else {
max_loops--;
+ }
}
} while (queued && max_loops > 0);
WARN_ON(max_loops <= 0);
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] x86/apic: Move pending intr check code into it's own function
2018-02-26 2:39 [PATCH v4 1/2] x86/apic: Move pending intr check code into it's own function Dou Liyang
2018-02-26 2:39 ` [PATCH v4 2/2] x86/apic: Replace common tools with new ones Dou Liyang
@ 2018-02-26 14:52 ` Andy Shevchenko
2018-02-28 14:12 ` [tip:x86/apic] " tip-bot for Dou Liyang
2 siblings, 0 replies; 6+ messages in thread
From: Andy Shevchenko @ 2018-02-26 14:52 UTC (permalink / raw)
To: Dou Liyang
Cc: Linux Kernel Mailing List, x86, Thomas Gleixner, Ingo Molnar,
ebiederm, Baoquan He
On Mon, Feb 26, 2018 at 4:39 AM, Dou Liyang <douly.fnst@cn.fujitsu.com> wrote:
> the pending interrupt check code is mixed with the local APIC setup code,
> that looks messy.
>
> Extract the related code, move it into a new function named
> apic_pending_intr_clear().
FWIW,
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
>
> Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
> ---
> arch/x86/kernel/apic/apic.c | 98 ++++++++++++++++++++++++---------------------
> 1 file changed, 52 insertions(+), 46 deletions(-)
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index 84b244ec49ed..be223ebd1bb3 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -1408,6 +1408,56 @@ static void lapic_setup_esr(void)
> oldvalue, value);
> }
>
> +static void apic_pending_intr_clear(void)
> +{
> + long long max_loops = cpu_khz ? cpu_khz : 1000000;
> + unsigned long long tsc = 0, ntsc;
> + unsigned int value, queued;
> + int i, j, acked = 0;
> +
> + if (boot_cpu_has(X86_FEATURE_TSC))
> + tsc = rdtsc();
> + /*
> + * After a crash, we no longer service the interrupts and a pending
> + * interrupt from previous kernel might still have ISR bit set.
> + *
> + * Most probably by now CPU has serviced that pending interrupt and
> + * it might not have done the ack_APIC_irq() because it thought,
> + * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
> + * does not clear the ISR bit and cpu thinks it has already serivced
> + * the interrupt. Hence a vector might get locked. It was noticed
> + * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
> + */
> + do {
> + queued = 0;
> + for (i = APIC_ISR_NR - 1; i >= 0; i--)
> + queued |= apic_read(APIC_IRR + i*0x10);
> +
> + for (i = APIC_ISR_NR - 1; i >= 0; i--) {
> + value = apic_read(APIC_ISR + i*0x10);
> + for (j = 31; j >= 0; j--) {
> + if (value & (1<<j)) {
> + ack_APIC_irq();
> + acked++;
> + }
> + }
> + }
> + if (acked > 256) {
> + printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
> + acked);
> + break;
> + }
> + if (queued) {
> + if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
> + ntsc = rdtsc();
> + max_loops = (cpu_khz << 10) - (ntsc - tsc);
> + } else
> + max_loops--;
> + }
> + } while (queued && max_loops > 0);
> + WARN_ON(max_loops <= 0);
> +}
> +
> /**
> * setup_local_APIC - setup the local APIC
> *
> @@ -1417,13 +1467,7 @@ static void lapic_setup_esr(void)
> static void setup_local_APIC(void)
> {
> int cpu = smp_processor_id();
> - unsigned int value, queued;
> - int i, j, acked = 0;
> - unsigned long long tsc = 0, ntsc;
> - long long max_loops = cpu_khz ? cpu_khz : 1000000;
> -
> - if (boot_cpu_has(X86_FEATURE_TSC))
> - tsc = rdtsc();
> + unsigned int value;
>
> if (disable_apic) {
> disable_ioapic_support();
> @@ -1475,45 +1519,7 @@ static void setup_local_APIC(void)
> value &= ~APIC_TPRI_MASK;
> apic_write(APIC_TASKPRI, value);
>
> - /*
> - * After a crash, we no longer service the interrupts and a pending
> - * interrupt from previous kernel might still have ISR bit set.
> - *
> - * Most probably by now CPU has serviced that pending interrupt and
> - * it might not have done the ack_APIC_irq() because it thought,
> - * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
> - * does not clear the ISR bit and cpu thinks it has already serivced
> - * the interrupt. Hence a vector might get locked. It was noticed
> - * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
> - */
> - do {
> - queued = 0;
> - for (i = APIC_ISR_NR - 1; i >= 0; i--)
> - queued |= apic_read(APIC_IRR + i*0x10);
> -
> - for (i = APIC_ISR_NR - 1; i >= 0; i--) {
> - value = apic_read(APIC_ISR + i*0x10);
> - for (j = 31; j >= 0; j--) {
> - if (value & (1<<j)) {
> - ack_APIC_irq();
> - acked++;
> - }
> - }
> - }
> - if (acked > 256) {
> - printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
> - acked);
> - break;
> - }
> - if (queued) {
> - if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
> - ntsc = rdtsc();
> - max_loops = (cpu_khz << 10) - (ntsc - tsc);
> - } else
> - max_loops--;
> - }
> - } while (queued && max_loops > 0);
> - WARN_ON(max_loops <= 0);
> + apic_pending_intr_clear();
>
> /*
> * Now that we are all set up, enable the APIC
> --
> 2.14.3
>
>
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 6+ messages in thread* [tip:x86/apic] x86/apic: Move pending intr check code into it's own function
2018-02-26 2:39 [PATCH v4 1/2] x86/apic: Move pending intr check code into it's own function Dou Liyang
2018-02-26 2:39 ` [PATCH v4 2/2] x86/apic: Replace common tools with new ones Dou Liyang
2018-02-26 14:52 ` [PATCH v4 1/2] x86/apic: Move pending intr check code into it's own function Andy Shevchenko
@ 2018-02-28 14:12 ` tip-bot for Dou Liyang
2 siblings, 0 replies; 6+ messages in thread
From: tip-bot for Dou Liyang @ 2018-02-28 14:12 UTC (permalink / raw)
To: linux-tip-commits
Cc: andy.shevchenko, tglx, hpa, linux-kernel, douly.fnst, mingo
Commit-ID: 2066f4d67e7d9cbe44e451d782cdcc0a0d12e5d3
Gitweb: https://git.kernel.org/tip/2066f4d67e7d9cbe44e451d782cdcc0a0d12e5d3
Author: Dou Liyang <douly.fnst@cn.fujitsu.com>
AuthorDate: Mon, 26 Feb 2018 10:39:56 +0800
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 28 Feb 2018 15:09:11 +0100
x86/apic: Move pending intr check code into it's own function
The pending interrupt check code is mixed with the local APIC setup code,
that looks messy.
Extract the related code, move it into a new function named
apic_pending_intr_clear().
Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: bhe@redhat.com
Cc: ebiederm@xmission.com
Link: https://lkml.kernel.org/r/20180226023957.22861-1-douly.fnst@cn.fujitsu.com
---
arch/x86/kernel/apic/apic.c | 98 ++++++++++++++++++++++++---------------------
1 file changed, 52 insertions(+), 46 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 2ceac9f6c5d7..3fda9734db25 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1408,6 +1408,56 @@ static void lapic_setup_esr(void)
oldvalue, value);
}
+static void apic_pending_intr_clear(void)
+{
+ long long max_loops = cpu_khz ? cpu_khz : 1000000;
+ unsigned long long tsc = 0, ntsc;
+ unsigned int value, queued;
+ int i, j, acked = 0;
+
+ if (boot_cpu_has(X86_FEATURE_TSC))
+ tsc = rdtsc();
+ /*
+ * After a crash, we no longer service the interrupts and a pending
+ * interrupt from previous kernel might still have ISR bit set.
+ *
+ * Most probably by now CPU has serviced that pending interrupt and
+ * it might not have done the ack_APIC_irq() because it thought,
+ * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
+ * does not clear the ISR bit and cpu thinks it has already serivced
+ * the interrupt. Hence a vector might get locked. It was noticed
+ * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
+ */
+ do {
+ queued = 0;
+ for (i = APIC_ISR_NR - 1; i >= 0; i--)
+ queued |= apic_read(APIC_IRR + i*0x10);
+
+ for (i = APIC_ISR_NR - 1; i >= 0; i--) {
+ value = apic_read(APIC_ISR + i*0x10);
+ for (j = 31; j >= 0; j--) {
+ if (value & (1<<j)) {
+ ack_APIC_irq();
+ acked++;
+ }
+ }
+ }
+ if (acked > 256) {
+ printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
+ acked);
+ break;
+ }
+ if (queued) {
+ if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
+ ntsc = rdtsc();
+ max_loops = (cpu_khz << 10) - (ntsc - tsc);
+ } else
+ max_loops--;
+ }
+ } while (queued && max_loops > 0);
+ WARN_ON(max_loops <= 0);
+}
+
/**
* setup_local_APIC - setup the local APIC
*
@@ -1417,13 +1467,7 @@ static void lapic_setup_esr(void)
static void setup_local_APIC(void)
{
int cpu = smp_processor_id();
- unsigned int value, queued;
- int i, j, acked = 0;
- unsigned long long tsc = 0, ntsc;
- long long max_loops = cpu_khz ? cpu_khz : 1000000;
-
- if (boot_cpu_has(X86_FEATURE_TSC))
- tsc = rdtsc();
+ unsigned int value;
if (disable_apic) {
disable_ioapic_support();
@@ -1475,45 +1519,7 @@ static void setup_local_APIC(void)
value &= ~APIC_TPRI_MASK;
apic_write(APIC_TASKPRI, value);
- /*
- * After a crash, we no longer service the interrupts and a pending
- * interrupt from previous kernel might still have ISR bit set.
- *
- * Most probably by now CPU has serviced that pending interrupt and
- * it might not have done the ack_APIC_irq() because it thought,
- * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
- * does not clear the ISR bit and cpu thinks it has already serivced
- * the interrupt. Hence a vector might get locked. It was noticed
- * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
- */
- do {
- queued = 0;
- for (i = APIC_ISR_NR - 1; i >= 0; i--)
- queued |= apic_read(APIC_IRR + i*0x10);
-
- for (i = APIC_ISR_NR - 1; i >= 0; i--) {
- value = apic_read(APIC_ISR + i*0x10);
- for (j = 31; j >= 0; j--) {
- if (value & (1<<j)) {
- ack_APIC_irq();
- acked++;
- }
- }
- }
- if (acked > 256) {
- printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
- acked);
- break;
- }
- if (queued) {
- if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
- ntsc = rdtsc();
- max_loops = (cpu_khz << 10) - (ntsc - tsc);
- } else
- max_loops--;
- }
- } while (queued && max_loops > 0);
- WARN_ON(max_loops <= 0);
+ apic_pending_intr_clear();
/*
* Now that we are all set up, enable the APIC
^ permalink raw reply related [flat|nested] 6+ messages in thread