[PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Dmitry Osipenko]

Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
as critical.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---

Change log:
v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
        Tegra124. Switched to a use of common EMC gate definition on Tegra20
        and Tegra30.

v3:     Dropped marking PLL_P outputs as critical, because seems they are
        not so critical. Although, I still haven't got a definitive answer
        about what exact HW functions are affected by the fixed-clocks.
        Anyway it should be cleaner to correct the actual drivers.

 drivers/clk/tegra/clk-emc.c              |  2 +-
 drivers/clk/tegra/clk-tegra-periph.c     |  2 +-
 drivers/clk/tegra/clk-tegra-super-gen4.c |  8 +++++---
 drivers/clk/tegra/clk-tegra114.c         |  3 +--
 drivers/clk/tegra/clk-tegra124.c         |  7 +++----
 drivers/clk/tegra/clk-tegra20.c          | 23 ++++++++++-------------
 drivers/clk/tegra/clk-tegra210.c         |  3 +--
 drivers/clk/tegra/clk-tegra30.c          | 14 ++++----------
 8 files changed, 26 insertions(+), 36 deletions(-)

diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
index 11a5066e5c27..5234acd30e89 100644
--- a/drivers/clk/tegra/clk-emc.c
+++ b/drivers/clk/tegra/clk-emc.c
@@ -515,7 +515,7 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
 
 	init.name = "emc";
 	init.ops = &tegra_clk_emc_ops;
-	init.flags = 0;
+	init.flags = CLK_IS_CRITICAL;
 	init.parent_names = emc_parent_clk_names;
 	init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
 
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index c02711927d79..2acba2986bc6 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -830,7 +830,7 @@ static struct tegra_periph_init_data gate_clks[] = {
 	GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
 	GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
 	GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
-	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
+	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
 	GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
 	GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
 	GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index 10047107c1dc..89d6b47a27a8 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -125,7 +125,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
 		/* SCLK */
 		dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
 		if (dt_clk) {
-			clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,
+			clk = clk_register_divider(NULL, "sclk", "sclk_mux",
+						CLK_IS_CRITICAL,
 						clk_base + SCLK_DIVIDER, 0, 8,
 						0, &sysrate_lock);
 			*dt_clk = clk;
@@ -137,7 +138,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
 			clk = tegra_clk_register_super_mux("sclk",
 						gen_info->sclk_parents,
 						gen_info->num_sclk_parents,
-						CLK_SET_RATE_PARENT,
+						CLK_SET_RATE_PARENT |
+						CLK_IS_CRITICAL,
 						clk_base + SCLK_BURST_POLICY,
 						0, 4, 0, 0, NULL);
 			*dt_clk = clk;
@@ -151,7 +153,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
 				   clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
 				   &sysrate_lock);
 		clk = clk_register_gate(NULL, "hclk", "hclk_div",
-				CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+				CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 				clk_base + SYSTEM_CLK_RATE,
 				7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
 		*dt_clk = clk;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 63087d17c3e2..c3945c683f60 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -955,8 +955,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
 
 	/* PLLM */
 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
-			     CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
-			     &pll_m_params, NULL);
+			     CLK_SET_RATE_GATE, &pll_m_params, NULL);
 	clks[TEGRA114_CLK_PLL_M] = clk;
 
 	/* PLLM_OUT1 */
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index e81ea5b11577..230f9a2c1abf 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1089,8 +1089,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base,
 
 	/* PLLM */
 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
-			     CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
-			     &pll_m_params, NULL);
+			     CLK_SET_RATE_GATE, &pll_m_params, NULL);
 	clk_register_clkdev(clk, "pll_m", NULL);
 	clks[TEGRA124_CLK_PLL_M] = clk;
 
@@ -1099,7 +1098,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base,
 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 				8, 8, 1, NULL);
 	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
-				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+				clk_base + PLLM_OUT, 1, 0,
 				CLK_SET_RATE_PARENT, 0, NULL);
 	clk_register_clkdev(clk, "pll_m_out1", NULL);
 	clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
@@ -1272,7 +1271,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
 	{ TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
 	{ TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
 	{ TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
-	{ TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
+	{ TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 },
 	{ TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
 	{ TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
 	{ TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index cbd5a2e5c569..e3392ca2c2fc 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -576,6 +576,7 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
 	[tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
 	[tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
+	[tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true },
 };
 
 static unsigned long tegra20_clk_measure_input_freq(void)
@@ -651,8 +652,7 @@ static void tegra20_pll_init(void)
 
 	/* PLLM */
 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
-			    CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
-			    &pll_m_params, NULL);
+			    CLK_SET_RATE_GATE, &pll_m_params, NULL);
 	clks[TEGRA20_CLK_PLL_M] = clk;
 
 	/* PLLM_OUT1 */
@@ -660,7 +660,7 @@ static void tegra20_pll_init(void)
 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 				8, 8, 1, NULL);
 	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
-				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+				clk_base + PLLM_OUT, 1, 0,
 				CLK_SET_RATE_PARENT, 0, NULL);
 	clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
 
@@ -723,7 +723,8 @@ static void tegra20_super_clk_init(void)
 
 	/* SCLK */
 	clk = tegra_clk_register_super_mux("sclk", sclk_parents,
-			      ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
+			      ARRAY_SIZE(sclk_parents),
+			      CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 			      clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
 	clks[TEGRA20_CLK_SCLK] = clk;
 
@@ -814,9 +815,6 @@ static void __init tegra20_periph_clk_init(void)
 			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       30, 2, 0, &emc_lock);
-	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
-				    57, periph_clk_enb_refcnt);
-	clks[TEGRA20_CLK_EMC] = clk;
 
 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
 				    &emc_lock);
@@ -1019,13 +1017,12 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
 	{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
 	{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
-	{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
-	{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
-	{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
-	{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
-	{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
+	{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
+	{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 0 },
+	{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 0 },
+	{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 0 },
+	{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
 	{ TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
-	{ TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
 	{ TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 9e6260869eb9..25cc6e0905be 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3025,7 +3025,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
 	{ TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
-	{ TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1 },
+	{ TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
 	{ TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
 	{ TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
 	{ TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
@@ -3040,7 +3040,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
 	{ TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
 	{ TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
-	{ TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	/* TODO find a way to enable this on-demand */
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index bee84c554932..8428895ad475 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -819,6 +819,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
 	[tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
 	[tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
+	[tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = true },
 };
 
 static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
@@ -843,8 +844,7 @@ static void __init tegra30_pll_init(void)
 
 	/* PLLM */
 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
-			    CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
-			    &pll_m_params, NULL);
+			    CLK_SET_RATE_GATE, &pll_m_params, NULL);
 	clks[TEGRA30_CLK_PLL_M] = clk;
 
 	/* PLLM_OUT1 */
@@ -852,7 +852,7 @@ static void __init tegra30_pll_init(void)
 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 				8, 8, 1, NULL);
 	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
-				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+				clk_base + PLLM_OUT, 1, 0,
 				CLK_SET_RATE_PARENT, 0, NULL);
 	clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
 
@@ -990,7 +990,7 @@ static void __init tegra30_super_clk_init(void)
 	/* SCLK */
 	clk = tegra_clk_register_super_mux("sclk", sclk_parents,
 				  ARRAY_SIZE(sclk_parents),
-				  CLK_SET_RATE_PARENT,
+				  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 				  clk_base + SCLK_BURST_POLICY,
 				  0, 4, 0, 0, NULL);
 	clks[TEGRA30_CLK_SCLK] = clk;
@@ -1060,9 +1060,6 @@ static void __init tegra30_periph_clk_init(void)
 			       CLK_SET_RATE_NO_REPARENT,
 			       clk_base + CLK_SOURCE_EMC,
 			       30, 2, 0, &emc_lock);
-	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
-				    57, periph_clk_enb_refcnt);
-	clks[TEGRA30_CLK_EMC] = clk;
 
 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
 				    &emc_lock);
@@ -1252,10 +1249,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
 	{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
 	{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
-	{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
-	{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
-	{ TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
 	{ TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
-- 
2.15.1

[PATCH v3 2/3] clk: tegra20: Correct PLL_C_OUT1 setup

[Dmitry Osipenko]

PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
set it to 240 MHz and explicitly specify HCLK rate for consistency.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---

Change log:
v2:     No change.
v3:     No change.

 drivers/clk/tegra/clk-tegra20.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index e3392ca2c2fc..dec95919fbff 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1018,9 +1018,9 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
 	{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
 	{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
-	{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 0 },
-	{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 0 },
-	{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 0 },
+	{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
+	{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 },
+	{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
 	{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
 	{ TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
-- 
2.15.1

[PATCH v3 3/3] clk: tegra: Specify VDE clock rate

[Dmitry Osipenko]

Currently VDE clock rate is determined by clock config left from
bootloader, let's not rely on it and explicitly specify the clock
rate in the CCF driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---

Change log:
v2:     No change.
v3:     No change.

 drivers/clk/tegra/clk-tegra114.c | 1 +
 drivers/clk/tegra/clk-tegra124.c | 2 +-
 drivers/clk/tegra/clk-tegra20.c  | 1 +
 drivers/clk/tegra/clk-tegra30.c  | 1 +
 4 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index c3945c683f60..5d5a22d529f5 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1189,6 +1189,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
 	{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
 	{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
+	{ TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
 	/* must be the last entry */
 	{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
 };
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 230f9a2c1abf..50088e976611 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1267,7 +1267,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
 	{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
-	{ TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 },
+	{ TEGRA124_CLK_VDE, TEGRA124_CLK_CLK_MAX, 600000000, 0 },
 	{ TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
 	{ TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
 	{ TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index dec95919fbff..0ee56dd04cec 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1048,6 +1048,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
 	{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
 	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
+	{ TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
 	/* must be the last entry */
 	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
 };
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8428895ad475..b316dfb6f6c7 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1266,6 +1266,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
 	{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
 	{ TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
+	{ TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
 	/* must be the last entry */
 	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
 };
-- 
2.15.1

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Dmitry Osipenko]

On 10.01.2018 16:59, Dmitry Osipenko wrote:
> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
> as critical.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> 
> Change log:
> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
>         and Tegra30.
> 
> v3:     Dropped marking PLL_P outputs as critical, because seems they are
>         not so critical. Although, I still haven't got a definitive answer
>         about what exact HW functions are affected by the fixed-clocks.
>         Anyway it should be cleaner to correct the actual drivers.

Stephen / Michael, would it be possible to schedule these patches for 4.16? My
T20 and T30 devices aren't working without the 'critical clocks' patch. Things
happen to work with the opensource u-boot, but not with the proprietary
bootloader. It's probably not a big deal that out-of-tree devices are broken,
although would be nice to have one problem less.

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Dmitry Osipenko]

On 15.01.2018 13:56, Dmitry Osipenko wrote:
> On 10.01.2018 16:59, Dmitry Osipenko wrote:
>> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
>> as critical.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>> ---
>>
>> Change log:
>> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
>>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
>>         and Tegra30.
>>
>> v3:     Dropped marking PLL_P outputs as critical, because seems they are
>>         not so critical. Although, I still haven't got a definitive answer
>>         about what exact HW functions are affected by the fixed-clocks.
>>         Anyway it should be cleaner to correct the actual drivers.
> 
> Stephen / Michael, would it be possible to schedule these patches for 4.16? My
> T20 and T30 devices aren't working without the 'critical clocks' patch. Things
> happen to work with the opensource u-boot, but not with the proprietary
> bootloader. It's probably not a big deal that out-of-tree devices are broken,
> although would be nice to have one problem less.

Guys, is there anything I could do to get these patches in linux-next?

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1678 bytes --]

On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
> On 15.01.2018 13:56, Dmitry Osipenko wrote:
> > On 10.01.2018 16:59, Dmitry Osipenko wrote:
> >> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
> >> as critical.
> >>
> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> >> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >> ---
> >>
> >> Change log:
> >> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
> >>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
> >>         and Tegra30.
> >>
> >> v3:     Dropped marking PLL_P outputs as critical, because seems they are
> >>         not so critical. Although, I still haven't got a definitive answer
> >>         about what exact HW functions are affected by the fixed-clocks.
> >>         Anyway it should be cleaner to correct the actual drivers.
> > 
> > Stephen / Michael, would it be possible to schedule these patches for 4.16? My
> > T20 and T30 devices aren't working without the 'critical clocks' patch. Things
> > happen to work with the opensource u-boot, but not with the proprietary
> > bootloader. It's probably not a big deal that out-of-tree devices are broken,
> > although would be nice to have one problem less.
> 
> Guys, is there anything I could do to get these patches in linux-next?

I've picked these up into the for-4.17/clk branch in the Tegra tree. I
already have that branch for the MBIST patches which are a dependency
for the for-4.17/soc branch.

Stephen, Mike, let me know if you have any objections to carrying these
in the Tegra tree.

Thanks,
Thierry

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Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Dmitry Osipenko]

On 08.03.2018 17:44, Thierry Reding wrote:
> On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
>> On 15.01.2018 13:56, Dmitry Osipenko wrote:
>>> On 10.01.2018 16:59, Dmitry Osipenko wrote:
>>>> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
>>>> as critical.
>>>>
>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>> ---
>>>>
>>>> Change log:
>>>> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
>>>>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
>>>>         and Tegra30.
>>>>
>>>> v3:     Dropped marking PLL_P outputs as critical, because seems they are
>>>>         not so critical. Although, I still haven't got a definitive answer
>>>>         about what exact HW functions are affected by the fixed-clocks.
>>>>         Anyway it should be cleaner to correct the actual drivers.
>>>
>>> Stephen / Michael, would it be possible to schedule these patches for 4.16? My
>>> T20 and T30 devices aren't working without the 'critical clocks' patch. Things
>>> happen to work with the opensource u-boot, but not with the proprietary
>>> bootloader. It's probably not a big deal that out-of-tree devices are broken,
>>> although would be nice to have one problem less.
>>
>> Guys, is there anything I could do to get these patches in linux-next?
> 
> I've picked these up into the for-4.17/clk branch in the Tegra tree. I
> already have that branch for the MBIST patches which are a dependency
> for the for-4.17/soc branch.

Thank you very much! Could you please add stable tag to this ("Mark HCLK, SCLK
and EMC as critical") patch? It would be nice to have 4.16 unbroken eventually
for those who (have to) use downstream android bootloader.

Cc: <stable@vger.kernel.org> # v4.16

> Stephen, Mike, let me know if you have any objections to carrying these
> in the Tegra tree.

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Stephen Boyd]

Quoting Thierry Reding (2018-03-08 06:44:37)
> On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
> > On 15.01.2018 13:56, Dmitry Osipenko wrote:
> > > On 10.01.2018 16:59, Dmitry Osipenko wrote:
> > >> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
> > >> as critical.
> > >>
> > >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> > >> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > >> ---
> > >>
> > >> Change log:
> > >> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
> > >>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
> > >>         and Tegra30.
> > >>
> > >> v3:     Dropped marking PLL_P outputs as critical, because seems they are
> > >>         not so critical. Although, I still haven't got a definitive answer
> > >>         about what exact HW functions are affected by the fixed-clocks.
> > >>         Anyway it should be cleaner to correct the actual drivers.
> > > 
> > > Stephen / Michael, would it be possible to schedule these patches for 4.16? My
> > > T20 and T30 devices aren't working without the 'critical clocks' patch. Things
> > > happen to work with the opensource u-boot, but not with the proprietary
> > > bootloader. It's probably not a big deal that out-of-tree devices are broken,
> > > although would be nice to have one problem less.
> > 
> > Guys, is there anything I could do to get these patches in linux-next?
> 
> I've picked these up into the for-4.17/clk branch in the Tegra tree. I
> already have that branch for the MBIST patches which are a dependency
> for the for-4.17/soc branch.
> 
> Stephen, Mike, let me know if you have any objections to carrying these
> in the Tegra tree.
> 

Are you going to send us a PR at some point?

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Stephen Boyd]

Quoting Thierry Reding (2018-03-08 06:44:37)
> On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
> > On 15.01.2018 13:56, Dmitry Osipenko wrote:
> > > On 10.01.2018 16:59, Dmitry Osipenko wrote:
> > >> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these cloc=
ks
> > >> as critical.
> > >>
> > >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> > >> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > >> ---
> > >>
> > >> Change log:
> > >> v2:     Fixed accidentally missed marking EMC as critical on Tegra30=
 and
> > >>         Tegra124. Switched to a use of common EMC gate definition on=
 Tegra20
> > >>         and Tegra30.
> > >>
> > >> v3:     Dropped marking PLL_P outputs as critical, because seems the=
y are
> > >>         not so critical. Although, I still haven't got a definitive =
answer
> > >>         about what exact HW functions are affected by the fixed-cloc=
ks.
> > >>         Anyway it should be cleaner to correct the actual drivers.
> > > =

> > > Stephen / Michael, would it be possible to schedule these patches for=
 4.16? My
> > > T20 and T30 devices aren't working without the 'critical clocks' patc=
h. Things
> > > happen to work with the opensource u-boot, but not with the proprieta=
ry
> > > bootloader. It's probably not a big deal that out-of-tree devices are=
 broken,
> > > although would be nice to have one problem less.
> > =

> > Guys, is there anything I could do to get these patches in linux-next?
> =

> I've picked these up into the for-4.17/clk branch in the Tegra tree. I
> already have that branch for the MBIST patches which are a dependency
> for the for-4.17/soc branch.
> =

> Stephen, Mike, let me know if you have any objections to carrying these
> in the Tegra tree.
> =


Are you going to send us a PR at some point?

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Thierry Reding]

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On Fri, Mar 09, 2018 at 09:33:06AM -0800, Stephen Boyd wrote:
> Quoting Thierry Reding (2018-03-08 06:44:37)
> > On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
> > > On 15.01.2018 13:56, Dmitry Osipenko wrote:
> > > > On 10.01.2018 16:59, Dmitry Osipenko wrote:
> > > >> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
> > > >> as critical.
> > > >>
> > > >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> > > >> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > > >> ---
> > > >>
> > > >> Change log:
> > > >> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
> > > >>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
> > > >>         and Tegra30.
> > > >>
> > > >> v3:     Dropped marking PLL_P outputs as critical, because seems they are
> > > >>         not so critical. Although, I still haven't got a definitive answer
> > > >>         about what exact HW functions are affected by the fixed-clocks.
> > > >>         Anyway it should be cleaner to correct the actual drivers.
> > > > 
> > > > Stephen / Michael, would it be possible to schedule these patches for 4.16? My
> > > > T20 and T30 devices aren't working without the 'critical clocks' patch. Things
> > > > happen to work with the opensource u-boot, but not with the proprietary
> > > > bootloader. It's probably not a big deal that out-of-tree devices are broken,
> > > > although would be nice to have one problem less.
> > > 
> > > Guys, is there anything I could do to get these patches in linux-next?
> > 
> > I've picked these up into the for-4.17/clk branch in the Tegra tree. I
> > already have that branch for the MBIST patches which are a dependency
> > for the for-4.17/soc branch.
> > 
> > Stephen, Mike, let me know if you have any objections to carrying these
> > in the Tegra tree.
> > 
> 
> Are you going to send us a PR at some point?

Yes, I was going to let the patches cook a little in linux-next and send
a PR by the end of the week. Does that sound okay?

Thierry

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Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Thierry Reding]

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On Fri, Mar 09, 2018 at 05:35:46PM +0300, Dmitry Osipenko wrote:
> On 08.03.2018 17:44, Thierry Reding wrote:
> > On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
> >> On 15.01.2018 13:56, Dmitry Osipenko wrote:
> >>> On 10.01.2018 16:59, Dmitry Osipenko wrote:
> >>>> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
> >>>> as critical.
> >>>>
> >>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> >>>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >>>> ---
> >>>>
> >>>> Change log:
> >>>> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
> >>>>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
> >>>>         and Tegra30.
> >>>>
> >>>> v3:     Dropped marking PLL_P outputs as critical, because seems they are
> >>>>         not so critical. Although, I still haven't got a definitive answer
> >>>>         about what exact HW functions are affected by the fixed-clocks.
> >>>>         Anyway it should be cleaner to correct the actual drivers.
> >>>
> >>> Stephen / Michael, would it be possible to schedule these patches for 4.16? My
> >>> T20 and T30 devices aren't working without the 'critical clocks' patch. Things
> >>> happen to work with the opensource u-boot, but not with the proprietary
> >>> bootloader. It's probably not a big deal that out-of-tree devices are broken,
> >>> although would be nice to have one problem less.
> >>
> >> Guys, is there anything I could do to get these patches in linux-next?
> > 
> > I've picked these up into the for-4.17/clk branch in the Tegra tree. I
> > already have that branch for the MBIST patches which are a dependency
> > for the for-4.17/soc branch.
> 
> Thank you very much! Could you please add stable tag to this ("Mark HCLK, SCLK
> and EMC as critical") patch? It would be nice to have 4.16 unbroken eventually
> for those who (have to) use downstream android bootloader.
> 
> Cc: <stable@vger.kernel.org> # v4.16

Should we add a Fixes: line instead? That way it will get automatically
backported to all applicable stable releases.

This is a little complicated because the clocks were introduced in
different commits, most of them a very long time ago:

	a7c8485a0ebbdce303c6709e208bb4fd08aff8ad (sclk)
	2db04f16b589c6c96bd07df3f1ef8558bfdb6810 (emc)
	76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 (emc)
	...

So Fixes: is perhaps not desirable after all, but then, so isn't tagging
v4.16 specifically because this is a bug since almost forever, so v4.16
is fairly arbitrary. Shouldn't we at least get this fixed for the last
couple of LTS releases?

Thierry

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Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Dmitry Osipenko]

On 12.03.2018 10:15, Thierry Reding wrote:
> On Fri, Mar 09, 2018 at 05:35:46PM +0300, Dmitry Osipenko wrote:
>> On 08.03.2018 17:44, Thierry Reding wrote:
>>> On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
>>>> On 15.01.2018 13:56, Dmitry Osipenko wrote:
>>>>> On 10.01.2018 16:59, Dmitry Osipenko wrote:
>>>>>> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
>>>>>> as critical.
>>>>>>
>>>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>>>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>>> ---
>>>>>>
>>>>>> Change log:
>>>>>> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
>>>>>>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
>>>>>>         and Tegra30.
>>>>>>
>>>>>> v3:     Dropped marking PLL_P outputs as critical, because seems they are
>>>>>>         not so critical. Although, I still haven't got a definitive answer
>>>>>>         about what exact HW functions are affected by the fixed-clocks.
>>>>>>         Anyway it should be cleaner to correct the actual drivers.
>>>>>
>>>>> Stephen / Michael, would it be possible to schedule these patches for 4.16? My
>>>>> T20 and T30 devices aren't working without the 'critical clocks' patch. Things
>>>>> happen to work with the opensource u-boot, but not with the proprietary
>>>>> bootloader. It's probably not a big deal that out-of-tree devices are broken,
>>>>> although would be nice to have one problem less.
>>>>
>>>> Guys, is there anything I could do to get these patches in linux-next?
>>>
>>> I've picked these up into the for-4.17/clk branch in the Tegra tree. I
>>> already have that branch for the MBIST patches which are a dependency
>>> for the for-4.17/soc branch.
>>
>> Thank you very much! Could you please add stable tag to this ("Mark HCLK, SCLK
>> and EMC as critical") patch? It would be nice to have 4.16 unbroken eventually
>> for those who (have to) use downstream android bootloader.
>>
>> Cc: <stable@vger.kernel.org> # v4.16
> 
> Should we add a Fixes: line instead? That way it will get automatically
> backported to all applicable stable releases.
> 
> This is a little complicated because the clocks were introduced in
> different commits, most of them a very long time ago:
> 
> 	a7c8485a0ebbdce303c6709e208bb4fd08aff8ad (sclk)
> 	2db04f16b589c6c96bd07df3f1ef8558bfdb6810 (emc)
> 	76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 (emc)
> 	...
> 
> So Fixes: is perhaps not desirable after all, but then, so isn't tagging
> v4.16 specifically because this is a bug since almost forever, so v4.16
> is fairly arbitrary. Shouldn't we at least get this fixed for the last
> couple of LTS releases?

That issue was masked in earlier kernels and only appears in 4.16, there is no
need to backport it further. I thought that adding of 'stable' tag is enough to
get patch backported automatically, so let's add 'fixes' instead:

Fixes: 109eba2eb61a ("clk: tegra: Mark APB clock as critical")

This patch applies cleanly to 4.16, everything should be fine.

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Thierry Reding]

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On Mon, Mar 12, 2018 at 03:37:28PM +0300, Dmitry Osipenko wrote:
> On 12.03.2018 10:15, Thierry Reding wrote:
> > On Fri, Mar 09, 2018 at 05:35:46PM +0300, Dmitry Osipenko wrote:
> >> On 08.03.2018 17:44, Thierry Reding wrote:
> >>> On Thu, Mar 01, 2018 at 04:33:29PM +0300, Dmitry Osipenko wrote:
> >>>> On 15.01.2018 13:56, Dmitry Osipenko wrote:
> >>>>> On 10.01.2018 16:59, Dmitry Osipenko wrote:
> >>>>>> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
> >>>>>> as critical.
> >>>>>>
> >>>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> >>>>>> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >>>>>> ---
> >>>>>>
> >>>>>> Change log:
> >>>>>> v2:     Fixed accidentally missed marking EMC as critical on Tegra30 and
> >>>>>>         Tegra124. Switched to a use of common EMC gate definition on Tegra20
> >>>>>>         and Tegra30.
> >>>>>>
> >>>>>> v3:     Dropped marking PLL_P outputs as critical, because seems they are
> >>>>>>         not so critical. Although, I still haven't got a definitive answer
> >>>>>>         about what exact HW functions are affected by the fixed-clocks.
> >>>>>>         Anyway it should be cleaner to correct the actual drivers.
> >>>>>
> >>>>> Stephen / Michael, would it be possible to schedule these patches for 4.16? My
> >>>>> T20 and T30 devices aren't working without the 'critical clocks' patch. Things
> >>>>> happen to work with the opensource u-boot, but not with the proprietary
> >>>>> bootloader. It's probably not a big deal that out-of-tree devices are broken,
> >>>>> although would be nice to have one problem less.
> >>>>
> >>>> Guys, is there anything I could do to get these patches in linux-next?
> >>>
> >>> I've picked these up into the for-4.17/clk branch in the Tegra tree. I
> >>> already have that branch for the MBIST patches which are a dependency
> >>> for the for-4.17/soc branch.
> >>
> >> Thank you very much! Could you please add stable tag to this ("Mark HCLK, SCLK
> >> and EMC as critical") patch? It would be nice to have 4.16 unbroken eventually
> >> for those who (have to) use downstream android bootloader.
> >>
> >> Cc: <stable@vger.kernel.org> # v4.16
> > 
> > Should we add a Fixes: line instead? That way it will get automatically
> > backported to all applicable stable releases.
> > 
> > This is a little complicated because the clocks were introduced in
> > different commits, most of them a very long time ago:
> > 
> > 	a7c8485a0ebbdce303c6709e208bb4fd08aff8ad (sclk)
> > 	2db04f16b589c6c96bd07df3f1ef8558bfdb6810 (emc)
> > 	76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 (emc)
> > 	...
> > 
> > So Fixes: is perhaps not desirable after all, but then, so isn't tagging
> > v4.16 specifically because this is a bug since almost forever, so v4.16
> > is fairly arbitrary. Shouldn't we at least get this fixed for the last
> > couple of LTS releases?
> 
> That issue was masked in earlier kernels and only appears in 4.16, there is no
> need to backport it further. I thought that adding of 'stable' tag is enough to
> get patch backported automatically, so let's add 'fixes' instead:
> 
> Fixes: 109eba2eb61a ("clk: tegra: Mark APB clock as critical")
> 
> This patch applies cleanly to 4.16, everything should be fine.

It's not immediately obvious why the above would expose the issue and
hence why this patch fixes the problem, and I'm quite frankly not sure
I understand why that is, so perhaps just going with the stable tag is
the best option after all.

Thierry

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Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Stephen Boyd]

Quoting Thierry Reding (2018-03-12 00:04:30)
> On Fri, Mar 09, 2018 at 09:33:06AM -0800, Stephen Boyd wrote:
> > 
> > Are you going to send us a PR at some point?
> 
> Yes, I was going to let the patches cook a little in linux-next and send
> a PR by the end of the week. Does that sound okay?
> 

Perfect! Thanks.

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

[Stephen Boyd]

Quoting Thierry Reding (2018-03-12 00:04:30)
> On Fri, Mar 09, 2018 at 09:33:06AM -0800, Stephen Boyd wrote:
> > =

> > Are you going to send us a PR at some point?
> =

> Yes, I was going to let the patches cook a little in linux-next and send
> a PR by the end of the week. Does that sound okay?
> =


Perfect! Thanks.