All of lore.kernel.org
 help / color / mirror / Atom feed
From: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Dmytro Laktyushkin <Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 20/34] drm/amd/display: align dtn logs and add mpc idle bit print
Date: Tue, 20 Mar 2018 15:12:45 -0400	[thread overview]
Message-ID: <20180320191259.14453-21-harry.wentland@amd.com> (raw)
In-Reply-To: <20180320191259.14453-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 53 ++++++++++------------
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |  2 +
 3 files changed, 28 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 999190aa8a08..675a81a87099 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -56,16 +56,17 @@
 #define FN(reg_name, field_name) \
 	hws->shifts->field_name, hws->masks->field_name
 
+/*print is 17 wide, first two characters are spaces*/
 #define DTN_INFO_MICRO_SEC(ref_cycle) \
 	print_microsec(dc_ctx, ref_cycle)
 
 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
 {
-	static const uint32_t ref_clk_mhz = 48;
-	static const unsigned int frac = 10;
+	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
+	static const unsigned int frac = 1000;
 	uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
 
-	DTN_INFO("%d.%d \t ",
+	DTN_INFO("  %11d.%03d",
 			us_x10 / frac,
 			us_x10 % frac);
 }
@@ -92,14 +93,14 @@ void dcn10_log_hubbub_state(struct dc *dc)
 
 	hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
 
-	DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
-			"sr_enter \t sr_exit \t dram_clk_change \n");
+	DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
+			"         sr_enter          sr_exit  dram_clk_change\n");
 
 	for (i = 0; i < 4; i++) {
 		struct dcn_hubbub_wm_set *s;
 
 		s = &wm.sets[i];
-		DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
+		DTN_INFO("WM_Set[%d]:", s->wm_set);
 		DTN_INFO_MICRO_SEC(s->data_urgent);
 		DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 		DTN_INFO_MICRO_SEC(s->sr_enter);
@@ -121,19 +122,17 @@ void dcn10_log_hw_state(struct dc *dc)
 
 	dcn10_log_hubbub_state(dc);
 
-	DTN_INFO("HUBP:  format  addr_hi  width  height  "
-			"rotation  mirror  sw_mode  "
-			"dcc_en  blank_en  ttu_dis  underflow  "
-			"min_ttu_vblank  qos_low_wm  qos_high_wm\n");
+	DTN_INFO("HUBP:  format  addr_hi  width  height"
+			"  rot  mir  sw_mode  dcc_en  blank_en  ttu_dis  underflow"
+			"   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 	for (i = 0; i < pool->pipe_count; i++) {
 		struct hubp *hubp = pool->hubps[i];
 		struct dcn_hubp_state s;
 
 		hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 
-		DTN_INFO("[%-2d]:  %5xh  %6xh  %5d  %6d  "
-				"%7xh  %5xh  %6xh  "
-				"%6d  %8d  %7d  %8xh \t",
+		DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
+				"  %6d  %8d  %7d  %8xh",
 				hubp->inst,
 				s.pixel_format,
 				s.inuse_addr_hi,
@@ -152,25 +151,21 @@ void dcn10_log_hw_state(struct dc *dc)
 		DTN_INFO("\n");
 	}
 	DTN_INFO("\n");
+
+	DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 	for (i = 0; i < pool->pipe_count; i++) {
-		struct output_pixel_processor *opp = pool->opps[i];
-		struct mpcc *mpcc = opp->mpc_tree_params.opp_list;
 		struct mpcc_state s = {0};
 
-		while (mpcc) {
-			ASSERT(opp->mpc_tree_params.opp_id == opp->inst);
-			pool->mpc->funcs->read_mpcc_state(pool->mpc, mpcc->mpcc_id, &s);
-			DTN_INFO("[OPP%d - MPCC%d]: DPP%d MPCCBOT%x MODE:%d ALPHA_MODE:%d PREMULT:%d OVERLAP_ONLY:%d\n",
-				s.opp_id, mpcc->mpcc_id, s.dpp_id, s.bot_mpcc_id,
-				s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only);
-			mpcc = mpcc->mpcc_bot;
-			ASSERT(!mpcc || mpcc->mpcc_id == s.bot_mpcc_id);
-		}
+		pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
+		DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
+			i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
+			s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
+			s.idle);
 	}
 	DTN_INFO("\n");
 
-	DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
-			"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
+	DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin"
+			"  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow\n");
 
 	for (i = 0; i < pool->timing_generator_count; i++) {
 		struct timing_generator *tg = pool->timing_generators[i];
@@ -182,9 +177,8 @@ void dcn10_log_hw_state(struct dc *dc)
 		if ((s.otg_enabled & 1) == 0)
 			continue;
 
-		DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
-				"%d \t %d \t %d \t %d \t %d \t %d \t "
-				"%d \t %d \t %d \t %d \t %d \t ",
+		DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %5d %5d %5d"
+				" %5d %5d %5d %5d  %9d\n",
 				tg->inst,
 				s.v_blank_start,
 				s.v_blank_end,
@@ -201,7 +195,6 @@ void dcn10_log_hw_state(struct dc *dc)
 				s.h_total,
 				s.v_total,
 				s.underflow_occurred_status);
-		DTN_INFO("\n");
 	}
 	DTN_INFO("\n");
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 29e15a93a7d0..6f7016a2a11e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -422,7 +422,9 @@ void mpc1_read_mpcc_state(
 	REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
 			MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
 			MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
-			MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->pre_multiplied_alpha);
+			MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
+	REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
+			MPCC_BUSY, &s->busy);
 }
 
 const struct mpc_funcs dcn10_mpc_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 5caacab216b5..caf74e3c836f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -113,6 +113,8 @@ struct mpcc_state {
 	uint32_t alpha_mode;
 	uint32_t pre_multiplied_alpha;
 	uint32_t overlap_only;
+	uint32_t idle;
+	uint32_t busy;
 };
 
 struct mpc_funcs {
-- 
2.14.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2018-03-20 19:12 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-20 19:12 [PATCH 00/34] DC Patches Mar 20, 2018 Harry Wentland
     [not found] ` <20180320191259.14453-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-20 19:12   ` [PATCH 01/34] drm/amd/display: correct the condition in setting cursor not visible beyond left edge Harry Wentland
2018-03-20 19:12   ` [PATCH 02/34] drm/amd/display: dal 3.1.39 Harry Wentland
2018-03-20 19:12   ` [PATCH 03/34] drm/amd/display: Allow truncation to 10 bits Harry Wentland
2018-03-20 19:12   ` [PATCH 04/34] drm/amd/display: Fix FMT truncation programming Harry Wentland
2018-03-20 19:12   ` [PATCH 05/34] drm/amd/display: We shouldn't set format_default on plane as atomic driver Harry Wentland
2018-03-20 19:12   ` [PATCH 06/34] drm/amd/display: Retry when read dpcd caps failed Harry Wentland
2018-03-20 19:12   ` [PATCH 07/34] drm/amd/display: Add one to EDID's audio channel count when passing to DC Harry Wentland
2018-03-20 19:12   ` [PATCH 08/34] drm/amd/display: Update ASIC header files Harry Wentland
2018-03-20 19:12   ` [PATCH 09/34] drm/amd/display: fix lexa bw bounding box Harry Wentland
     [not found]     ` <20180320191259.14453-10-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-21  1:27       ` Zhang, Jerry (Junwei)
2018-03-22 18:39       ` [PATCH v2] drm/amd/display: fix Polaris 12 " Harry Wentland
     [not found]         ` <20180322183957.11419-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-22 18:51           ` Deucher, Alexander
2018-03-20 19:12   ` [PATCH 10/34] drm/amd/display: Rename feature-specific register address init macro Harry Wentland
2018-03-20 19:12   ` [PATCH 11/34] drm/amd/display: Don't read EDID in atomic_check Harry Wentland
2018-03-20 19:12   ` [PATCH 12/34] drm/amd/display: add mpc to dtn log Harry Wentland
2018-03-20 19:12   ` [PATCH 13/34] drm/amd/display: Add debug prints for bandwidth calculations Harry Wentland
2018-03-20 19:12   ` [PATCH 14/34] drm/amd/display: Don't call amdgpu_dm_display_resume as it doesn't exist Harry Wentland
2018-03-20 19:12   ` [PATCH 15/34] drm/amd/display: Adding stutter entry wm to dce bw struct Harry Wentland
2018-03-20 19:12   ` [PATCH 16/34] drm/amd/display: Change wb_h/vratio to double Harry Wentland
2018-03-20 19:12   ` [PATCH 17/34] drm/amd/display: drop dc_validate_guaranteed Harry Wentland
2018-03-20 19:12   ` [PATCH 18/34] drm/amd/display: Implementing new bandwidth registers for DCE120 Harry Wentland
2018-03-20 19:12   ` [PATCH 19/34] drm/amd/display: dal 3.1.40 Harry Wentland
2018-03-20 19:12   ` Harry Wentland [this message]
2018-03-20 19:12   ` [PATCH 21/34] drm/amd/display: add assert in enable FBC Harry Wentland
2018-03-20 19:12   ` [PATCH 22/34] drm/amd/display: Separate mem input constuctors for dce 112 and 120 Harry Wentland
2018-03-20 19:12   ` [PATCH 23/34] drm/amd/display: Only update mpc blend config if not full update Harry Wentland
2018-03-20 19:12   ` [PATCH 24/34] drm/amd/display: hide inconsistent mpcc programming from dtn log Harry Wentland
2018-03-20 19:12   ` [PATCH 25/34] drm/amd/display: Add dc_lut_mode enum Harry Wentland
2018-03-20 19:12   ` [PATCH 26/34] drm/amd/display: Correct print types in DC_LOGS Harry Wentland
2018-03-20 19:12   ` [PATCH 27/34] drm/amd/display: Add num_active_wb to DML Harry Wentland
2018-03-20 19:12   ` [PATCH 28/34] drm/amd/display: Add double buffer machanism to ICSC Harry Wentland
2018-03-20 19:12   ` [PATCH 29/34] drm/amd/display: Couple bug fixes in stats module Harry Wentland
2018-03-20 19:12   ` [PATCH 30/34] drm/amd/display: Rename encoder_info_packet to dc_info_packet Harry Wentland
2018-03-20 19:12   ` [PATCH 31/34] drm/amd/display: Add vline IRQ programming for DCN Harry Wentland
2018-03-20 19:12   ` [PATCH 32/34] drm/amd/display: Add double buffer machanism to OCSC Harry Wentland
2018-03-20 19:12   ` [PATCH 33/34] drm/amd/display: Only program MSA_TIMING_PARAM if it changed Harry Wentland
2018-03-20 19:12   ` [PATCH 34/34] drm/amd/display: Move commit_planes_to_stream to amdgpu_dm Harry Wentland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180320191259.14453-21-harry.wentland@amd.com \
    --to=harry.wentland-5c7gfcevmho@public.gmane.org \
    --cc=Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org \
    --cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.