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From: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: SivapiriyanKumarasamy
	<sivapiriyan.kumarasamy-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 31/34] drm/amd/display: Add vline IRQ programming for DCN
Date: Tue, 20 Mar 2018 15:12:56 -0400	[thread overview]
Message-ID: <20180320191259.14453-32-harry.wentland@amd.com> (raw)
In-Reply-To: <20180320191259.14453-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>

From: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  6 ++
 drivers/gpu/drm/amd/display/dc/dc_stream.h         |  4 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c  | 76 ++++++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  | 14 ++++
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  3 +
 drivers/gpu/drm/amd/display/dc/irq_types.h         |  7 ++
 6 files changed, 110 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 63a3d468939a..554cf975be05 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1375,6 +1375,12 @@ static void commit_planes_for_stream(struct dc *dc,
 					pipe_ctx->stream_res.abm->funcs->set_abm_level(
 							pipe_ctx->stream_res.abm, stream->abm_level);
 			}
+
+			if (stream_update && stream_update->periodic_fn_vsync_delta &&
+					pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
+				pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
+						pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing,
+						pipe_ctx->stream->periodic_fn_vsync_delta);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 3a7093ede569..8d5161060b60 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -70,6 +70,9 @@ struct dc_stream_state {
 	enum color_transfer_func output_tf;
 
 	bool ignore_msa_timing_param;
+
+	unsigned long long periodic_fn_vsync_delta;
+
 	/* TODO: custom INFO packets */
 	/* TODO: ABM info (DMCU) */
 	/* PSR info */
@@ -113,6 +116,7 @@ struct dc_stream_update {
 	struct dc_hdr_static_metadata *hdr_static_metadata;
 	enum color_transfer_func color_output_tf;
 	unsigned int *abm_level;
+	unsigned long long *periodic_fn_vsync_delta;
 };
 
 bool dc_is_stream_unchanged(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 4bf64d1b2c60..f56eac0e4dd2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -93,6 +93,81 @@ static void optc1_disable_stereo(struct timing_generator *optc)
 		OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
 }
 
+static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing)
+{
+	struct dc_crtc_timing patched_crtc_timing;
+	uint32_t vesa_sync_start;
+	uint32_t asic_blank_end;
+	uint32_t interlace_factor;
+	uint32_t vertical_line_start;
+
+	patched_crtc_timing = *dc_crtc_timing;
+	optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
+
+	vesa_sync_start = patched_crtc_timing.h_addressable +
+			patched_crtc_timing.h_border_right +
+			patched_crtc_timing.h_front_porch;
+
+	asic_blank_end = patched_crtc_timing.h_total -
+			vesa_sync_start -
+			patched_crtc_timing.h_border_left;
+
+	interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
+
+	vesa_sync_start = patched_crtc_timing.v_addressable +
+			patched_crtc_timing.v_border_bottom +
+			patched_crtc_timing.v_front_porch;
+
+	asic_blank_end = (patched_crtc_timing.v_total -
+			vesa_sync_start -
+			patched_crtc_timing.v_border_top)
+			* interlace_factor;
+
+	vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
+	if (vertical_line_start < 0) {
+		ASSERT(0);
+		vertical_line_start = 0;
+	}
+
+	return vertical_line_start;
+}
+
+void optc1_program_vline_interrupt(
+		struct timing_generator *optc,
+		const struct dc_crtc_timing *dc_crtc_timing,
+		unsigned long long vsync_delta)
+{
+
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
+	unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
+	uint32_t req_delta_lines = (uint32_t) div64_u64(
+			(req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
+								dc_crtc_timing->h_total);
+
+	uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);
+	uint32_t start_line = 0;
+	uint32_t endLine = 0;
+
+	if (req_delta_lines != 0)
+		req_delta_lines--;
+
+	if (req_delta_lines > vsync_line)
+		start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1;
+	else
+		start_line = vsync_line - req_delta_lines;
+
+	endLine = start_line + 2;
+
+	if (endLine >= dc_crtc_timing->v_total)
+		endLine = 2;
+
+	REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
+			OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
+			OTG_VERTICAL_INTERRUPT0_LINE_END, endLine);
+}
+
 /**
  * program_timing_generator   used by mode timing set
  * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
@@ -1215,6 +1290,7 @@ static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
 static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
 		.program_timing = optc1_program_timing,
+		.program_vline_interrupt = optc1_program_vline_interrupt,
 		.program_global_sync = optc1_program_global_sync,
 		.enable_crtc = optc1_enable_crtc,
 		.disable_crtc = optc1_disable_crtc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index d25e7bf0d0d7..5a9a73d69fd6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -65,6 +65,8 @@
 	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
 	SRI(OTG_BLACK_COLOR, OTG, inst),\
 	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
 	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
 	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
 	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
@@ -124,6 +126,8 @@ struct dcn_optc_registers {
 	uint32_t OTG_TEST_PATTERN_CONTROL;
 	uint32_t OTG_TEST_PATTERN_COLOR;
 	uint32_t OTG_CLOCK_CONTROL;
+	uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
+	uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
 	uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
 	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
 	uint32_t OPTC_INPUT_CLOCK_CONTROL;
@@ -206,6 +210,9 @@ struct dcn_optc_registers {
 	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
 	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
 	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
 	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
 	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
 	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
@@ -323,6 +330,9 @@ struct dcn_optc_registers {
 	type OTG_CLOCK_EN;\
 	type OTG_CLOCK_ON;\
 	type OTG_CLOCK_GATE_DIS;\
+	type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
+	type OTG_VERTICAL_INTERRUPT0_LINE_START;\
+	type OTG_VERTICAL_INTERRUPT0_LINE_END;\
 	type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
 	type OTG_VERTICAL_INTERRUPT2_LINE_START;\
 	type OPTC_INPUT_CLK_EN;\
@@ -420,6 +430,10 @@ void optc1_program_timing(
 	const struct dc_crtc_timing *dc_crtc_timing,
 	bool use_vbios);
 
+void optc1_program_vline_interrupt(struct timing_generator *optc,
+		const struct dc_crtc_timing *dc_crtc_timing,
+		unsigned long long vsync_delta);
+
 void optc1_program_global_sync(
 		struct timing_generator *optc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 3217b5bf6c7a..69cb0a105300 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -140,6 +140,9 @@ struct timing_generator_funcs {
 	void (*program_timing)(struct timing_generator *tg,
 							const struct dc_crtc_timing *timing,
 							bool use_vbios);
+	void (*program_vline_interrupt)(struct timing_generator *optc,
+			const struct dc_crtc_timing *dc_crtc_timing,
+			unsigned long long vsync_delta);
 	bool (*enable_crtc)(struct timing_generator *tg);
 	bool (*disable_crtc)(struct timing_generator *tg);
 	bool (*is_counter_moving)(struct timing_generator *tg);
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h
index a506c2e939f5..cc3b1bc6cedd 100644
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -135,6 +135,13 @@ enum dc_irq_source {
 	DC_IRQ_SOURCE_VBLANK5,
 	DC_IRQ_SOURCE_VBLANK6,
 
+	DC_IRQ_SOURCE_DC1_VLINE0,
+	DC_IRQ_SOURCE_DC2_VLINE0,
+	DC_IRQ_SOURCE_DC3_VLINE0,
+	DC_IRQ_SOURCE_DC4_VLINE0,
+	DC_IRQ_SOURCE_DC5_VLINE0,
+	DC_IRQ_SOURCE_DC6_VLINE0,
+
 	DAL_IRQ_SOURCES_NUMBER
 };
 
-- 
2.14.1

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  parent reply	other threads:[~2018-03-20 19:12 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-20 19:12 [PATCH 00/34] DC Patches Mar 20, 2018 Harry Wentland
     [not found] ` <20180320191259.14453-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-20 19:12   ` [PATCH 01/34] drm/amd/display: correct the condition in setting cursor not visible beyond left edge Harry Wentland
2018-03-20 19:12   ` [PATCH 02/34] drm/amd/display: dal 3.1.39 Harry Wentland
2018-03-20 19:12   ` [PATCH 03/34] drm/amd/display: Allow truncation to 10 bits Harry Wentland
2018-03-20 19:12   ` [PATCH 04/34] drm/amd/display: Fix FMT truncation programming Harry Wentland
2018-03-20 19:12   ` [PATCH 05/34] drm/amd/display: We shouldn't set format_default on plane as atomic driver Harry Wentland
2018-03-20 19:12   ` [PATCH 06/34] drm/amd/display: Retry when read dpcd caps failed Harry Wentland
2018-03-20 19:12   ` [PATCH 07/34] drm/amd/display: Add one to EDID's audio channel count when passing to DC Harry Wentland
2018-03-20 19:12   ` [PATCH 08/34] drm/amd/display: Update ASIC header files Harry Wentland
2018-03-20 19:12   ` [PATCH 09/34] drm/amd/display: fix lexa bw bounding box Harry Wentland
     [not found]     ` <20180320191259.14453-10-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-21  1:27       ` Zhang, Jerry (Junwei)
2018-03-22 18:39       ` [PATCH v2] drm/amd/display: fix Polaris 12 " Harry Wentland
     [not found]         ` <20180322183957.11419-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-22 18:51           ` Deucher, Alexander
2018-03-20 19:12   ` [PATCH 10/34] drm/amd/display: Rename feature-specific register address init macro Harry Wentland
2018-03-20 19:12   ` [PATCH 11/34] drm/amd/display: Don't read EDID in atomic_check Harry Wentland
2018-03-20 19:12   ` [PATCH 12/34] drm/amd/display: add mpc to dtn log Harry Wentland
2018-03-20 19:12   ` [PATCH 13/34] drm/amd/display: Add debug prints for bandwidth calculations Harry Wentland
2018-03-20 19:12   ` [PATCH 14/34] drm/amd/display: Don't call amdgpu_dm_display_resume as it doesn't exist Harry Wentland
2018-03-20 19:12   ` [PATCH 15/34] drm/amd/display: Adding stutter entry wm to dce bw struct Harry Wentland
2018-03-20 19:12   ` [PATCH 16/34] drm/amd/display: Change wb_h/vratio to double Harry Wentland
2018-03-20 19:12   ` [PATCH 17/34] drm/amd/display: drop dc_validate_guaranteed Harry Wentland
2018-03-20 19:12   ` [PATCH 18/34] drm/amd/display: Implementing new bandwidth registers for DCE120 Harry Wentland
2018-03-20 19:12   ` [PATCH 19/34] drm/amd/display: dal 3.1.40 Harry Wentland
2018-03-20 19:12   ` [PATCH 20/34] drm/amd/display: align dtn logs and add mpc idle bit print Harry Wentland
2018-03-20 19:12   ` [PATCH 21/34] drm/amd/display: add assert in enable FBC Harry Wentland
2018-03-20 19:12   ` [PATCH 22/34] drm/amd/display: Separate mem input constuctors for dce 112 and 120 Harry Wentland
2018-03-20 19:12   ` [PATCH 23/34] drm/amd/display: Only update mpc blend config if not full update Harry Wentland
2018-03-20 19:12   ` [PATCH 24/34] drm/amd/display: hide inconsistent mpcc programming from dtn log Harry Wentland
2018-03-20 19:12   ` [PATCH 25/34] drm/amd/display: Add dc_lut_mode enum Harry Wentland
2018-03-20 19:12   ` [PATCH 26/34] drm/amd/display: Correct print types in DC_LOGS Harry Wentland
2018-03-20 19:12   ` [PATCH 27/34] drm/amd/display: Add num_active_wb to DML Harry Wentland
2018-03-20 19:12   ` [PATCH 28/34] drm/amd/display: Add double buffer machanism to ICSC Harry Wentland
2018-03-20 19:12   ` [PATCH 29/34] drm/amd/display: Couple bug fixes in stats module Harry Wentland
2018-03-20 19:12   ` [PATCH 30/34] drm/amd/display: Rename encoder_info_packet to dc_info_packet Harry Wentland
2018-03-20 19:12   ` Harry Wentland [this message]
2018-03-20 19:12   ` [PATCH 32/34] drm/amd/display: Add double buffer machanism to OCSC Harry Wentland
2018-03-20 19:12   ` [PATCH 33/34] drm/amd/display: Only program MSA_TIMING_PARAM if it changed Harry Wentland
2018-03-20 19:12   ` [PATCH 34/34] drm/amd/display: Move commit_planes_to_stream to amdgpu_dm Harry Wentland

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