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From: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Xingyue Tao <xingyue.tao-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 32/34] drm/amd/display: Add double buffer machanism to OCSC
Date: Tue, 20 Mar 2018 15:12:57 -0400	[thread overview]
Message-ID: <20180320191259.14453-33-harry.wentland@amd.com> (raw)
In-Reply-To: <20180320191259.14453-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>

From: Xingyue Tao <xingyue.tao@amd.com>

- Added double buffer mechanism to output CSC
so that there's no tearing when adjusting brightness
from Radeon settings

Signed-off-by: Xingyue Tao <xingyue.tao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 36 +++++++++++++++++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c    | 46 +++++++++++++---------
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 32 ++-------------
 3 files changed, 67 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index b81b2aa3c49f..9b5ff76a8027 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -420,6 +420,41 @@
 	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
 	TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
 
+/*
+ *
+	DCN1 CM debug status register definition
+
+	register :ID9_CM_STATUS do
+	implement_ref :cm
+	map to:  :cmdebugind, at: j
+	width 32
+	disclosure   NEVER
+
+		field :ID9_VUPDATE_CFG, [0], R
+		field :ID9_IGAM_LUT_MODE, [2..1], R
+		field :ID9_BNS_BYPASS, [3], R
+		field :ID9_ICSC_MODE, [5..4], R
+		field :ID9_DGAM_LUT_MODE, [8..6], R
+		field :ID9_HDR_BYPASS, [9], R
+		field :ID9_GAMUT_REMAP_MODE, [11..10], R
+		field :ID9_RGAM_LUT_MODE, [14..12], R
+		#1 free bit
+		field :ID9_OCSC_MODE, [18..16], R
+		field :ID9_DENORM_MODE, [21..19], R
+		field :ID9_ROUND_TRUNC_MODE, [25..22], R
+		field :ID9_DITHER_EN, [26], R
+		field :ID9_DITHER_MODE, [28..27], R
+	end
+*/
+
+#define TF_DEBUG_REG_LIST_SH_DCN10 \
+	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
+	.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
+
+#define TF_DEBUG_REG_LIST_MASK_DCN10 \
+	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
+	.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000
+
 #define TF_REG_FIELD_LIST(type) \
 	type EXT_OVERSCAN_LEFT; \
 	type EXT_OVERSCAN_RIGHT; \
@@ -1015,6 +1050,7 @@
 	type CM_BYPASS; \
 	type CM_TEST_DEBUG_INDEX; \
 	type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
+	type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
 	type FORMAT_CONTROL__ALPHA_EN; \
 	type CUR0_COLOR0; \
 	type CUR0_COLOR1; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index cc511415caee..4f373c97804f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -216,41 +216,55 @@ static void dpp1_cm_program_color_matrix(
 		struct dcn10_dpp *dpp,
 		const uint16_t *regval)
 {
-	uint32_t mode;
+	uint32_t ocsc_mode;
+	uint32_t cur_mode;
 	struct color_matrices_reg gam_regs;
 
-	REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
-
 	if (regval == NULL) {
 		BREAK_TO_DEBUGGER();
 		return;
 	}
-	mode = 4;
+
+	/* determine which CSC matrix (ocsc or comb) we are using
+	 * currently.  select the alternate set to double buffer
+	 * the CSC update so CSC is updated on frame boundary
+	 */
+	REG_SET(CM_TEST_DEBUG_INDEX, 0,
+			CM_TEST_DEBUG_INDEX, 9);
+
+	REG_GET(CM_TEST_DEBUG_DATA,
+			CM_TEST_DEBUG_DATA_ID9_OCSC_MODE, &cur_mode);
+
+	if (cur_mode != 4)
+		ocsc_mode = 4;
+	else
+		ocsc_mode = 5;
+
+
 	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
 	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_OCSC_C11;
 	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
 	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
 
-	if (mode == 4) {
+	if (ocsc_mode == 4) {
 
 		gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
 		gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
 
-		cm_helper_program_color_matrices(
-				dpp->base.ctx,
-				regval,
-				&gam_regs);
-
 	} else {
 
 		gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
 		gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
 
-		cm_helper_program_color_matrices(
-				dpp->base.ctx,
-				regval,
-				&gam_regs);
 	}
+
+	cm_helper_program_color_matrices(
+			dpp->base.ctx,
+			regval,
+			&gam_regs);
+
+	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
+
 }
 
 void dpp1_cm_set_output_csc_default(
@@ -260,7 +274,6 @@ void dpp1_cm_set_output_csc_default(
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 	const uint16_t *regval = NULL;
 	int arr_size;
-	uint32_t ocsc_mode = 4;
 
 	regval = find_color_matrix(colorspace, &arr_size);
 	if (regval == NULL) {
@@ -269,7 +282,6 @@ void dpp1_cm_set_output_csc_default(
 	}
 
 	dpp1_cm_program_color_matrix(dpp, regval);
-	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 }
 
 static void dpp1_cm_get_reg_field(
@@ -330,10 +342,8 @@ void dpp1_cm_set_output_csc_adjustment(
 		const uint16_t *regval)
 {
 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-	uint32_t ocsc_mode = 4;
 
 	dpp1_cm_program_color_matrix(dpp, regval);
-	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 }
 
 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index d321da97217c..7ad290cbc730 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -319,41 +319,15 @@ static const struct dcn_dpp_registers tf_regs[] = {
 	tf_regs(3),
 };
 
-/*
- *
-	DCN1 CM debug status register definition
-
-	register :ID9_CM_STATUS do
-	implement_ref :cm
-	map to:  :cmdebugind, at: j
-	width 32
-	disclosure   NEVER
-
-		field :ID9_VUPDATE_CFG, [0], R
-		field :ID9_IGAM_LUT_MODE, [2..1], R
-		field :ID9_BNS_BYPASS, [3], R
-		field :ID9_ICSC_MODE, [5..4], R
-		field :ID9_DGAM_LUT_MODE, [8..6], R
-		field :ID9_HDR_BYPASS, [9], R
-		field :ID9_GAMUT_REMAP_MODE, [11..10], R
-		field :ID9_RGAM_LUT_MODE, [14..12], R
-		#1 free bit
-		field :ID9_OCSC_MODE, [18..16], R
-		field :ID9_DENORM_MODE, [21..19], R
-		field :ID9_ROUND_TRUNC_MODE, [25..22], R
-		field :ID9_DITHER_EN, [26], R
-		field :ID9_DITHER_MODE, [28..27], R
-	end
-*/
-
 static const struct dcn_dpp_shift tf_shift = {
 	TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
-	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x4
+	TF_DEBUG_REG_LIST_SH_DCN10
+
 };
 
 static const struct dcn_dpp_mask tf_mask = {
 	TF_REG_LIST_SH_MASK_DCN10(_MASK),
-	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30
+	TF_DEBUG_REG_LIST_MASK_DCN10
 };
 
 static const struct dcn_mpc_registers mpc_regs = {
-- 
2.14.1

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  parent reply	other threads:[~2018-03-20 19:12 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-20 19:12 [PATCH 00/34] DC Patches Mar 20, 2018 Harry Wentland
     [not found] ` <20180320191259.14453-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-20 19:12   ` [PATCH 01/34] drm/amd/display: correct the condition in setting cursor not visible beyond left edge Harry Wentland
2018-03-20 19:12   ` [PATCH 02/34] drm/amd/display: dal 3.1.39 Harry Wentland
2018-03-20 19:12   ` [PATCH 03/34] drm/amd/display: Allow truncation to 10 bits Harry Wentland
2018-03-20 19:12   ` [PATCH 04/34] drm/amd/display: Fix FMT truncation programming Harry Wentland
2018-03-20 19:12   ` [PATCH 05/34] drm/amd/display: We shouldn't set format_default on plane as atomic driver Harry Wentland
2018-03-20 19:12   ` [PATCH 06/34] drm/amd/display: Retry when read dpcd caps failed Harry Wentland
2018-03-20 19:12   ` [PATCH 07/34] drm/amd/display: Add one to EDID's audio channel count when passing to DC Harry Wentland
2018-03-20 19:12   ` [PATCH 08/34] drm/amd/display: Update ASIC header files Harry Wentland
2018-03-20 19:12   ` [PATCH 09/34] drm/amd/display: fix lexa bw bounding box Harry Wentland
     [not found]     ` <20180320191259.14453-10-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-21  1:27       ` Zhang, Jerry (Junwei)
2018-03-22 18:39       ` [PATCH v2] drm/amd/display: fix Polaris 12 " Harry Wentland
     [not found]         ` <20180322183957.11419-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-22 18:51           ` Deucher, Alexander
2018-03-20 19:12   ` [PATCH 10/34] drm/amd/display: Rename feature-specific register address init macro Harry Wentland
2018-03-20 19:12   ` [PATCH 11/34] drm/amd/display: Don't read EDID in atomic_check Harry Wentland
2018-03-20 19:12   ` [PATCH 12/34] drm/amd/display: add mpc to dtn log Harry Wentland
2018-03-20 19:12   ` [PATCH 13/34] drm/amd/display: Add debug prints for bandwidth calculations Harry Wentland
2018-03-20 19:12   ` [PATCH 14/34] drm/amd/display: Don't call amdgpu_dm_display_resume as it doesn't exist Harry Wentland
2018-03-20 19:12   ` [PATCH 15/34] drm/amd/display: Adding stutter entry wm to dce bw struct Harry Wentland
2018-03-20 19:12   ` [PATCH 16/34] drm/amd/display: Change wb_h/vratio to double Harry Wentland
2018-03-20 19:12   ` [PATCH 17/34] drm/amd/display: drop dc_validate_guaranteed Harry Wentland
2018-03-20 19:12   ` [PATCH 18/34] drm/amd/display: Implementing new bandwidth registers for DCE120 Harry Wentland
2018-03-20 19:12   ` [PATCH 19/34] drm/amd/display: dal 3.1.40 Harry Wentland
2018-03-20 19:12   ` [PATCH 20/34] drm/amd/display: align dtn logs and add mpc idle bit print Harry Wentland
2018-03-20 19:12   ` [PATCH 21/34] drm/amd/display: add assert in enable FBC Harry Wentland
2018-03-20 19:12   ` [PATCH 22/34] drm/amd/display: Separate mem input constuctors for dce 112 and 120 Harry Wentland
2018-03-20 19:12   ` [PATCH 23/34] drm/amd/display: Only update mpc blend config if not full update Harry Wentland
2018-03-20 19:12   ` [PATCH 24/34] drm/amd/display: hide inconsistent mpcc programming from dtn log Harry Wentland
2018-03-20 19:12   ` [PATCH 25/34] drm/amd/display: Add dc_lut_mode enum Harry Wentland
2018-03-20 19:12   ` [PATCH 26/34] drm/amd/display: Correct print types in DC_LOGS Harry Wentland
2018-03-20 19:12   ` [PATCH 27/34] drm/amd/display: Add num_active_wb to DML Harry Wentland
2018-03-20 19:12   ` [PATCH 28/34] drm/amd/display: Add double buffer machanism to ICSC Harry Wentland
2018-03-20 19:12   ` [PATCH 29/34] drm/amd/display: Couple bug fixes in stats module Harry Wentland
2018-03-20 19:12   ` [PATCH 30/34] drm/amd/display: Rename encoder_info_packet to dc_info_packet Harry Wentland
2018-03-20 19:12   ` [PATCH 31/34] drm/amd/display: Add vline IRQ programming for DCN Harry Wentland
2018-03-20 19:12   ` Harry Wentland [this message]
2018-03-20 19:12   ` [PATCH 33/34] drm/amd/display: Only program MSA_TIMING_PARAM if it changed Harry Wentland
2018-03-20 19:12   ` [PATCH 34/34] drm/amd/display: Move commit_planes_to_stream to amdgpu_dm Harry Wentland

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