[PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg for INSTDONE.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip

Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h        |  1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9c3b2b..d902c50 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2296,6 +2296,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
 #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
+#define INTEL_SSEU(dev_priv)	((dev_priv)->info.sseu)
 
 #define REVID_FOREVER		0xff
 #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index de09fa4..cc19e0a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 	}
 }
 
+static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
+{
+	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
+	u32 slice = fls(sseu->slice_mask);
+	u32 subslice = fls(sseu->subslice_mask[slice]);
+
+	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+	return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+	u32 mcr;
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr = calculate_mcr(mcr, dev_priv);
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 		  int subslice, i915_reg_t reg)
@@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
 	/*
 	 * The HW expects the slice and sublice selectors to be reset to 0
 	 * after reading out the registers.
 	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	if (INTEL_GEN(dev_priv) < 10)
+		WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~mcr_slice_subslice_mask;
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+	 * expects mcr to be programed to a enabled slice/subslice pair
+	 * before any MMIO read into slice/subslice register
+	 */
+	if (INTEL_GEN(dev_priv) < 10)
+		mcr &= ~mcr_slice_subslice_mask;
+	else
+		mcr = calculate_mcr(mcr, dev_priv);
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+	wa_init_mcr(dev_priv);
+
 	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
 	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
 		I915_WRITE(GAMT_CHKN_BIT_REG,
-- 
2.7.4

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[PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip

Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
 drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da2f6c6..8436657 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2531,6 +2531,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index cc19e0a..3eb763c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -811,7 +811,25 @@ static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
 	u32 mcr;
+	u32 fuse3;
+	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
+	u32 slice;
 
+	/* If more than one slice are enabled, L3Banks should be all enabled */
+	if (is_power_of_2(sseu->slice_mask)) {
+		/*
+		 * WaProgramMgsrForL3BankSpecificMmioReads:
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		slice = fls(sseu->slice_mask);
+		fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		if (WARN_ON(!((fuse3 & GEN10_L3BANK_MASK)
+			       & ((sseu->subslice_mask[slice]
+			       | sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)
+			       & GEN10_L3BANK_MASK))))
+			DRM_WARN("Production silicon should have matched L3Bank and subslice enabled\n");
+	}
 	mcr = I915_READ(GEN8_MCR_SELECTOR);
 	mcr = calculate_mcr(mcr, dev_priv);
 	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
-- 
2.7.4

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[PATCH v4 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v4:
 - Added referecens (Mika)

References: HSDES#1405586840

Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
 drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1bca695f..4f2f5e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2691,6 +2691,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index cc19e0a..3eb763c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -811,7 +811,25 @@ static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
 	u32 mcr;
+	u32 fuse3;
+	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
+	u32 slice;
 
+	/* If more than one slice are enabled, L3Banks should be all enabled */
+	if (is_power_of_2(sseu->slice_mask)) {
+		/*
+		 * WaProgramMgsrForL3BankSpecificMmioReads:
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		slice = fls(sseu->slice_mask);
+		fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		if (WARN_ON(!((fuse3 & GEN10_L3BANK_MASK)
+			       & ((sseu->subslice_mask[slice]
+			       | sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)
+			       & GEN10_L3BANK_MASK))))
+			DRM_WARN("Production silicon should have matched L3Bank and subslice enabled\n");
+	}
 	mcr = I915_READ(GEN8_MCR_SELECTOR);
 	mcr = calculate_mcr(mcr, dev_priv);
 	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
-- 
2.7.4

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Re: [PATCH v4 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Tvrtko Ursulin]

On 26/03/2018 17:12, Yunwei Zhang wrote:
> L3Bank could be fused off in hardware for debug purpose, and it
> is possible that subslice is enabled while its corresponding L3Bank pairs
> are disabled. In such case, if MCR packet control register(0xFDC) is
> programed to point to a disabled bank pair, a MMIO read into L3Bank range
> will return 0 instead of correct values.
> 
> However, this is not going to be the case in any production silicon.
> Therefore, we only check at initialization and issue a warning should
> this really happen.
> 
> v2:
>   - use fls instead of find_last_bit (Chris)
>   - use is_power_of_2() instead of counting bit set (Chris)
> v3:
>   - rebase on latest tip
> v4:
>   - Added referecens (Mika)
> 
> References: HSDES#1405586840
> 
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
>   drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++++++++++++++++++
>   2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1bca695f..4f2f5e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2691,6 +2691,10 @@ enum i915_power_well_id {
>   #define   GEN10_F2_SS_DIS_SHIFT		18
>   #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>   
> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT     4
> +#define GEN10_L3BANK_MASK   0x0F
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index cc19e0a..3eb763c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -811,7 +811,25 @@ static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
>   static void wa_init_mcr(struct drm_i915_private *dev_priv)
>   {
>   	u32 mcr;
> +	u32 fuse3;
> +	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
> +	u32 slice;

fuse3 and slice can be moved into the is_power_of_2 block below.

>   
> +	/* If more than one slice are enabled, L3Banks should be all enabled */
> +	if (is_power_of_2(sseu->slice_mask)) {
> +		/*
> +		 * WaProgramMgsrForL3BankSpecificMmioReads:
> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +		 * enabled subslice, no need to redirect MCR packet
> +		 */
> +		slice = fls(sseu->slice_mask);
> +		fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> +		if (WARN_ON(!((fuse3 & GEN10_L3BANK_MASK)
> +			       & ((sseu->subslice_mask[slice]
> +			       | sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)

Spaces around operators to satisfy checkpatch.

> +			       & GEN10_L3BANK_MASK))))

Whole conditional is a bit hard to read (maybe it is just me!) so maybe 
store sseu->subslice_mask[slice] to a local? Not sure if that would make 
it better.

> +			DRM_WARN("Production silicon should have matched L3Bank and subslice enabled\n");

Aren't both WARN_ON and DRM_WARN an overkill? One should be enough I hope.

> +	}
>   	mcr = I915_READ(GEN8_MCR_SELECTOR);
>   	mcr = calculate_mcr(mcr, dev_priv);
>   	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> 

Regards,

Tvrtko
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[PATCH v5 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
 drivers/gpu/drm/i915/intel_engine_cs.c | 20 ++++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1bca695f..4f2f5e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2691,6 +2691,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4c78d1e..7be7a75 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -811,6 +811,26 @@ static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
 	u32 mcr;
+	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+
+	/* If more than one slice are enabled, L3Banks should be all enabled */
+	if (is_power_of_2(sseu->slice_mask)) {
+		/*
+		 * WaProgramMgsrForL3BankSpecificMmioReads:
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		u32 slice = fls(sseu->slice_mask);
+		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		u8 ss_mask = sseu->subslice_mask[slice];
+		/*
+		 * Production silicon should have matched L3Bank and
+		 * subslice enabled
+		 */
+		WARN_ON(!((fuse3 & GEN10_L3BANK_MASK) &
+			  ((ss_mask | ss_mask >> GEN10_L3BANK_PAIR_COUNT) &
+			   GEN10_L3BANK_MASK)));
+	}
 
 	mcr = I915_READ(GEN8_MCR_SELECTOR);
 	mcr = calculate_mcr(dev_priv, mcr);
-- 
2.7.4

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Re: [PATCH v5 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Tvrtko Ursulin]

On 27/03/2018 23:14, Yunwei Zhang wrote:
> L3Bank could be fused off in hardware for debug purpose, and it
> is possible that subslice is enabled while its corresponding L3Bank pairs
> are disabled. In such case, if MCR packet control register(0xFDC) is
> programed to point to a disabled bank pair, a MMIO read into L3Bank range
> will return 0 instead of correct values.
> 
> However, this is not going to be the case in any production silicon.
> Therefore, we only check at initialization and issue a warning should
> this really happen.
> 
> References: HSDES#1405586840
> 
> v2:
>   - use fls instead of find_last_bit (Chris)
>   - use is_power_of_2() instead of counting bit set (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Move local variable into scope where they are used (Ursulin)
>   - use a new local variable to reduce long line of code (Ursulin)
> 
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
>   drivers/gpu/drm/i915/intel_engine_cs.c | 20 ++++++++++++++++++++
>   2 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1bca695f..4f2f5e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2691,6 +2691,10 @@ enum i915_power_well_id {
>   #define   GEN10_F2_SS_DIS_SHIFT		18
>   #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>   
> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT     4
> +#define GEN10_L3BANK_MASK   0x0F
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 4c78d1e..7be7a75 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -811,6 +811,26 @@ static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
>   static void wa_init_mcr(struct drm_i915_private *dev_priv)
>   {
>   	u32 mcr;
> +	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);

Another style nitpick - sorry I did not notice it before - we typically 
order assignments from functions arguments to locals first, then pure 
locals. Also we typically try to make the declaration block start wide 
and then narrow.

> +
> +	/* If more than one slice are enabled, L3Banks should be all enabled */

L3Banks should be all enabled, or enabled for all enabled slices? (That 
comment below says "should have _matched_".

> +	if (is_power_of_2(sseu->slice_mask)) {
> +		/*
> +		 * WaProgramMgsrForL3BankSpecificMmioReads:
> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +		 * enabled subslice, no need to redirect MCR packet
> +		 */

This comment implies there will be some action taken depending on this 
conditional relating to the MCR, but there is nothing there?

It is not clear to me what should and whether perhaps this comment 
should be pulled up and merged with the one above the conditional.

> +		u32 slice = fls(sseu->slice_mask);
> +		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> +		u8 ss_mask = sseu->subslice_mask[slice];

Insert blank line after declarations.

Also, is it correct to only consider the subslice mask of the last slice 
for this check?

> +		/*
> +		 * Production silicon should have matched L3Bank and
> +		 * subslice enabled
> +		 */
> +		WARN_ON(!((fuse3 & GEN10_L3BANK_MASK) &
> +			  ((ss_mask | ss_mask >> GEN10_L3BANK_PAIR_COUNT) & > +			   GEN10_L3BANK_MASK)));

Mask in fuse3 is the disabled mask right, since BSpec calls them "L3 
Bank Disable Select"?

Should you not be checking that none of the enabled slices have L3Bank 
disabled, while the above looks like it can miss a partial mismatch? 
Something like this:

u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
u8 disabled_mask = fuse3 & 0xf;

WARN_ON((enabled_mask & disabled_mask) != enabled_mask);

> +	}
>   
>   	mcr = I915_READ(GEN8_MCR_SELECTOR);
>   	mcr = calculate_mcr(dev_priv, mcr);
> 

Regards,

Tvrtko
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Re: [PATCH v5 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Tvrtko Ursulin]

On 28/03/2018 10:39, Tvrtko Ursulin wrote:
> 
> On 27/03/2018 23:14, Yunwei Zhang wrote:
>> L3Bank could be fused off in hardware for debug purpose, and it
>> is possible that subslice is enabled while its corresponding L3Bank pairs
>> are disabled. In such case, if MCR packet control register(0xFDC) is
>> programed to point to a disabled bank pair, a MMIO read into L3Bank range
>> will return 0 instead of correct values.
>>
>> However, this is not going to be the case in any production silicon.
>> Therefore, we only check at initialization and issue a warning should
>> this really happen.
>>
>> References: HSDES#1405586840
>>
>> v2:
>>   - use fls instead of find_last_bit (Chris)
>>   - use is_power_of_2() instead of counting bit set (Chris)
>> v3:
>>   - rebase on latest tip
>> v5:
>>   - Added references (Mika)
>>   - Move local variable into scope where they are used (Ursulin)
>>   - use a new local variable to reduce long line of code (Ursulin)
>>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 20 ++++++++++++++++++++
>>   2 files changed, 24 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 1bca695f..4f2f5e1 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2691,6 +2691,10 @@ enum i915_power_well_id {
>>   #define   GEN10_F2_SS_DIS_SHIFT        18
>>   #define   GEN10_F2_SS_DIS_MASK        (0xf << GEN10_F2_SS_DIS_SHIFT)
>> +#define    GEN10_MIRROR_FUSE3        _MMIO(0x9118)
>> +#define GEN10_L3BANK_PAIR_COUNT     4
>> +#define GEN10_L3BANK_MASK   0x0F
>> +
>>   #define GEN8_EU_DISABLE0        _MMIO(0x9134)
>>   #define   GEN8_EU_DIS0_S0_MASK        0xffffff
>>   #define   GEN8_EU_DIS0_S1_SHIFT        24
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
>> b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 4c78d1e..7be7a75 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -811,6 +811,26 @@ static u32 calculate_mcr(struct drm_i915_private 
>> *dev_priv, u32 mcr)
>>   static void wa_init_mcr(struct drm_i915_private *dev_priv)
>>   {
>>       u32 mcr;
>> +    const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> 
> Another style nitpick - sorry I did not notice it before - we typically 
> order assignments from functions arguments to locals first, then pure 
> locals. Also we typically try to make the declaration block start wide 
> and then narrow.
> 
>> +
>> +    /* If more than one slice are enabled, L3Banks should be all 
>> enabled */
> 
> L3Banks should be all enabled, or enabled for all enabled slices? (That 
> comment below says "should have _matched_".
> 
>> +    if (is_power_of_2(sseu->slice_mask)) {
>> +        /*
>> +         * WaProgramMgsrForL3BankSpecificMmioReads:
>> +         * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>> +         * enabled subslice, no need to redirect MCR packet
>> +         */
> 
> This comment implies there will be some action taken depending on this 
> conditional relating to the MCR, but there is nothing there?
> 
> It is not clear to me what should and whether perhaps this comment 
> should be pulled up and merged with the one above the conditional.
> 
>> +        u32 slice = fls(sseu->slice_mask);
>> +        u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
>> +        u8 ss_mask = sseu->subslice_mask[slice];
> 
> Insert blank line after declarations.
> 
> Also, is it correct to only consider the subslice mask of the last slice 
> for this check?
> 
>> +        /*
>> +         * Production silicon should have matched L3Bank and
>> +         * subslice enabled
>> +         */
>> +        WARN_ON(!((fuse3 & GEN10_L3BANK_MASK) &
>> +              ((ss_mask | ss_mask >> GEN10_L3BANK_PAIR_COUNT) & > 
>> +               GEN10_L3BANK_MASK)));
> 
> Mask in fuse3 is the disabled mask right, since BSpec calls them "L3 
> Bank Disable Select"?
> 
> Should you not be checking that none of the enabled slices have L3Bank 
> disabled, while the above looks like it can miss a partial mismatch? 
> Something like this:
> 
> u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
> u8 disabled_mask = fuse3 & 0xf;
> 
> WARN_ON((enabled_mask & disabled_mask) != enabled_mask);

Oops no, that's wrong, should be "(enabled_mask & ~disabled_mask) != 
enabled_mask)" I think. Which is then the same as WARN_ON(enabled_mask & 
disabled_mask) - aka same bit is both enabled and disabled - so maybe I 
got the meaning of "L3 Bank Disable Select" wrong.

Regards,

Tvrtko

> 
>> +    }
>>       mcr = I915_READ(GEN8_MCR_SELECTOR);
>>       mcr = calculate_mcr(dev_priv, mcr);
>>
> 
> Regards,
> 
> Tvrtko
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Re: [PATCH v5 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Zhang, Yunwei]

On 3/28/2018 2:39 AM, Tvrtko Ursulin wrote:
>
> On 27/03/2018 23:14, Yunwei Zhang wrote:
>> L3Bank could be fused off in hardware for debug purpose, and it
>> is possible that subslice is enabled while its corresponding L3Bank 
>> pairs
>> are disabled. In such case, if MCR packet control register(0xFDC) is
>> programed to point to a disabled bank pair, a MMIO read into L3Bank 
>> range
>> will return 0 instead of correct values.
>>
>> However, this is not going to be the case in any production silicon.
>> Therefore, we only check at initialization and issue a warning should
>> this really happen.
>>
>> References: HSDES#1405586840
>>
>> v2:
>>   - use fls instead of find_last_bit (Chris)
>>   - use is_power_of_2() instead of counting bit set (Chris)
>> v3:
>>   - rebase on latest tip
>> v5:
>>   - Added references (Mika)
>>   - Move local variable into scope where they are used (Ursulin)
>>   - use a new local variable to reduce long line of code (Ursulin)
>>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 20 ++++++++++++++++++++
>>   2 files changed, 24 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 1bca695f..4f2f5e1 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2691,6 +2691,10 @@ enum i915_power_well_id {
>>   #define   GEN10_F2_SS_DIS_SHIFT        18
>>   #define   GEN10_F2_SS_DIS_MASK        (0xf << GEN10_F2_SS_DIS_SHIFT)
>>   +#define    GEN10_MIRROR_FUSE3        _MMIO(0x9118)
>> +#define GEN10_L3BANK_PAIR_COUNT     4
>> +#define GEN10_L3BANK_MASK   0x0F
>> +
>>   #define GEN8_EU_DISABLE0        _MMIO(0x9134)
>>   #define   GEN8_EU_DIS0_S0_MASK        0xffffff
>>   #define   GEN8_EU_DIS0_S1_SHIFT        24
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
>> b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 4c78d1e..7be7a75 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -811,6 +811,26 @@ static u32 calculate_mcr(struct drm_i915_private 
>> *dev_priv, u32 mcr)
>>   static void wa_init_mcr(struct drm_i915_private *dev_priv)
>>   {
>>       u32 mcr;
>> +    const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
>
> Another style nitpick - sorry I did not notice it before - we 
> typically order assignments from functions arguments to locals first, 
> then pure locals. Also we typically try to make the declaration block 
> start wide and then narrow.
>
>> +
>> +    /* If more than one slice are enabled, L3Banks should be all 
>> enabled */
>
> L3Banks should be all enabled, or enabled for all enabled slices? 
> (That comment below says "should have _matched_".
See comment below
>
>> +    if (is_power_of_2(sseu->slice_mask)) {
>> +        /*
>> +         * WaProgramMgsrForL3BankSpecificMmioReads:
>> +         * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>> +         * enabled subslice, no need to redirect MCR packet
>> +         */
>
> This comment implies there will be some action taken depending on this 
> conditional relating to the MCR, but there is nothing there?
>
> It is not clear to me what should and whether perhaps this comment 
> should be pulled up and merged with the one above the conditional.
This WA(L3Bank but not the slice/subslice) is not meant to exist on 
production silicon, I am not sure in this case whether we should 
implement/upstream the WA. So we did this also to solicit suggestions.
That is why in case of L3Banks somehow do get fused off, we issue a 
warning instead of programming MCR register.
>
>> +        u32 slice = fls(sseu->slice_mask);
>> +        u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
>> +        u8 ss_mask = sseu->subslice_mask[slice];
>
> Insert blank line after declarations.
>
> Also, is it correct to only consider the subslice mask of the last 
> slice for this check?
The case only exists on 1 enabled slice scenario, if there are two or 
more slices enabled, no subslice will be fused off.
>
>> +        /*
>> +         * Production silicon should have matched L3Bank and
>> +         * subslice enabled
>> +         */
>> +        WARN_ON(!((fuse3 & GEN10_L3BANK_MASK) &
>> +              ((ss_mask | ss_mask >> GEN10_L3BANK_PAIR_COUNT) & > + 
>> GEN10_L3BANK_MASK)));
>
> Mask in fuse3 is the disabled mask right, since BSpec calls them "L3 
> Bank Disable Select"?
>
> Should you not be checking that none of the enabled slices have L3Bank 
> disabled, while the above looks like it can miss a partial mismatch? 
> Something like this:
>
> u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
> u8 disabled_mask = fuse3 & 0xf;
>
> WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
>
>> +    }
>>         mcr = I915_READ(GEN8_MCR_SELECTOR);
>>       mcr = calculate_mcr(dev_priv, mcr);
>>
>
> Regards,
>
> Tvrtko
Thanks,
Yunwei
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[PATCH v6 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)
v6:
 - Some coding style change and uses of local variables for clearer
   logic (Ursulin)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
 drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 32c297a..994870f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2697,6 +2697,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4c50bee..57f4c35 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -810,8 +810,33 @@ static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
 
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
+	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
 	u32 mcr;
 
+	/*
+	 * L3Banks could be fused off in single slice scenario, however, if
+	 * more than one slice is enabled, this should not happen.
+	 */
+	if (is_power_of_2(sseu->slice_mask)) {
+		/*
+		 * WaProgramMgsrForL3BankSpecificMmioReads:
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		u32 slice = fls(sseu->slice_mask);
+		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		u8 ss_mask = sseu->subslice_mask[slice];
+
+		u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
+		u8 disabled_mask = fuse3 & 0xf;
+
+		/*
+		 * Production silicon should have matched L3Bank and
+		 * subslice enabled
+		 */
+		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+	}
+
 	mcr = I915_READ(GEN8_MCR_SELECTOR);
 	mcr = calculate_mcr(dev_priv, mcr);
 	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
-- 
2.7.4

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[PATCH v7 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)
v6:
 - Some coding style and use more local variables for clearer
   logic (Ursulin)
v7:
 - Rebased.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
 drivers/gpu/drm/i915/intel_workarounds.c | 25 +++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..6c9c01b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2709,6 +2709,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 8a2354e..fe1c908 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -647,8 +647,33 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
+	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
 	u32 mcr;
 
+	/*
+	 * L3Banks could be fused off in single slice scenario, however, if
+	 * more than one slice is enabled, this should not happen.
+	 */
+	if (is_power_of_2(sseu->slice_mask)) {
+		/*
+		 * WaProgramMgsrForL3BankSpecificMmioReads:
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		u32 slice = fls(sseu->slice_mask);
+		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		u8 ss_mask = sseu->subslice_mask[slice];
+
+		u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
+		u8 disabled_mask = fuse3 & 0xf;
+
+		/*
+		 * Production silicon should have matched L3Bank and
+		 * subslice enabled
+		 */
+		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+	}
+
 	mcr = I915_READ(GEN8_MCR_SELECTOR);
 	mcr = calculate_mcr(dev_priv, mcr);
 	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
-- 
2.7.4

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Re: [PATCH v7 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Oscar Mateo]

On 04/16/2018 02:24 PM, Yunwei Zhang wrote:
> L3Bank could be fused off in hardware for debug purpose, and it
> is possible that subslice is enabled while its corresponding L3Bank pairs
> are disabled. In such case, if MCR packet control register(0xFDC) is
> programed to point to a disabled bank pair, a MMIO read into L3Bank range
> will return 0 instead of correct values.
>
> However, this is not going to be the case in any production silicon.
> Therefore, we only check at initialization and issue a warning should
> this really happen.
>
> References: HSDES#1405586840
>
> v2:
>   - use fls instead of find_last_bit (Chris)
>   - use is_power_of_2() instead of counting bit set (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Move local variable into scope where they are used (Ursulin)
>   - use a new local variable to reduce long line of code (Ursulin)
> v6:
>   - Some coding style and use more local variables for clearer
>     logic (Ursulin)
> v7:
>   - Rebased.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>   drivers/gpu/drm/i915/intel_workarounds.c | 25 +++++++++++++++++++++++++
>   2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..6c9c01b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2709,6 +2709,10 @@ enum i915_power_well_id {
>   #define   GEN10_F2_SS_DIS_SHIFT		18
>   #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>   
> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT     4
> +#define GEN10_L3BANK_MASK   0x0F
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 8a2354e..fe1c908 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -647,8 +647,33 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   
>   static void wa_init_mcr(struct drm_i915_private *dev_priv)
>   {
> +	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
>   	u32 mcr;
>   
> +	/*
> +	 * L3Banks could be fused off in single slice scenario, however, if
> +	 * more than one slice is enabled, this should not happen.
> +	 */
> +	if (is_power_of_2(sseu->slice_mask)) {
> +		/*
> +		 * WaProgramMgsrForL3BankSpecificMmioReads:
> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +		 * enabled subslice, no need to redirect MCR packet
> +		 */
> +		u32 slice = fls(sseu->slice_mask);
> +		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> +		u8 ss_mask = sseu->subslice_mask[slice];
> +
> +		u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
> +		u8 disabled_mask = fuse3 & 0xf;
> +
> +		/*
> +		 * Production silicon should have matched L3Bank and
> +		 * subslice enabled
> +		 */
> +		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> +	}
> +

Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

And this warning is also required for Icelake.

>   	mcr = I915_READ(GEN8_MCR_SELECTOR);
>   	mcr = calculate_mcr(dev_priv, mcr);
>   	I915_WRITE(GEN8_MCR_SELECTOR, mcr);

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[PATCH v8 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)
v6:
 - Some coding style and use more local variables for clearer
   logic (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
 drivers/gpu/drm/i915/intel_device_info.c | 23 +++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..6c9c01b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2709,6 +2709,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 2243a23..5a013fa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -729,6 +729,29 @@ static void wa_init_mcr(struct intel_device_info *info)
 	u32 slice = fls(info->sseu.slice_mask);
 	u32 subslice = fls(info->sseu.subslice_mask[slice]);
 
+	/*
+	 * L3Banks could be fused off in single slice scenario, however, if
+	 * more than one slice is enabled, this should not happen.
+	 */
+	if (is_power_of_2(info->sseu.slice_mask)) {
+		/*
+		 * WaProgramMgsrForL3BankSpecificMmioReads:
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		u8 ss_mask = info->sseu.subslice_mask[slice];
+
+		u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
+		u8 disabled_mask = fuse3 & 0xf;
+
+		/*
+		 * Production silicon should have matched L3Bank and
+		 * subslice enabled
+		 */
+		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+	}
+
 	if (INTEL_GEN(dev_priv) >= 11) {
 		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
 					  GEN11_MCR_SUBSLICE_MASK;
-- 
2.7.4

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Re: [PATCH v8 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Oscar Mateo]

On 4/17/2018 2:05 PM, Yunwei Zhang wrote:
> L3Bank could be fused off in hardware for debug purpose, and it
> is possible that subslice is enabled while its corresponding L3Bank pairs
> are disabled. In such case, if MCR packet control register(0xFDC) is
> programed to point to a disabled bank pair, a MMIO read into L3Bank range
> will return 0 instead of correct values.
>
> However, this is not going to be the case in any production silicon.
> Therefore, we only check at initialization and issue a warning should
> this really happen.
>
> References: HSDES#1405586840
>
> v2:
>   - use fls instead of find_last_bit (Chris)
>   - use is_power_of_2() instead of counting bit set (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Move local variable into scope where they are used (Ursulin)
>   - use a new local variable to reduce long line of code (Ursulin)
> v6:
>   - Some coding style and use more local variables for clearer
>     logic (Ursulin)
> v7:
>   - Rebased.
> v8:
>   - Reviewed by Oscar.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>   drivers/gpu/drm/i915/intel_device_info.c | 23 +++++++++++++++++++++++
>   2 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..6c9c01b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2709,6 +2709,10 @@ enum i915_power_well_id {
>   #define   GEN10_F2_SS_DIS_SHIFT		18
>   #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>   
> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT     4
> +#define GEN10_L3BANK_MASK   0x0F
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 2243a23..5a013fa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -729,6 +729,29 @@ static void wa_init_mcr(struct intel_device_info *info)
>   	u32 slice = fls(info->sseu.slice_mask);
>   	u32 subslice = fls(info->sseu.subslice_mask[slice]);
>   
> +	/*
> +	 * L3Banks could be fused off in single slice scenario, however, if
> +	 * more than one slice is enabled, this should not happen.
> +	 */
> +	if (is_power_of_2(info->sseu.slice_mask)) {
> +		/*
> +		 * WaProgramMgsrForL3BankSpecificMmioReads:
> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +		 * enabled subslice, no need to redirect MCR packet
> +		 */
> +		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> +		u8 ss_mask = info->sseu.subslice_mask[slice];
> +
> +		u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
> +		u8 disabled_mask = fuse3 & 0xf;
> +
> +		/*
> +		 * Production silicon should have matched L3Bank and
> +		 * subslice enabled
> +		 */
> +		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> +	}
> +

You have lost the WaProgramMgsrForL3BankSpecificMmioReads label here. 
Also, this check only makes sense for platforms where the WA is needed 
(Gen10+)

>   	if (INTEL_GEN(dev_priv) >= 11) {
>   		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>   					  GEN11_MCR_SUBSLICE_MASK;

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[PATCH v9 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)
v6:
 - Some coding style and use more local variables for clearer
   logic (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar.
v9:
 - Fixed label location. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
 drivers/gpu/drm/i915/intel_device_info.c | 23 +++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..6c9c01b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2709,6 +2709,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 1a4288f..530b6ba 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -729,6 +729,29 @@ static void sanitize_mcr(struct intel_device_info *info)
 	u32 slice = fls(info->sseu.slice_mask);
 	u32 subslice = fls(info->sseu.subslice_mask[slice]);
 
+	/*
+	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
+	 * L3Banks could be fused off in single slice scenario, however, if
+	 * more than one slice is enabled, this should not happen.
+	 */
+	if (is_power_of_2(info->sseu.slice_mask)) {
+		/*
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		u8 ss_mask = info->sseu.subslice_mask[slice];
+
+		u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
+		u8 disabled_mask = fuse3 & 0xf;
+
+		/*
+		 * Production silicon should have matched L3Bank and
+		 * subslice enabled
+		 */
+		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+	}
+
 	if (INTEL_GEN(dev_priv) >= 11) {
 		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
 					  GEN11_MCR_SUBSLICE_MASK;
-- 
2.7.4

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Re: [PATCH v9 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Oscar Mateo]

On 4/17/2018 3:59 PM, Yunwei Zhang wrote:
> L3Bank could be fused off in hardware for debug purpose, and it
> is possible that subslice is enabled while its corresponding L3Bank pairs
> are disabled. In such case, if MCR packet control register(0xFDC) is
> programed to point to a disabled bank pair, a MMIO read into L3Bank range
> will return 0 instead of correct values.
>
> However, this is not going to be the case in any production silicon.
> Therefore, we only check at initialization and issue a warning should
> this really happen.
>
> References: HSDES#1405586840
>
> v2:
>   - use fls instead of find_last_bit (Chris)
>   - use is_power_of_2() instead of counting bit set (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Move local variable into scope where they are used (Ursulin)
>   - use a new local variable to reduce long line of code (Ursulin)
> v6:
>   - Some coding style and use more local variables for clearer
>     logic (Ursulin)
> v7:
>   - Rebased.
> v8:
>   - Reviewed by Oscar.
> v9:
>   - Fixed label location. (Oscar)
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>   drivers/gpu/drm/i915/intel_device_info.c | 23 +++++++++++++++++++++++
>   2 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..6c9c01b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2709,6 +2709,10 @@ enum i915_power_well_id {
>   #define   GEN10_F2_SS_DIS_SHIFT		18
>   #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>   
> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT     4
> +#define GEN10_L3BANK_MASK   0x0F
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 1a4288f..530b6ba 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -729,6 +729,29 @@ static void sanitize_mcr(struct intel_device_info *info)
>   	u32 slice = fls(info->sseu.slice_mask);
>   	u32 subslice = fls(info->sseu.subslice_mask[slice]);
>   
> +	/*
> +	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> +	 * L3Banks could be fused off in single slice scenario, however, if
> +	 * more than one slice is enabled, this should not happen.
> +	 */
> +	if (is_power_of_2(info->sseu.slice_mask)) {

This WA is only required for GEN >= 10. In other GENs, 
GEN10_MIRROR_FUSE3 does not even exist!

> +		/*
> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +		 * enabled subslice, no need to redirect MCR packet
> +		 */
> +		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> +		u8 ss_mask = info->sseu.subslice_mask[slice];
> +
> +		u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
> +		u8 disabled_mask = fuse3 & 0xf;
> +

You defined GEN10_L3BANK_MASK. Might as well use it :)

> +		/*
> +		 * Production silicon should have matched L3Bank and
> +		 * subslice enabled
> +		 */
> +		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> +	}
> +
>   	if (INTEL_GEN(dev_priv) >= 11) {
>   		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>   					  GEN11_MCR_SUBSLICE_MASK;

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Re: [PATCH v9 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Oscar Mateo]

On 4/18/2018 9:40 AM, Oscar Mateo wrote:
>
>
> On 4/17/2018 3:59 PM, Yunwei Zhang wrote:
>> L3Bank could be fused off in hardware for debug purpose, and it
>> is possible that subslice is enabled while its corresponding L3Bank 
>> pairs
>> are disabled. In such case, if MCR packet control register(0xFDC) is
>> programed to point to a disabled bank pair, a MMIO read into L3Bank 
>> range
>> will return 0 instead of correct values.
>>
>> However, this is not going to be the case in any production silicon.
>> Therefore, we only check at initialization and issue a warning should
>> this really happen.
>>
>> References: HSDES#1405586840
>>
>> v2:
>>   - use fls instead of find_last_bit (Chris)
>>   - use is_power_of_2() instead of counting bit set (Chris)
>> v3:
>>   - rebase on latest tip
>> v5:
>>   - Added references (Mika)
>>   - Move local variable into scope where they are used (Ursulin)
>>   - use a new local variable to reduce long line of code (Ursulin)
>> v6:
>>   - Some coding style and use more local variables for clearer
>>     logic (Ursulin)
>> v7:
>>   - Rebased.
>> v8:
>>   - Reviewed by Oscar.
>> v9:
>>   - Fixed label location. (Oscar)
>>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>>   drivers/gpu/drm/i915/intel_device_info.c | 23 +++++++++++++++++++++++
>>   2 files changed, 27 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index fb10602..6c9c01b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2709,6 +2709,10 @@ enum i915_power_well_id {
>>   #define   GEN10_F2_SS_DIS_SHIFT        18
>>   #define   GEN10_F2_SS_DIS_MASK        (0xf << GEN10_F2_SS_DIS_SHIFT)
>>   +#define    GEN10_MIRROR_FUSE3        _MMIO(0x9118)
>> +#define GEN10_L3BANK_PAIR_COUNT     4
>> +#define GEN10_L3BANK_MASK   0x0F
>> +
>>   #define GEN8_EU_DISABLE0        _MMIO(0x9134)
>>   #define   GEN8_EU_DIS0_S0_MASK        0xffffff
>>   #define   GEN8_EU_DIS0_S1_SHIFT        24
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index 1a4288f..530b6ba 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -729,6 +729,29 @@ static void sanitize_mcr(struct 
>> intel_device_info *info)
>>       u32 slice = fls(info->sseu.slice_mask);
>>       u32 subslice = fls(info->sseu.subslice_mask[slice]);
>>   +    /*
>> +     * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
>> +     * L3Banks could be fused off in single slice scenario, however, if
>> +     * more than one slice is enabled, this should not happen.
>> +     */

Maybe a better explanation is warranted:

/*
  * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
  * L3Banks could be fused off in single slice scenario. If that is the 
case,
  * we might need to program MCR select to a valid L3Bank by default,
  * to make sure we correctly read certain registers later on
* (in the range 0xB100 - 0xB3FF).
  * This might be incompatible with 
WaProgramMgsrForCorrectSliceSpecificMmioReads.
  * Fortunately, this should not happen in production hardware, so we only
  * assert that this is the case (instead of implementing something more 
complex
  * that requires checking the range of every MMIO read).
  */

>> +    if (is_power_of_2(info->sseu.slice_mask)) {
>
> This WA is only required for GEN >= 10. In other GENs, 
> GEN10_MIRROR_FUSE3 does not even exist!
>
>> +        /*
>> +         * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>> +         * enabled subslice, no need to redirect MCR packet
>> +         */
>> +        u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
>> +        u8 ss_mask = info->sseu.subslice_mask[slice];
>> +
>> +        u8 enabled_mask = (ss_mask | ss_mask >> 4) & 0xf;
>> +        u8 disabled_mask = fuse3 & 0xf;
>> +
>
> You defined GEN10_L3BANK_MASK. Might as well use it :)
>
>> +        /*
>> +         * Production silicon should have matched L3Bank and
>> +         * subslice enabled
>> +         */
>> +        WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
>> +    }
>> +
>>       if (INTEL_GEN(dev_priv) >= 11) {
>>           mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>>                         GEN11_MCR_SUBSLICE_MASK;
>

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[PATCH v10 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)
v6:
 - Some coding style and use more local variables for clearer
   logic (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar.
v9:
 - Fixed label location. (Oscar)
v10:
 - Improved comments and replaced magical number. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
 drivers/gpu/drm/i915/intel_device_info.c | 34 ++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..6c9c01b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2709,6 +2709,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3791b52..a42842d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -741,6 +741,40 @@ static void sanitize_mcr(struct intel_device_info *info)
 	u32 slice = fls(info->sseu.slice_mask);
 	u32 subslice = fls(info->sseu.subslice_mask[slice]);
 
+	/*
+	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
+	 * L3Banks could be fused off in single slice scenario. If that is
+	 * the case, we might need to program MCR select to a valid L3Bank
+	 * by default, to make sure we correctly read certain registers
+	 * later on (in the range 0xB100 - 0xB3FF).
+	 * This might be incompatible with
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads.
+	 * Fortunately, this should not happen in production hardware, so
+	 * we only assert that this is the case (instead of implementing
+	 * something more complex that requires checking the range of every
+	 * MMIO read).
+	 */
+	if (INTEL_GEN(dev_priv) >= 10 &&
+	    is_power_of_2(info->sseu.slice_mask)) {
+		/*
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		u8 ss_mask = info->sseu.subslice_mask[slice];
+
+		u8 enabled_mask = (ss_mask | ss_mask >>
+				   GEN10_L3BANK_PAIR_COUNT) &
+				   GEN10_L3BANK_MASK;
+		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
+
+		/*
+		 * Production silicon should have matched L3Bank and
+		 * subslice enabled
+		 */
+		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+	}
+
 	if (INTEL_GEN(dev_priv) >= 11) {
 		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
 					  GEN11_MCR_SUBSLICE_MASK;
-- 
2.7.4

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Re: [PATCH v10 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Oscar Mateo]

On 4/18/2018 1:23 PM, Yunwei Zhang wrote:
> L3Bank could be fused off in hardware for debug purpose, and it
> is possible that subslice is enabled while its corresponding L3Bank pairs
> are disabled. In such case, if MCR packet control register(0xFDC) is
> programed to point to a disabled bank pair, a MMIO read into L3Bank range
> will return 0 instead of correct values.
>
> However, this is not going to be the case in any production silicon.
> Therefore, we only check at initialization and issue a warning should
> this really happen.
>
> References: HSDES#1405586840
>
> v2:
>   - use fls instead of find_last_bit (Chris)
>   - use is_power_of_2() instead of counting bit set (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Move local variable into scope where they are used (Ursulin)
>   - use a new local variable to reduce long line of code (Ursulin)
> v6:
>   - Some coding style and use more local variables for clearer
>     logic (Ursulin)
> v7:
>   - Rebased.
> v8:
>   - Reviewed by Oscar.
> v9:
>   - Fixed label location. (Oscar)
> v10:
>   - Improved comments and replaced magical number. (Oscar)
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

Re-
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>   drivers/gpu/drm/i915/intel_device_info.c | 34 ++++++++++++++++++++++++++++++++
>   2 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..6c9c01b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2709,6 +2709,10 @@ enum i915_power_well_id {
>   #define   GEN10_F2_SS_DIS_SHIFT		18
>   #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>   
> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT     4
> +#define GEN10_L3BANK_MASK   0x0F
> +
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>   #define   GEN8_EU_DIS0_S1_SHIFT		24
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 3791b52..a42842d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -741,6 +741,40 @@ static void sanitize_mcr(struct intel_device_info *info)
>   	u32 slice = fls(info->sseu.slice_mask);
>   	u32 subslice = fls(info->sseu.subslice_mask[slice]);
>   
> +	/*
> +	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> +	 * L3Banks could be fused off in single slice scenario. If that is
> +	 * the case, we might need to program MCR select to a valid L3Bank
> +	 * by default, to make sure we correctly read certain registers
> +	 * later on (in the range 0xB100 - 0xB3FF).
> +	 * This might be incompatible with
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads.
> +	 * Fortunately, this should not happen in production hardware, so
> +	 * we only assert that this is the case (instead of implementing
> +	 * something more complex that requires checking the range of every
> +	 * MMIO read).
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 10 &&
> +	    is_power_of_2(info->sseu.slice_mask)) {
> +		/*
> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +		 * enabled subslice, no need to redirect MCR packet
> +		 */
> +		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> +		u8 ss_mask = info->sseu.subslice_mask[slice];
> +
> +		u8 enabled_mask = (ss_mask | ss_mask >>
> +				   GEN10_L3BANK_PAIR_COUNT) &
> +				   GEN10_L3BANK_MASK;
> +		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
> +
> +		/*
> +		 * Production silicon should have matched L3Bank and
> +		 * subslice enabled
> +		 */
> +		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> +	}
> +
>   	if (INTEL_GEN(dev_priv) >= 11) {
>   		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>   					  GEN11_MCR_SUBSLICE_MASK;

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[PATCH v11 2/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
 - use fls instead of find_last_bit (Chris)
 - use is_power_of_2() instead of counting bit set (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Move local variable into scope where they are used (Ursulin)
 - use a new local variable to reduce long line of code (Ursulin)
v6:
 - Some coding style and use more local variables for clearer
   logic (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar.
v9:
 - Fixed label location. (Oscar)
v10:
 - Improved comments and replaced magical number. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
 drivers/gpu/drm/i915/intel_device_info.c | 34 ++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb10602..6c9c01b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2709,6 +2709,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT		18
 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT     4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d917c9b..44ca90a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -729,6 +729,40 @@ static void sanitize_mcr(struct intel_device_info *info)
 	u32 slice = fls(info->sseu.slice_mask);
 	u32 subslice = fls(info->sseu.subslice_mask[slice]);
 
+	/*
+	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
+	 * L3Banks could be fused off in single slice scenario. If that is
+	 * the case, we might need to program MCR select to a valid L3Bank
+	 * by default, to make sure we correctly read certain registers
+	 * later on (in the range 0xB100 - 0xB3FF).
+	 * This might be incompatible with
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads.
+	 * Fortunately, this should not happen in production hardware, so
+	 * we only assert that this is the case (instead of implementing
+	 * something more complex that requires checking the range of every
+	 * MMIO read).
+	 */
+	if (INTEL_GEN(dev_priv) >= 10 &&
+	    is_power_of_2(info->sseu.slice_mask)) {
+		/*
+		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet
+		 */
+		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+		u8 ss_mask = info->sseu.subslice_mask[slice];
+
+		u8 enabled_mask = (ss_mask | ss_mask >>
+				   GEN10_L3BANK_PAIR_COUNT) &
+				   GEN10_L3BANK_MASK;
+		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
+
+		/*
+		 * Production silicon should have matched L3Bank and
+		 * subslice enabled
+		 */
+		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+	}
+
 	if (INTEL_GEN(dev_priv) >= 11) {
 		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
 					  GEN11_MCR_SUBSLICE_MASK;
-- 
2.7.4

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Re: [PATCH v11 2/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Rodrigo Vivi]

On Mon, Apr 23, 2018 at 09:12:46AM -0700, Yunwei Zhang wrote:
> L3Bank could be fused off in hardware for debug purpose, and it
> is possible that subslice is enabled while its corresponding L3Bank pairs
> are disabled. In such case, if MCR packet control register(0xFDC) is
> programed to point to a disabled bank pair, a MMIO read into L3Bank range
> will return 0 instead of correct values.
> 
> However, this is not going to be the case in any production silicon.
> Therefore, we only check at initialization and issue a warning should
> this really happen.
> 
> References: HSDES#1405586840
> 
> v2:
>  - use fls instead of find_last_bit (Chris)
>  - use is_power_of_2() instead of counting bit set (Chris)
> v3:
>  - rebase on latest tip
> v5:
>  - Added references (Mika)
>  - Move local variable into scope where they are used (Ursulin)
>  - use a new local variable to reduce long line of code (Ursulin)
> v6:
>  - Some coding style and use more local variables for clearer
>    logic (Ursulin)
> v7:
>  - Rebased.
> v8:
>  - Reviewed by Oscar.
> v9:
>  - Fixed label location. (Oscar)
> v10:
>  - Improved comments and replaced magical number. (Oscar)
> 
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

I confess that I got lost on this thread, so please
accept my apologies in advance if I'm missing something here.

But I don't know anymore:

- if this series has 2 or 3 patches.
- which of the patches rv-b by Oscar are still valid
- if they are passing cleaning on CI.

So, my suggestion is to start a new series from scratch.
(resend all without any in-reply-to)

But please double check with Oscar if his rv-b should stay
on the new series.

Thanks,
Rodrigo.


> ---
>  drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>  drivers/gpu/drm/i915/intel_device_info.c | 34 ++++++++++++++++++++++++++++++++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb10602..6c9c01b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2709,6 +2709,10 @@ enum i915_power_well_id {
>  #define   GEN10_F2_SS_DIS_SHIFT		18
>  #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>  
> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT     4
> +#define GEN10_L3BANK_MASK   0x0F
> +
>  #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>  #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>  #define   GEN8_EU_DIS0_S1_SHIFT		24
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d917c9b..44ca90a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -729,6 +729,40 @@ static void sanitize_mcr(struct intel_device_info *info)
>  	u32 slice = fls(info->sseu.slice_mask);
>  	u32 subslice = fls(info->sseu.subslice_mask[slice]);
>  
> +	/*
> +	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> +	 * L3Banks could be fused off in single slice scenario. If that is
> +	 * the case, we might need to program MCR select to a valid L3Bank
> +	 * by default, to make sure we correctly read certain registers
> +	 * later on (in the range 0xB100 - 0xB3FF).
> +	 * This might be incompatible with
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads.
> +	 * Fortunately, this should not happen in production hardware, so
> +	 * we only assert that this is the case (instead of implementing
> +	 * something more complex that requires checking the range of every
> +	 * MMIO read).
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 10 &&
> +	    is_power_of_2(info->sseu.slice_mask)) {
> +		/*
> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +		 * enabled subslice, no need to redirect MCR packet
> +		 */
> +		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> +		u8 ss_mask = info->sseu.subslice_mask[slice];
> +
> +		u8 enabled_mask = (ss_mask | ss_mask >>
> +				   GEN10_L3BANK_PAIR_COUNT) &
> +				   GEN10_L3BANK_MASK;
> +		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
> +
> +		/*
> +		 * Production silicon should have matched L3Bank and
> +		 * subslice enabled
> +		 */
> +		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> +	}
> +
>  	if (INTEL_GEN(dev_priv) >= 11) {
>  		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>  					  GEN11_MCR_SUBSLICE_MASK;
> -- 
> 2.7.4
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v11 2/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Zhang, Yunwei]

Sorry, I added a debug patch when submitting to trybot and forgot to 
remove that from my local branch. I will resubmit to a new series.

Yunwei


On 4/23/2018 12:55 PM, Rodrigo Vivi wrote:
> On Mon, Apr 23, 2018 at 09:12:46AM -0700, Yunwei Zhang wrote:
>> L3Bank could be fused off in hardware for debug purpose, and it
>> is possible that subslice is enabled while its corresponding L3Bank pairs
>> are disabled. In such case, if MCR packet control register(0xFDC) is
>> programed to point to a disabled bank pair, a MMIO read into L3Bank range
>> will return 0 instead of correct values.
>>
>> However, this is not going to be the case in any production silicon.
>> Therefore, we only check at initialization and issue a warning should
>> this really happen.
>>
>> References: HSDES#1405586840
>>
>> v2:
>>   - use fls instead of find_last_bit (Chris)
>>   - use is_power_of_2() instead of counting bit set (Chris)
>> v3:
>>   - rebase on latest tip
>> v5:
>>   - Added references (Mika)
>>   - Move local variable into scope where they are used (Ursulin)
>>   - use a new local variable to reduce long line of code (Ursulin)
>> v6:
>>   - Some coding style and use more local variables for clearer
>>     logic (Ursulin)
>> v7:
>>   - Rebased.
>> v8:
>>   - Reviewed by Oscar.
>> v9:
>>   - Fixed label location. (Oscar)
>> v10:
>>   - Improved comments and replaced magical number. (Oscar)
>>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> I confess that I got lost on this thread, so please
> accept my apologies in advance if I'm missing something here.
>
> But I don't know anymore:
>
> - if this series has 2 or 3 patches.
> - which of the patches rv-b by Oscar are still valid
> - if they are passing cleaning on CI.
>
> So, my suggestion is to start a new series from scratch.
> (resend all without any in-reply-to)
>
> But please double check with Oscar if his rv-b should stay
> on the new series.
>
> Thanks,
> Rodrigo.
>
>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>>   drivers/gpu/drm/i915/intel_device_info.c | 34 ++++++++++++++++++++++++++++++++
>>   2 files changed, 38 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index fb10602..6c9c01b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2709,6 +2709,10 @@ enum i915_power_well_id {
>>   #define   GEN10_F2_SS_DIS_SHIFT		18
>>   #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
>>   
>> +#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
>> +#define GEN10_L3BANK_PAIR_COUNT     4
>> +#define GEN10_L3BANK_MASK   0x0F
>> +
>>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
>>   #define   GEN8_EU_DIS0_S1_SHIFT		24
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index d917c9b..44ca90a 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -729,6 +729,40 @@ static void sanitize_mcr(struct intel_device_info *info)
>>   	u32 slice = fls(info->sseu.slice_mask);
>>   	u32 subslice = fls(info->sseu.subslice_mask[slice]);
>>   
>> +	/*
>> +	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
>> +	 * L3Banks could be fused off in single slice scenario. If that is
>> +	 * the case, we might need to program MCR select to a valid L3Bank
>> +	 * by default, to make sure we correctly read certain registers
>> +	 * later on (in the range 0xB100 - 0xB3FF).
>> +	 * This might be incompatible with
>> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads.
>> +	 * Fortunately, this should not happen in production hardware, so
>> +	 * we only assert that this is the case (instead of implementing
>> +	 * something more complex that requires checking the range of every
>> +	 * MMIO read).
>> +	 */
>> +	if (INTEL_GEN(dev_priv) >= 10 &&
>> +	    is_power_of_2(info->sseu.slice_mask)) {
>> +		/*
>> +		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>> +		 * enabled subslice, no need to redirect MCR packet
>> +		 */
>> +		u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
>> +		u8 ss_mask = info->sseu.subslice_mask[slice];
>> +
>> +		u8 enabled_mask = (ss_mask | ss_mask >>
>> +				   GEN10_L3BANK_PAIR_COUNT) &
>> +				   GEN10_L3BANK_MASK;
>> +		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
>> +
>> +		/*
>> +		 * Production silicon should have matched L3Bank and
>> +		 * subslice enabled
>> +		 */
>> +		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
>> +	}
>> +
>>   	if (INTEL_GEN(dev_priv) >= 11) {
>>   		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>>   					  GEN11_MCR_SUBSLICE_MASK;
>> -- 
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
URL   : https://patchwork.freedesktop.org/series/40503/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5538dcdd0612 drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
9632e3a2f229 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
-:67: CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
#67: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:829:
+			       | sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)
 			                                   ^

total: 0 errors, 0 warnings, 1 checks, 35 lines checked

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✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
URL   : https://patchwork.freedesktop.org/series/40503/
State : warning

== Summary ==

Series 40503v1 series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/1/mbox/

---- Possible new issues:

Test gem_busy:
        Subgroup basic-hang-default:
                pass       -> DMESG-WARN (fi-cnl-drrs)
Test gem_exec_fence:
        Subgroup await-hang-default:
                pass       -> DMESG-WARN (fi-cnl-drrs)
Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-cnl-drrs)
Test gem_ringfill:
        Subgroup basic-default-hang:
                pass       -> DMESG-WARN (fi-cnl-drrs)

---- Known issues:

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> DMESG-WARN (fi-cnl-drrs) fdo#105086
Test kms_frontbuffer_tracking:
        Subgroup basic:
                pass       -> INCOMPLETE (fi-cnl-y3) fdo#103167
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-cnl-drrs) k.org#198519 +2
                pass       -> INCOMPLETE (fi-hsw-4770) fdo#104944

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
k.org#198519 https://bugzilla.kernel.org/show_bug.cgi?id=198519
fdo#104944 https://bugs.freedesktop.org/show_bug.cgi?id=104944

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:433s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:441s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:379s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:533s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:296s
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:514s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:515s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:514s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:505s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:410s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:514s
fi-cnl-drrs      total:285  pass:246  dwarn:11  dfail:0   fail:0   skip:28  time:529s
fi-cnl-y3        total:224  pass:199  dwarn:0   dfail:0   fail:0   skip:24 
fi-elk-e7500     total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  time:426s
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:317s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:538s
fi-hsw-4770      total:241  pass:217  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:418s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:473s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:436s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:473s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:464s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:511s
fi-pnv-d510      total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  time:652s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:438s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:533s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:503s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:496s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:430s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:441s
fi-snb-2520m     total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:587s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:399s
fi-cfl-s3 failed to connect after reboot

40fcdd23bec787a5913496f2b11c5d26bdff985a drm-tip: 2018y-03m-22d-15h-28m-32s UTC integration manifest
9632e3a2f229 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
5538dcdd0612 drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8457/issues.html
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Re: [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Mika Kuoppala]

Hi,

Yunwei Zhang <yunwei.zhang@intel.com> writes:

> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg for INSTDONE.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> v2:
>  - use fls() instead of find_last_bit() (Chris)
>  - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>  - rebase on latest tip
>

Please add the relevant bspec id's and/or hsds
as a references into both patches.

For example see commit 86ebb015fa744dd1e265c9b45ade870ac859a4d5
-Mika

> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h        |  1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
>  2 files changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c9c3b2b..d902c50 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2296,6 +2296,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
>  #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
> +#define INTEL_SSEU(dev_priv)	((dev_priv)->info.sseu)
>  
>  #define REVID_FOREVER		0xff
>  #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index de09fa4..cc19e0a 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>  	}
>  }
>  
> +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
> +{
> +	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
> +	u32 slice = fls(sseu->slice_mask);
> +	u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> +	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> +	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> +
> +	return mcr;
> +}
> +
> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> +{
> +	u32 mcr;
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr = calculate_mcr(mcr, dev_priv);
> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +}
> +
>  static inline uint32_t
>  read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>  		  int subslice, i915_reg_t reg)
> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>  	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>  
>  	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
>  	/*
>  	 * The HW expects the slice and sublice selectors to be reset to 0
>  	 * after reading out the registers.
>  	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +	if (INTEL_GEN(dev_priv) < 10)
> +		WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>  	mcr &= ~mcr_slice_subslice_mask;
>  	mcr |= mcr_slice_subslice_select;
>  	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>  
>  	ret = I915_READ_FW(reg);
>  
> -	mcr &= ~mcr_slice_subslice_mask;
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> +	 * expects mcr to be programed to a enabled slice/subslice pair
> +	 * before any MMIO read into slice/subslice register
> +	 */
> +	if (INTEL_GEN(dev_priv) < 10)
> +		mcr &= ~mcr_slice_subslice_mask;
> +	else
> +		mcr = calculate_mcr(mcr, dev_priv);
> +
>  	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>  
>  	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> @@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	int ret;
>  
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
> +	wa_init_mcr(dev_priv);
> +
>  	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
>  	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
>  		I915_WRITE(GAMT_CHKN_BIT_REG,
> -- 
> 2.7.4
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[PATCH v4 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

Reference: HSD#1405586840 BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v4:
 - Added references (Mika)

Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h        |  1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 800230b..2db2a04 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2297,6 +2297,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
 #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
+#define INTEL_SSEU(dev_priv)	((dev_priv)->info.sseu)
 
 #define REVID_FOREVER		0xff
 #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index de09fa4..cc19e0a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 	}
 }
 
+static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
+{
+	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
+	u32 slice = fls(sseu->slice_mask);
+	u32 subslice = fls(sseu->subslice_mask[slice]);
+
+	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+	return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+	u32 mcr;
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr = calculate_mcr(mcr, dev_priv);
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 		  int subslice, i915_reg_t reg)
@@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
 	/*
 	 * The HW expects the slice and sublice selectors to be reset to 0
 	 * after reading out the registers.
 	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	if (INTEL_GEN(dev_priv) < 10)
+		WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~mcr_slice_subslice_mask;
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+	 * expects mcr to be programed to a enabled slice/subslice pair
+	 * before any MMIO read into slice/subslice register
+	 */
+	if (INTEL_GEN(dev_priv) < 10)
+		mcr &= ~mcr_slice_subslice_mask;
+	else
+		mcr = calculate_mcr(mcr, dev_priv);
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+	wa_init_mcr(dev_priv);
+
 	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
 	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
 		I915_WRITE(GAMT_CHKN_BIT_REG,
-- 
2.7.4

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Re: [PATCH v4 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Tvrtko Ursulin]

On 26/03/2018 17:12, Yunwei Zhang wrote:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
> 
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
> 
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
> 
> Reference: HSD#1405586840 BSID#0575
> 
> v2:
>   - use fls() instead of find_last_bit() (Chris)
>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>   - rebase on latest tip
> v4:
>   - Added references (Mika)
> 
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h        |  1 +
>   drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
>   2 files changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 800230b..2db2a04 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2297,6 +2297,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>   
>   #define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
>   #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
> +#define INTEL_SSEU(dev_priv)	((dev_priv)->info.sseu)

If we add this someone gets the job of converting existing users?

>   
>   #define REVID_FOREVER		0xff
>   #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index de09fa4..cc19e0a 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>   	}
>   }
>   
> +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)

dev_priv first would be more typical function argument order.

> +{
> +	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
> +	u32 slice = fls(sseu->slice_mask);
> +	u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> +	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> +	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> +
> +	return mcr;
> +}
> +
> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> +{
> +	u32 mcr;
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr = calculate_mcr(mcr, dev_priv);
> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +}
> +
>   static inline uint32_t
>   read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   		  int subslice, i915_reg_t reg)
> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>   
>   	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
>   	/*
>   	 * The HW expects the slice and sublice selectors to be reset to 0
>   	 * after reading out the registers.
>   	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +	if (INTEL_GEN(dev_priv) < 10)
> +		WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);

Can squash to single line WARN_ON_ONCE(INTEL_GEN() < 10 && (mcr & ...)), 
if it fits.

>   	mcr &= ~mcr_slice_subslice_mask;
>   	mcr |= mcr_slice_subslice_select;
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	ret = I915_READ_FW(reg);
>   
> -	mcr &= ~mcr_slice_subslice_mask;
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> +	 * expects mcr to be programed to a enabled slice/subslice pair
> +	 * before any MMIO read into slice/subslice register
> +	 */
> +	if (INTEL_GEN(dev_priv) < 10)
> +		mcr &= ~mcr_slice_subslice_mask;
> +	else
> +		mcr = calculate_mcr(mcr, dev_priv);

Does it make sense to move the conditional and comment to calculate_mcr 
- so here only a single call to it remains?

> +
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> @@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>   	struct drm_i915_private *dev_priv = engine->i915;
>   	int ret;
>   
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
> +	wa_init_mcr(dev_priv);
> +
>   	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
>   	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
>   		I915_WRITE(GAMT_CHKN_BIT_REG,
> 

Above are suggestions and questions only.

Regards,

Tvrtko
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Re: [PATCH v4 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-03-26 17:57:38)
> 
> On 26/03/2018 17:12, Yunwei Zhang wrote:
> > ---
> >   drivers/gpu/drm/i915/i915_drv.h        |  1 +
> >   drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
> >   2 files changed, 38 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 800230b..2db2a04 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2297,6 +2297,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >   
> >   #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
> >   #define INTEL_DEVID(dev_priv)       ((dev_priv)->info.device_id)
> > +#define INTEL_SSEU(dev_priv) ((dev_priv)->info.sseu)
> 
> If we add this someone gets the job of converting existing users?

My bad, I hadn't realised that the INTEL_SSEU conversion was local to my
tree. It must have fallen out as part of the static device_info reform.
-Chris
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Re: [PATCH v4 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Zhang, Yunwei]

On 3/26/2018 9:57 AM, Tvrtko Ursulin wrote:
>
> On 26/03/2018 17:12, Yunwei Zhang wrote:
>> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any 
>> MMIO
>> read into Slice/Subslice specific registers, MCR packet control
>> register(0xFDC) needs to be programmed to point to any enabled
>> slice/subslice pair. Otherwise, incorrect value will be returned.
>>
>> However, that means each subsequent MMIO read will be forwarded to a
>> specific slice/subslice combination as read is unicast. This is OK since
>> slice/subslice specific register values are consistent in almost all 
>> cases
>> across slice/subslice. There are rare occasions such as INSTDONE that 
>> this
>> value will be dependent on slice/subslice combo, in such cases, we 
>> need to
>> program 0xFDC and recover this after. This is already covered by
>> read_subslice_reg.
>>
>> Also, 0xFDC will lose its information after TDR/engine reset/power state
>> change.
>>
>> Reference: HSD#1405586840 BSID#0575
>>
>> v2:
>>   - use fls() instead of find_last_bit() (Chris)
>>   - added INTEL_SSEU to extract sseu from device info. (Chris)
>> v3:
>>   - rebase on latest tip
>> v4:
>>   - Added references (Mika)
>>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h        |  1 +
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 39 
>> ++++++++++++++++++++++++++++++++--
>>   2 files changed, 38 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 800230b..2db2a04 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2297,6 +2297,7 @@ intel_info(const struct drm_i915_private 
>> *dev_priv)
>>     #define INTEL_GEN(dev_priv)    ((dev_priv)->info.gen)
>>   #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
>> +#define INTEL_SSEU(dev_priv)    ((dev_priv)->info.sseu)
>
> If we add this someone gets the job of converting existing users?
This is suggestion from Chris Wilson, I am new here, but I guess if I am 
going to do that, it is better in a separate patch. I will remove this 
in next patchset and submit a new patch later.
>>     #define REVID_FOREVER        0xff
>>   #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
>> b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index de09fa4..cc19e0a 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct 
>> drm_i915_private *i915, int type)
>>       }
>>   }
>>   +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
>
> dev_priv first would be more typical function argument order.
>
>> +{
>> +    const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
>> +    u32 slice = fls(sseu->slice_mask);
>> +    u32 subslice = fls(sseu->subslice_mask[slice]);
>> +
>> +    mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
>> +    mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
>> +
>> +    return mcr;
>> +}
>> +
>> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
>> +{
>> +    u32 mcr;
>> +
>> +    mcr = I915_READ(GEN8_MCR_SELECTOR);
>> +    mcr = calculate_mcr(mcr, dev_priv);
>> +    I915_WRITE(GEN8_MCR_SELECTOR, mcr);
>> +}
>> +
>>   static inline uint32_t
>>   read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>             int subslice, i915_reg_t reg)
>> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private 
>> *dev_priv, int slice,
>>       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>>         mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>> +
>>       /*
>>        * The HW expects the slice and sublice selectors to be reset to 0
>>        * after reading out the registers.
>>        */
>> -    WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>> +    if (INTEL_GEN(dev_priv) < 10)
>> +        WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>
> Can squash to single line WARN_ON_ONCE(INTEL_GEN() < 10 && (mcr & 
> ...)), if it fits.
>
>>       mcr &= ~mcr_slice_subslice_mask;
>>       mcr |= mcr_slice_subslice_select;
>>       I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>         ret = I915_READ_FW(reg);
>>   -    mcr &= ~mcr_slice_subslice_mask;
>> +    /*
>> +     * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
>> +     * expects mcr to be programed to a enabled slice/subslice pair
>> +     * before any MMIO read into slice/subslice register
>> +     */
>> +    if (INTEL_GEN(dev_priv) < 10)
>> +        mcr &= ~mcr_slice_subslice_mask;
>> +    else
>> +        mcr = calculate_mcr(mcr, dev_priv);
>
> Does it make sense to move the conditional and comment to 
> calculate_mcr - so here only a single call to it remains?
I am thinking maybe it is better to save jump/return for GENs that don't 
have WA..
>> +
>>       I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
>> @@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct 
>> intel_engine_cs *engine)
>>       struct drm_i915_private *dev_priv = engine->i915;
>>       int ret;
>>   +    /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
>> +    wa_init_mcr(dev_priv);
>> +
>>       /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
>>       if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
>>           I915_WRITE(GAMT_CHKN_BIT_REG,
>>
>
> Above are suggestions and questions only.
>
> Regards,
>
> Tvrtko

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Re: [PATCH v4 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Mika Kuoppala]

Yunwei Zhang <yunwei.zhang@intel.com> writes:

> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> Reference: HSD#1405586840 BSID#0575

Use plural, and add comma in between.

Move 'References' right before Cc:s after the version log...

>
> v2:
>  - use fls() instead of find_last_bit() (Chris)
>  - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>  - rebase on latest tip
> v4:
>  - Added references (Mika)
>

.. in here.

And we usually do put Cc:s before s-o-b.

For example, see commit 465418c6064c88d4af555abe0480c417eb47eae3

Thanks,
-Mika

> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h        |  1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
>  2 files changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 800230b..2db2a04 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2297,6 +2297,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
>  #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
> +#define INTEL_SSEU(dev_priv)	((dev_priv)->info.sseu)
>  
>  #define REVID_FOREVER		0xff
>  #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index de09fa4..cc19e0a 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>  	}
>  }
>  
> +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
> +{
> +	const struct sseu_dev_info *sseu = &(INTEL_SSEU(dev_priv));
> +	u32 slice = fls(sseu->slice_mask);
> +	u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> +	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> +	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> +
> +	return mcr;
> +}
> +
> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> +{
> +	u32 mcr;
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr = calculate_mcr(mcr, dev_priv);
> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +}
> +
>  static inline uint32_t
>  read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>  		  int subslice, i915_reg_t reg)
> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>  	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>  
>  	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
>  	/*
>  	 * The HW expects the slice and sublice selectors to be reset to 0
>  	 * after reading out the registers.
>  	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +	if (INTEL_GEN(dev_priv) < 10)
> +		WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>  	mcr &= ~mcr_slice_subslice_mask;
>  	mcr |= mcr_slice_subslice_select;
>  	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>  
>  	ret = I915_READ_FW(reg);
>  
> -	mcr &= ~mcr_slice_subslice_mask;
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> +	 * expects mcr to be programed to a enabled slice/subslice pair
> +	 * before any MMIO read into slice/subslice register
> +	 */
> +	if (INTEL_GEN(dev_priv) < 10)
> +		mcr &= ~mcr_slice_subslice_mask;
> +	else
> +		mcr = calculate_mcr(mcr, dev_priv);
> +
>  	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>  
>  	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> @@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	int ret;
>  
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
> +	wa_init_mcr(dev_priv);
> +
>  	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
>  	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
>  		I915_WRITE(GAMT_CHKN_BIT_REG,
> -- 
> 2.7.4
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[PATCH v5 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index de09fa4..4c78d1e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 	}
 }
 
+static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
+{
+	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+	u32 slice = fls(sseu->slice_mask);
+	u32 subslice = fls(sseu->subslice_mask[slice]);
+
+	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+	return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+	u32 mcr;
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr = calculate_mcr(dev_priv, mcr);
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 		  int subslice, i915_reg_t reg)
@@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
 	/*
 	 * The HW expects the slice and sublice selectors to be reset to 0
 	 * after reading out the registers.
 	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
+		     (mcr & mcr_slice_subslice_mask));
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~mcr_slice_subslice_mask;
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+	 * expects mcr to be programed to a enabled slice/subslice pair
+	 * before any MMIO read into slice/subslice register
+	 */
+	if (INTEL_GEN(dev_priv) < 10)
+		mcr &= ~mcr_slice_subslice_mask;
+	else
+		mcr = calculate_mcr(dev_priv, mcr);
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1307,6 +1339,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+	wa_init_mcr(dev_priv);
+
 	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
 	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
 		I915_WRITE(GAMT_CHKN_BIT_REG,
-- 
2.7.4

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Re: [PATCH v5 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Chris Wilson]

Quoting Yunwei Zhang (2018-03-27 23:14:16)
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
> 
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
> 
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
> 
> References: HSD#1405586840, BSID#0575
> 
> v2:
>  - use fls() instead of find_last_bit() (Chris)
>  - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>  - rebase on latest tip
> v5:
>  - Added references (Mika)
>  - Change the ordered of passing arguments and etc. (Ursulin)
> 
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
>  1 file changed, 37 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index de09fa4..4c78d1e 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>         }
>  }
>  
> +static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
> +{
> +       const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> +       u32 slice = fls(sseu->slice_mask);
> +       u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> +       mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> +       mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> +
> +       return mcr;
> +}
> +
> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> +{
> +       u32 mcr;
> +
> +       mcr = I915_READ(GEN8_MCR_SELECTOR);
> +       mcr = calculate_mcr(dev_priv, mcr);
> +       I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +}
> +
>  static inline uint32_t
>  read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>                   int subslice, i915_reg_t reg)
> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>         intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>  
>         mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
>         /*
>          * The HW expects the slice and sublice selectors to be reset to 0
>          * after reading out the registers.
>          */
> -       WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +       WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
> +                    (mcr & mcr_slice_subslice_mask));
>         mcr &= ~mcr_slice_subslice_mask;
>         mcr |= mcr_slice_subslice_select;
>         I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>  
>         ret = I915_READ_FW(reg);
>  
> -       mcr &= ~mcr_slice_subslice_mask;
> +       /*
> +        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> +        * expects mcr to be programed to a enabled slice/subslice pair
> +        * before any MMIO read into slice/subslice register
> +        */

So the read was above, where we did set the subslice_select
appropriately. Here we are resetting back to 0 *after* the read, as the
comment before indicates.

So what are you trying to accomplish with this patch? Other than leaving
the code in conflict with itself.
-Chris
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Re: [PATCH v5 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Zhang, Yunwei]

On 3/27/2018 3:27 PM, Chris Wilson wrote:
> Quoting Yunwei Zhang (2018-03-27 23:14:16)
>> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
>> read into Slice/Subslice specific registers, MCR packet control
>> register(0xFDC) needs to be programmed to point to any enabled
>> slice/subslice pair. Otherwise, incorrect value will be returned.
>>
>> However, that means each subsequent MMIO read will be forwarded to a
>> specific slice/subslice combination as read is unicast. This is OK since
>> slice/subslice specific register values are consistent in almost all cases
>> across slice/subslice. There are rare occasions such as INSTDONE that this
>> value will be dependent on slice/subslice combo, in such cases, we need to
>> program 0xFDC and recover this after. This is already covered by
>> read_subslice_reg.
>>
>> Also, 0xFDC will lose its information after TDR/engine reset/power state
>> change.
>>
>> References: HSD#1405586840, BSID#0575
>>
>> v2:
>>   - use fls() instead of find_last_bit() (Chris)
>>   - added INTEL_SSEU to extract sseu from device info. (Chris)
>> v3:
>>   - rebase on latest tip
>> v5:
>>   - Added references (Mika)
>>   - Change the ordered of passing arguments and etc. (Ursulin)
>>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
>>   1 file changed, 37 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index de09fa4..4c78d1e 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>>          }
>>   }
>>   
>> +static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
>> +{
>> +       const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
>> +       u32 slice = fls(sseu->slice_mask);
>> +       u32 subslice = fls(sseu->subslice_mask[slice]);
>> +
>> +       mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
>> +       mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
>> +
>> +       return mcr;
>> +}
>> +
>> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
>> +{
>> +       u32 mcr;
>> +
>> +       mcr = I915_READ(GEN8_MCR_SELECTOR);
>> +       mcr = calculate_mcr(dev_priv, mcr);
>> +       I915_WRITE(GEN8_MCR_SELECTOR, mcr);
>> +}
>> +
>>   static inline uint32_t
>>   read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>                    int subslice, i915_reg_t reg)
>> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>          intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>>   
>>          mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>> +
>>          /*
>>           * The HW expects the slice and sublice selectors to be reset to 0
>>           * after reading out the registers.
>>           */
>> -       WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>> +       WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
>> +                    (mcr & mcr_slice_subslice_mask));
>>          mcr &= ~mcr_slice_subslice_mask;
>>          mcr |= mcr_slice_subslice_select;
>>          I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>   
>>          ret = I915_READ_FW(reg);
>>   
>> -       mcr &= ~mcr_slice_subslice_mask;
>> +       /*
>> +        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
>> +        * expects mcr to be programed to a enabled slice/subslice pair
>> +        * before any MMIO read into slice/subslice register
>> +        */
> So the read was above, where we did set the subslice_select
> appropriately. Here we are resetting back to 0 *after* the read, as the
> comment before indicates.
>
> So what are you trying to accomplish with this patch? Other than leaving
> the code in conflict with itself.
> -Chris
Hi Chris,

The comment mentioned 0xFDC needs to be reset to 0 was before this WA 
was introduced, in later HW, this WA requires 0xFDC to be programmed to 
a enabled slice/subslice.

What this patch does it to initialize 0xFDC once at the initialization 
(also it will be called after engine reset/TDR/coming out of c6) and 
make sure every time it is changed, it will be reprogrammed to a enabled 
slice/subslice so that a MMIO
read will get the correct value. read_subslice_reg changes the 0xFDC 
value and if it is set to 0, it will cause MMIO read to return invalid 
value for s/ss specific registers.
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Re: [PATCH v5 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Chris Wilson]

Quoting Zhang, Yunwei (2018-03-27 23:49:27)
> 
> 
> On 3/27/2018 3:27 PM, Chris Wilson wrote:
> > Quoting Yunwei Zhang (2018-03-27 23:14:16)
> >> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> >> read into Slice/Subslice specific registers, MCR packet control
> >> register(0xFDC) needs to be programmed to point to any enabled
> >> slice/subslice pair. Otherwise, incorrect value will be returned.
> >>
> >> However, that means each subsequent MMIO read will be forwarded to a
> >> specific slice/subslice combination as read is unicast. This is OK since
> >> slice/subslice specific register values are consistent in almost all cases
> >> across slice/subslice. There are rare occasions such as INSTDONE that this
> >> value will be dependent on slice/subslice combo, in such cases, we need to
> >> program 0xFDC and recover this after. This is already covered by
> >> read_subslice_reg.
> >>
> >> Also, 0xFDC will lose its information after TDR/engine reset/power state
> >> change.
> >>
> >> References: HSD#1405586840, BSID#0575
> >>
> >> v2:
> >>   - use fls() instead of find_last_bit() (Chris)
> >>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> >> v3:
> >>   - rebase on latest tip
> >> v5:
> >>   - Added references (Mika)
> >>   - Change the ordered of passing arguments and etc. (Ursulin)
> >>
> >> Cc: Oscar Mateo <oscar.mateo@intel.com>
> >> Cc: Michel Thierry <michel.thierry@intel.com>
> >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> >> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
> >>   1 file changed, 37 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> >> index de09fa4..4c78d1e 100644
> >> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> >> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> >> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
> >>          }
> >>   }
> >>   
> >> +static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
> >> +{
> >> +       const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> >> +       u32 slice = fls(sseu->slice_mask);
> >> +       u32 subslice = fls(sseu->subslice_mask[slice]);
> >> +
> >> +       mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> >> +       mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> >> +
> >> +       return mcr;
> >> +}
> >> +
> >> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> >> +{
> >> +       u32 mcr;
> >> +
> >> +       mcr = I915_READ(GEN8_MCR_SELECTOR);
> >> +       mcr = calculate_mcr(dev_priv, mcr);
> >> +       I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> >> +}
> >> +
> >>   static inline uint32_t
> >>   read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> >>                    int subslice, i915_reg_t reg)
> >> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> >>          intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> >>   
> >>          mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> >> +
> >>          /*
> >>           * The HW expects the slice and sublice selectors to be reset to 0
> >>           * after reading out the registers.
> >>           */
> >> -       WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> >> +       WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
> >> +                    (mcr & mcr_slice_subslice_mask));
> >>          mcr &= ~mcr_slice_subslice_mask;
> >>          mcr |= mcr_slice_subslice_select;
> >>          I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
> >>   
> >>          ret = I915_READ_FW(reg);
> >>   
> >> -       mcr &= ~mcr_slice_subslice_mask;
> >> +       /*
> >> +        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> >> +        * expects mcr to be programed to a enabled slice/subslice pair
> >> +        * before any MMIO read into slice/subslice register
> >> +        */
> > So the read was above, where we did set the subslice_select
> > appropriately. Here we are resetting back to 0 *after* the read, as the
> > comment before indicates.
> >
> > So what are you trying to accomplish with this patch? Other than leaving
> > the code in conflict with itself.
> > -Chris
> Hi Chris,
> 
> The comment mentioned 0xFDC needs to be reset to 0 was before this WA 
> was introduced, in later HW, this WA requires 0xFDC to be programmed to 
> a enabled slice/subslice.
> 
> What this patch does it to initialize 0xFDC once at the initialization 
> (also it will be called after engine reset/TDR/coming out of c6) and 
> make sure every time it is changed, it will be reprogrammed to a enabled 
> slice/subslice so that a MMIO
> read will get the correct value. read_subslice_reg changes the 0xFDC 
> value and if it is set to 0, it will cause MMIO read to return invalid 
> value for s/ss specific registers.

What mmio read? The only accessor should be this function.

And still the two comments are in direct conflict with each other.
-Chris
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Re: [PATCH v5 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Zhang, Yunwei]

On 3/27/2018 4:13 PM, Chris Wilson wrote:
> Quoting Zhang, Yunwei (2018-03-27 23:49:27)
>>
>> On 3/27/2018 3:27 PM, Chris Wilson wrote:
>>> Quoting Yunwei Zhang (2018-03-27 23:14:16)
>>>> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
>>>> read into Slice/Subslice specific registers, MCR packet control
>>>> register(0xFDC) needs to be programmed to point to any enabled
>>>> slice/subslice pair. Otherwise, incorrect value will be returned.
>>>>
>>>> However, that means each subsequent MMIO read will be forwarded to a
>>>> specific slice/subslice combination as read is unicast. This is OK since
>>>> slice/subslice specific register values are consistent in almost all cases
>>>> across slice/subslice. There are rare occasions such as INSTDONE that this
>>>> value will be dependent on slice/subslice combo, in such cases, we need to
>>>> program 0xFDC and recover this after. This is already covered by
>>>> read_subslice_reg.
>>>>
>>>> Also, 0xFDC will lose its information after TDR/engine reset/power state
>>>> change.
>>>>
>>>> References: HSD#1405586840, BSID#0575
>>>>
>>>> v2:
>>>>    - use fls() instead of find_last_bit() (Chris)
>>>>    - added INTEL_SSEU to extract sseu from device info. (Chris)
>>>> v3:
>>>>    - rebase on latest tip
>>>> v5:
>>>>    - Added references (Mika)
>>>>    - Change the ordered of passing arguments and etc. (Ursulin)
>>>>
>>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>>> Cc: Michel Thierry <michel.thierry@intel.com>
>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
>>>>    1 file changed, 37 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> index de09fa4..4c78d1e 100644
>>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>>>>           }
>>>>    }
>>>>    
>>>> +static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
>>>> +{
>>>> +       const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
>>>> +       u32 slice = fls(sseu->slice_mask);
>>>> +       u32 subslice = fls(sseu->subslice_mask[slice]);
>>>> +
>>>> +       mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
>>>> +       mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
>>>> +
>>>> +       return mcr;
>>>> +}
>>>> +
>>>> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
>>>> +{
>>>> +       u32 mcr;
>>>> +
>>>> +       mcr = I915_READ(GEN8_MCR_SELECTOR);
>>>> +       mcr = calculate_mcr(dev_priv, mcr);
>>>> +       I915_WRITE(GEN8_MCR_SELECTOR, mcr);
>>>> +}
>>>> +
>>>>    static inline uint32_t
>>>>    read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>>>                     int subslice, i915_reg_t reg)
>>>> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>>>           intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>>>>    
>>>>           mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>>>> +
>>>>           /*
>>>>            * The HW expects the slice and sublice selectors to be reset to 0
>>>>            * after reading out the registers.
>>>>            */
>>>> -       WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>>>> +       WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
>>>> +                    (mcr & mcr_slice_subslice_mask));
>>>>           mcr &= ~mcr_slice_subslice_mask;
>>>>           mcr |= mcr_slice_subslice_select;
>>>>           I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>>>    
>>>>           ret = I915_READ_FW(reg);
>>>>    
>>>> -       mcr &= ~mcr_slice_subslice_mask;
>>>> +       /*
>>>> +        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
>>>> +        * expects mcr to be programed to a enabled slice/subslice pair
>>>> +        * before any MMIO read into slice/subslice register
>>>> +        */
>>> So the read was above, where we did set the subslice_select
>>> appropriately. Here we are resetting back to 0 *after* the read, as the
>>> comment before indicates.
>>>
>>> So what are you trying to accomplish with this patch? Other than leaving
>>> the code in conflict with itself.
>>> -Chris
>> Hi Chris,
>>
>> The comment mentioned 0xFDC needs to be reset to 0 was before this WA
>> was introduced, in later HW, this WA requires 0xFDC to be programmed to
>> a enabled slice/subslice.
>>
>> What this patch does it to initialize 0xFDC once at the initialization
>> (also it will be called after engine reset/TDR/coming out of c6) and
>> make sure every time it is changed, it will be reprogrammed to a enabled
>> slice/subslice so that a MMIO
>> read will get the correct value. read_subslice_reg changes the 0xFDC
>> value and if it is set to 0, it will cause MMIO read to return invalid
>> value for s/ss specific registers.
> What mmio read? The only accessor should be this function.
>
> And still the two comments are in direct conflict with each other.
> -Chris
This function is only used in INST_DONE case which you need to iterate 
through each slice/subslice to check and makes sense to program MCR for 
each s/ss combination. But there could be inadvertent read into this 
range without using this function, the value would be wrong without this 
WA.

Anyway, the comment is not right given the latest WA required, I will 
submit a new patchset to update this comment.

Thanks,
Yunwei
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Re: [PATCH v5 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Chris Wilson]

Quoting Zhang, Yunwei (2018-03-28 16:54:26)
> 
> 
> On 3/27/2018 4:13 PM, Chris Wilson wrote:
> > Quoting Zhang, Yunwei (2018-03-27 23:49:27)
> >>
> >> On 3/27/2018 3:27 PM, Chris Wilson wrote:
> >>> Quoting Yunwei Zhang (2018-03-27 23:14:16)
> >>>> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> >>>> read into Slice/Subslice specific registers, MCR packet control
> >>>> register(0xFDC) needs to be programmed to point to any enabled
> >>>> slice/subslice pair. Otherwise, incorrect value will be returned.
> >>>>
> >>>> However, that means each subsequent MMIO read will be forwarded to a
> >>>> specific slice/subslice combination as read is unicast. This is OK since
> >>>> slice/subslice specific register values are consistent in almost all cases
> >>>> across slice/subslice. There are rare occasions such as INSTDONE that this
> >>>> value will be dependent on slice/subslice combo, in such cases, we need to
> >>>> program 0xFDC and recover this after. This is already covered by
> >>>> read_subslice_reg.
> >>>>
> >>>> Also, 0xFDC will lose its information after TDR/engine reset/power state
> >>>> change.
> >>>>
> >>>> References: HSD#1405586840, BSID#0575
> >>>>
> >>>> v2:
> >>>>    - use fls() instead of find_last_bit() (Chris)
> >>>>    - added INTEL_SSEU to extract sseu from device info. (Chris)
> >>>> v3:
> >>>>    - rebase on latest tip
> >>>> v5:
> >>>>    - Added references (Mika)
> >>>>    - Change the ordered of passing arguments and etc. (Ursulin)
> >>>>
> >>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
> >>>> Cc: Michel Thierry <michel.thierry@intel.com>
> >>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> >>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> >>>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> >>>> ---
> >>>>    drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
> >>>>    1 file changed, 37 insertions(+), 2 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>>> index de09fa4..4c78d1e 100644
> >>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> >>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>>> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
> >>>>           }
> >>>>    }
> >>>>    
> >>>> +static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
> >>>> +{
> >>>> +       const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> >>>> +       u32 slice = fls(sseu->slice_mask);
> >>>> +       u32 subslice = fls(sseu->subslice_mask[slice]);
> >>>> +
> >>>> +       mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> >>>> +       mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> >>>> +
> >>>> +       return mcr;
> >>>> +}
> >>>> +
> >>>> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> >>>> +{
> >>>> +       u32 mcr;
> >>>> +
> >>>> +       mcr = I915_READ(GEN8_MCR_SELECTOR);
> >>>> +       mcr = calculate_mcr(dev_priv, mcr);
> >>>> +       I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> >>>> +}
> >>>> +
> >>>>    static inline uint32_t
> >>>>    read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> >>>>                     int subslice, i915_reg_t reg)
> >>>> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> >>>>           intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> >>>>    
> >>>>           mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> >>>> +
> >>>>           /*
> >>>>            * The HW expects the slice and sublice selectors to be reset to 0
> >>>>            * after reading out the registers.
> >>>>            */
> >>>> -       WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> >>>> +       WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
> >>>> +                    (mcr & mcr_slice_subslice_mask));
> >>>>           mcr &= ~mcr_slice_subslice_mask;
> >>>>           mcr |= mcr_slice_subslice_select;
> >>>>           I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
> >>>>    
> >>>>           ret = I915_READ_FW(reg);
> >>>>    
> >>>> -       mcr &= ~mcr_slice_subslice_mask;
> >>>> +       /*
> >>>> +        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> >>>> +        * expects mcr to be programed to a enabled slice/subslice pair
> >>>> +        * before any MMIO read into slice/subslice register
> >>>> +        */
> >>> So the read was above, where we did set the subslice_select
> >>> appropriately. Here we are resetting back to 0 *after* the read, as the
> >>> comment before indicates.
> >>>
> >>> So what are you trying to accomplish with this patch? Other than leaving
> >>> the code in conflict with itself.
> >>> -Chris
> >> Hi Chris,
> >>
> >> The comment mentioned 0xFDC needs to be reset to 0 was before this WA
> >> was introduced, in later HW, this WA requires 0xFDC to be programmed to
> >> a enabled slice/subslice.
> >>
> >> What this patch does it to initialize 0xFDC once at the initialization
> >> (also it will be called after engine reset/TDR/coming out of c6) and
> >> make sure every time it is changed, it will be reprogrammed to a enabled
> >> slice/subslice so that a MMIO
> >> read will get the correct value. read_subslice_reg changes the 0xFDC
> >> value and if it is set to 0, it will cause MMIO read to return invalid
> >> value for s/ss specific registers.
> > What mmio read? The only accessor should be this function.
> >
> > And still the two comments are in direct conflict with each other.
> > -Chris
> This function is only used in INST_DONE case which you need to iterate 
> through each slice/subslice to check and makes sense to program MCR for 
> each s/ss combination. But there could be inadvertent read into this 
> range without using this function, the value would be wrong without this 
> WA.

Sure, but garbage in, garbage out. If we write an accessor for a
register because it requires a workaround, anyone who wants to access
the register should use the accessor. Not just leave HW in a random
state so that one particular selector works.
-Chris
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Re: [PATCH v5 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Zhang, Yunwei]

On 3/28/2018 9:03 AM, Chris Wilson wrote:
> Quoting Zhang, Yunwei (2018-03-28 16:54:26)
>>
>> On 3/27/2018 4:13 PM, Chris Wilson wrote:
>>> Quoting Zhang, Yunwei (2018-03-27 23:49:27)
>>>> On 3/27/2018 3:27 PM, Chris Wilson wrote:
>>>>> Quoting Yunwei Zhang (2018-03-27 23:14:16)
>>>>>> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
>>>>>> read into Slice/Subslice specific registers, MCR packet control
>>>>>> register(0xFDC) needs to be programmed to point to any enabled
>>>>>> slice/subslice pair. Otherwise, incorrect value will be returned.
>>>>>>
>>>>>> However, that means each subsequent MMIO read will be forwarded to a
>>>>>> specific slice/subslice combination as read is unicast. This is OK since
>>>>>> slice/subslice specific register values are consistent in almost all cases
>>>>>> across slice/subslice. There are rare occasions such as INSTDONE that this
>>>>>> value will be dependent on slice/subslice combo, in such cases, we need to
>>>>>> program 0xFDC and recover this after. This is already covered by
>>>>>> read_subslice_reg.
>>>>>>
>>>>>> Also, 0xFDC will lose its information after TDR/engine reset/power state
>>>>>> change.
>>>>>>
>>>>>> References: HSD#1405586840, BSID#0575
>>>>>>
>>>>>> v2:
>>>>>>     - use fls() instead of find_last_bit() (Chris)
>>>>>>     - added INTEL_SSEU to extract sseu from device info. (Chris)
>>>>>> v3:
>>>>>>     - rebase on latest tip
>>>>>> v5:
>>>>>>     - Added references (Mika)
>>>>>>     - Change the ordered of passing arguments and etc. (Ursulin)
>>>>>>
>>>>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>>>>> Cc: Michel Thierry <michel.thierry@intel.com>
>>>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>>>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>>>>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>>>>>> ---
>>>>>>     drivers/gpu/drm/i915/intel_engine_cs.c | 39 ++++++++++++++++++++++++++++++++--
>>>>>>     1 file changed, 37 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>>>> index de09fa4..4c78d1e 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>>>>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>>>> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>>>>>>            }
>>>>>>     }
>>>>>>     
>>>>>> +static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
>>>>>> +{
>>>>>> +       const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
>>>>>> +       u32 slice = fls(sseu->slice_mask);
>>>>>> +       u32 subslice = fls(sseu->subslice_mask[slice]);
>>>>>> +
>>>>>> +       mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
>>>>>> +       mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
>>>>>> +
>>>>>> +       return mcr;
>>>>>> +}
>>>>>> +
>>>>>> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
>>>>>> +{
>>>>>> +       u32 mcr;
>>>>>> +
>>>>>> +       mcr = I915_READ(GEN8_MCR_SELECTOR);
>>>>>> +       mcr = calculate_mcr(dev_priv, mcr);
>>>>>> +       I915_WRITE(GEN8_MCR_SELECTOR, mcr);
>>>>>> +}
>>>>>> +
>>>>>>     static inline uint32_t
>>>>>>     read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>>>>>                      int subslice, i915_reg_t reg)
>>>>>> @@ -828,18 +849,29 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>>>>>            intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>>>>>>     
>>>>>>            mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>>>>>> +
>>>>>>            /*
>>>>>>             * The HW expects the slice and sublice selectors to be reset to 0
>>>>>>             * after reading out the registers.
>>>>>>             */
>>>>>> -       WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>>>>>> +       WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
>>>>>> +                    (mcr & mcr_slice_subslice_mask));
>>>>>>            mcr &= ~mcr_slice_subslice_mask;
>>>>>>            mcr |= mcr_slice_subslice_select;
>>>>>>            I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>>>>>     
>>>>>>            ret = I915_READ_FW(reg);
>>>>>>     
>>>>>> -       mcr &= ~mcr_slice_subslice_mask;
>>>>>> +       /*
>>>>>> +        * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
>>>>>> +        * expects mcr to be programed to a enabled slice/subslice pair
>>>>>> +        * before any MMIO read into slice/subslice register
>>>>>> +        */
>>>>> So the read was above, where we did set the subslice_select
>>>>> appropriately. Here we are resetting back to 0 *after* the read, as the
>>>>> comment before indicates.
>>>>>
>>>>> So what are you trying to accomplish with this patch? Other than leaving
>>>>> the code in conflict with itself.
>>>>> -Chris
>>>> Hi Chris,
>>>>
>>>> The comment mentioned 0xFDC needs to be reset to 0 was before this WA
>>>> was introduced, in later HW, this WA requires 0xFDC to be programmed to
>>>> a enabled slice/subslice.
>>>>
>>>> What this patch does it to initialize 0xFDC once at the initialization
>>>> (also it will be called after engine reset/TDR/coming out of c6) and
>>>> make sure every time it is changed, it will be reprogrammed to a enabled
>>>> slice/subslice so that a MMIO
>>>> read will get the correct value. read_subslice_reg changes the 0xFDC
>>>> value and if it is set to 0, it will cause MMIO read to return invalid
>>>> value for s/ss specific registers.
>>> What mmio read? The only accessor should be this function.
>>>
>>> And still the two comments are in direct conflict with each other.
>>> -Chris
>> This function is only used in INST_DONE case which you need to iterate
>> through each slice/subslice to check and makes sense to program MCR for
>> each s/ss combination. But there could be inadvertent read into this
>> range without using this function, the value would be wrong without this
>> WA.
> Sure, but garbage in, garbage out. If we write an accessor for a
> register because it requires a workaround, anyone who wants to access
> the register should use the accessor. Not just leave HW in a random
> state so that one particular selector works.
> -Chris
But keep in mind this is not only *a* register, it is a range of 
registers, if we don't use this WA, developer needs to reminded if there 
is a MMIO read in slice/subslice/l3bank range, they will need to use 
read_subslice_reg instead of i915_READ.

To me, it is just safe to program MCR in the beginning and reprogram it 
every time we have to change like in INST_DONE case.

Thanks,
Yunwei
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[PATCH v6 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v6:
 - Updated the comment that conflict with the patch. (Chris)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++++++++++++++++++++++++++++++---
 1 file changed, 39 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8..4c50bee 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 	}
 }
 
+static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
+{
+	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+	u32 slice = fls(sseu->slice_mask);
+	u32 subslice = fls(sseu->subslice_mask[slice]);
+
+	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+	return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+	u32 mcr;
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr = calculate_mcr(dev_priv, mcr);
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 		  int subslice, i915_reg_t reg)
@@ -828,18 +849,30 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
 	/*
 	 * The HW expects the slice and sublice selectors to be reset to 0
-	 * after reading out the registers.
+	 * before GEN10 or to a enabled s/ss post GEN10 after reading out the
+	 * registers.
 	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
+		     (mcr & mcr_slice_subslice_mask));
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~mcr_slice_subslice_mask;
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+	 * expects mcr to be programed to a enabled slice/subslice pair
+	 * before any MMIO read into slice/subslice register
+	 */
+	if (INTEL_GEN(dev_priv) < 10)
+		mcr &= ~mcr_slice_subslice_mask;
+	else
+		mcr = calculate_mcr(dev_priv, mcr);
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1307,6 +1340,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+	wa_init_mcr(dev_priv);
+
 	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
 	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
 		I915_WRITE(GAMT_CHKN_BIT_REG,
-- 
2.7.4

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Re: [PATCH v6 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Zhang, Yunwei]

Hi All,

I see the latest BAT test failed but the only thing I changed in this 
new patchset is comment. It should be false alarm, not sure if this is 
halting the further review. Please see if the code needs more change.

Thanks,

Yunwei


On 3/29/2018 8:44 AM, Yunwei Zhang wrote:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> References: HSD#1405586840, BSID#0575
>
> v2:
>   - use fls() instead of find_last_bit() (Chris)
>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Change the ordered of passing arguments and etc. (Ursulin)
> v6:
>   - Updated the comment that conflict with the patch. (Chris)
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++++++++++++++++++++++++++++++---
>   1 file changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 12486d8..4c50bee 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -796,6 +796,27 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>   	}
>   }
>   
> +static u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
> +{
> +	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> +	u32 slice = fls(sseu->slice_mask);
> +	u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> +	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> +	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> +
> +	return mcr;
> +}
> +
> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> +{
> +	u32 mcr;
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr = calculate_mcr(dev_priv, mcr);
> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +}
> +
>   static inline uint32_t
>   read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   		  int subslice, i915_reg_t reg)
> @@ -828,18 +849,30 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>   
>   	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
>   	/*
>   	 * The HW expects the slice and sublice selectors to be reset to 0
> -	 * after reading out the registers.
> +	 * before GEN10 or to a enabled s/ss post GEN10 after reading out the
> +	 * registers.
>   	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +	WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
> +		     (mcr & mcr_slice_subslice_mask));
>   	mcr &= ~mcr_slice_subslice_mask;
>   	mcr |= mcr_slice_subslice_select;
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	ret = I915_READ_FW(reg);
>   
> -	mcr &= ~mcr_slice_subslice_mask;
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> +	 * expects mcr to be programed to a enabled slice/subslice pair
> +	 * before any MMIO read into slice/subslice register
> +	 */
> +	if (INTEL_GEN(dev_priv) < 10)
> +		mcr &= ~mcr_slice_subslice_mask;
> +	else
> +		mcr = calculate_mcr(dev_priv, mcr);
> +
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> @@ -1307,6 +1340,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>   	struct drm_i915_private *dev_priv = engine->i915;
>   	int ret;
>   
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
> +	wa_init_mcr(dev_priv);
> +
>   	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
>   	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
>   		I915_WRITE(GAMT_CHKN_BIT_REG,

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[PATCH v7 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v7:
 - Rebased.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/intel_engine_cs.c   | 30 +++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_workarounds.c | 12 ++++++++++++
 3 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e8667d..43498a47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2725,6 +2725,8 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
 int intel_engines_init(struct drm_i915_private *dev_priv);
 
+u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr);
+
 /* intel_hotplug.c */
 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
 			   u32 pin_mask, u32 long_mask);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a83707..3b6bc5e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -799,6 +799,18 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 	}
 }
 
+u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
+{
+	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+	u32 slice = fls(sseu->slice_mask);
+	u32 subslice = fls(sseu->subslice_mask[slice]);
+
+	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+	return mcr;
+}
+
 static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 		  int subslice, i915_reg_t reg)
@@ -831,18 +843,30 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
 	/*
 	 * The HW expects the slice and sublice selectors to be reset to 0
-	 * after reading out the registers.
+	 * before GEN10 or to a enabled s/ss post GEN10 after reading out the
+	 * registers.
 	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
+		     (mcr & mcr_slice_subslice_mask));
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~mcr_slice_subslice_mask;
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+	 * expects mcr to be programed to a enabled slice/subslice pair
+	 * before any MMIO read into slice/subslice register
+	 */
+	if (INTEL_GEN(dev_priv) < 10)
+		mcr &= ~mcr_slice_subslice_mask;
+	else
+		mcr = calculate_mcr(dev_priv, mcr);
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340..8a2354e 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -645,8 +645,20 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 }
 
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+	u32 mcr;
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr = calculate_mcr(dev_priv, mcr);
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+	wa_init_mcr(dev_priv);
+
 	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
 	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
 		I915_WRITE(GAMT_CHKN_BIT_REG,
-- 
2.7.4

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Re: [PATCH v7 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 04/16/2018 02:22 PM, Yunwei Zhang wrote:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> References: HSD#1405586840, BSID#0575
>
> v2:
>   - use fls() instead of find_last_bit() (Chris)
>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Change the ordered of passing arguments and etc. (Ursulin)
> v7:
>   - Rebased.
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h          |  2 ++
>   drivers/gpu/drm/i915/intel_engine_cs.c   | 30 +++++++++++++++++++++++++++---
>   drivers/gpu/drm/i915/intel_workarounds.c | 12 ++++++++++++
>   3 files changed, 41 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8e8667d..43498a47 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2725,6 +2725,8 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
>   int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
>   int intel_engines_init(struct drm_i915_private *dev_priv);
>   
> +u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr);
> +

As a global function, this could use a better prefix (intel_something_)

Or, alternatively, make it local and store the calculation somewhere.

>   /* intel_hotplug.c */
>   void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
>   			   u32 pin_mask, u32 long_mask);
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 1a83707..3b6bc5e 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -799,6 +799,18 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>   	}
>   }
>   
> +u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
> +{
> +	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
> +	u32 slice = fls(sseu->slice_mask);
> +	u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> +	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> +	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> +
> +	return mcr;
> +}
> +
>   static inline uint32_t
>   read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   		  int subslice, i915_reg_t reg)
> @@ -831,18 +843,30 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>   
>   	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
>   	/*
>   	 * The HW expects the slice and sublice selectors to be reset to 0
> -	 * after reading out the registers.
> +	 * before GEN10 or to a enabled s/ss post GEN10 after reading out the
> +	 * registers.
>   	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +	WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
> +		     (mcr & mcr_slice_subslice_mask));

Advantage of storing the calculation: you can assert here for the 
expected value, independently of the platform.

>   	mcr &= ~mcr_slice_subslice_mask;
>   	mcr |= mcr_slice_subslice_select;
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	ret = I915_READ_FW(reg);
>   
> -	mcr &= ~mcr_slice_subslice_mask;
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
> +	 * expects mcr to be programed to a enabled slice/subslice pair
> +	 * before any MMIO read into slice/subslice register
> +	 */
> +	if (INTEL_GEN(dev_priv) < 10)
> +		mcr &= ~mcr_slice_subslice_mask;
> +	else
> +		mcr = calculate_mcr(dev_priv, mcr);

Another advantage: no branching here either.

> +
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ec9d340..8a2354e 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -645,8 +645,20 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
>   }
>   
> +static void wa_init_mcr(struct drm_i915_private *dev_priv)
> +{
> +	u32 mcr;
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr = calculate_mcr(dev_priv, mcr);
> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +}
> +
>   static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   {
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
> +	wa_init_mcr(dev_priv);
> +
>   	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
>   	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
>   		I915_WRITE(GAMT_CHKN_BIT_REG,

With one of the two above (appropriate prefix or store value), this is:

Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

And as a side note: this is also needed for Icelake.
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Re: [PATCH v7 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Zhang, Yunwei]

On 4/16/2018 3:09 PM, Oscar Mateo wrote:
>
>
> On 04/16/2018 02:22 PM, Yunwei Zhang wrote:
>> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any 
>> MMIO
>> read into Slice/Subslice specific registers, MCR packet control
>> register(0xFDC) needs to be programmed to point to any enabled
>> slice/subslice pair. Otherwise, incorrect value will be returned.
>>
>> However, that means each subsequent MMIO read will be forwarded to a
>> specific slice/subslice combination as read is unicast. This is OK since
>> slice/subslice specific register values are consistent in almost all 
>> cases
>> across slice/subslice. There are rare occasions such as INSTDONE that 
>> this
>> value will be dependent on slice/subslice combo, in such cases, we 
>> need to
>> program 0xFDC and recover this after. This is already covered by
>> read_subslice_reg.
>>
>> Also, 0xFDC will lose its information after TDR/engine reset/power state
>> change.
>>
>> References: HSD#1405586840, BSID#0575
>>
>> v2:
>>   - use fls() instead of find_last_bit() (Chris)
>>   - added INTEL_SSEU to extract sseu from device info. (Chris)
>> v3:
>>   - rebase on latest tip
>> v5:
>>   - Added references (Mika)
>>   - Change the ordered of passing arguments and etc. (Ursulin)
>> v7:
>>   - Rebased.
>>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h          |  2 ++
>>   drivers/gpu/drm/i915/intel_engine_cs.c   | 30 
>> +++++++++++++++++++++++++++---
>>   drivers/gpu/drm/i915/intel_workarounds.c | 12 ++++++++++++
>>   3 files changed, 41 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 8e8667d..43498a47 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2725,6 +2725,8 @@ int vlv_force_gfx_clock(struct drm_i915_private 
>> *dev_priv, bool on);
>>   int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
>>   int intel_engines_init(struct drm_i915_private *dev_priv);
>>   +u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr);
>> +
>
> As a global function, this could use a better prefix (intel_something_)
>
> Or, alternatively, make it local and store the calculation somewhere.
Good suggestion, do you think intel_device_info will be a good place to 
store, it is deduced from that structure after all? Or should I put it 
in drm_i915_private?
>
>>   /* intel_hotplug.c */
>>   void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
>>                  u32 pin_mask, u32 long_mask);
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
>> b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 1a83707..3b6bc5e 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -799,6 +799,18 @@ const char *i915_cache_level_str(struct 
>> drm_i915_private *i915, int type)
>>       }
>>   }
>>   +u32 calculate_mcr(struct drm_i915_private *dev_priv, u32 mcr)
>> +{
>> +    const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
>> +    u32 slice = fls(sseu->slice_mask);
>> +    u32 subslice = fls(sseu->subslice_mask[slice]);
>> +
>> +    mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
>> +    mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
>> +
>> +    return mcr;
>> +}
>> +
>>   static inline uint32_t
>>   read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>>             int subslice, i915_reg_t reg)
>> @@ -831,18 +843,30 @@ read_subslice_reg(struct drm_i915_private 
>> *dev_priv, int slice,
>>       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>>         mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>> +
>>       /*
>>        * The HW expects the slice and sublice selectors to be reset to 0
>> -     * after reading out the registers.
>> +     * before GEN10 or to a enabled s/ss post GEN10 after reading 
>> out the
>> +     * registers.
>>        */
>> -    WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>> +    WARN_ON_ONCE(INTEL_GEN(dev_priv) < 10 &&
>> +             (mcr & mcr_slice_subslice_mask));
>
> Advantage of storing the calculation: you can assert here for the 
> expected value, independently of the platform.
>
>>       mcr &= ~mcr_slice_subslice_mask;
>>       mcr |= mcr_slice_subslice_select;
>>       I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>         ret = I915_READ_FW(reg);
>>   -    mcr &= ~mcr_slice_subslice_mask;
>> +    /*
>> +     * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
>> +     * expects mcr to be programed to a enabled slice/subslice pair
>> +     * before any MMIO read into slice/subslice register
>> +     */
>> +    if (INTEL_GEN(dev_priv) < 10)
>> +        mcr &= ~mcr_slice_subslice_mask;
>> +    else
>> +        mcr = calculate_mcr(dev_priv, mcr);
>
> Another advantage: no branching here either.
>
>> +
>>       I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
>> b/drivers/gpu/drm/i915/intel_workarounds.c
>> index ec9d340..8a2354e 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -645,8 +645,20 @@ static void cfl_gt_workarounds_apply(struct 
>> drm_i915_private *dev_priv)
>>              GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
>>   }
>>   +static void wa_init_mcr(struct drm_i915_private *dev_priv)
>> +{
>> +    u32 mcr;
>> +
>> +    mcr = I915_READ(GEN8_MCR_SELECTOR);
>> +    mcr = calculate_mcr(dev_priv, mcr);
>> +    I915_WRITE(GEN8_MCR_SELECTOR, mcr);
>> +}
>> +
>>   static void cnl_gt_workarounds_apply(struct drm_i915_private 
>> *dev_priv)
>>   {
>> +    /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
>> +    wa_init_mcr(dev_priv);
>> +
>>       /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
>>       if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
>>           I915_WRITE(GAMT_CHKN_BIT_REG,
>
> With one of the two above (appropriate prefix or store value), this is:
>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
>
> And as a side note: this is also needed for Icelake.
Will do in a separate patch, when I first floated the patch, icl was 
still in internal.

Thanks,
Yunwei

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[PATCH v8 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar
 - Store default MCR value instead of calculate on the run. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 33 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c   | 14 +++++++++++---
 3 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a32ba72..2243a23 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -719,6 +719,36 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static void wa_init_mcr(struct intel_device_info *info)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(info, struct drm_i915_private, info);
+	u32 mcr;
+	u32 mcr_slice_subslice_mask;
+	u32 mcr_slice_subslice_select;
+	u32 slice = fls(info->sseu.slice_mask);
+	u32 subslice = fls(info->sseu.subslice_mask[slice]);
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+					  GEN11_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+						GEN11_MCR_SUBSLICE(subslice);
+	} else {
+		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+					  GEN8_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+						GEN8_MCR_SUBSLICE(subslice);
+	}
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr &= ~mcr_slice_subslice_mask;
+	if (INTEL_GEN(dev_priv) >= 10)
+		mcr |= mcr_slice_subslice_select;
+
+	info->mcr = mcr;
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @info: intel device info struct
@@ -851,6 +881,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	else if (INTEL_INFO(dev_priv)->gen >= 11)
 		gen11_sseu_info_init(dev_priv);
 
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl */
+	wa_init_mcr(info);
+
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 933e316..5449a15 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -176,6 +176,9 @@ struct intel_device_info {
 	/* Slice/subslice/EU info */
 	struct sseu_dev_info sseu;
 
+	/* MCR packet control */
+	u32 mcr;
+
 	u32 cs_timestamp_frequency_khz;
 
 	struct color_luts {
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a83707..08798f2 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -831,18 +831,26 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
 	/*
 	 * The HW expects the slice and sublice selectors to be reset to 0
-	 * after reading out the registers.
+	 * before GEN10 or to a enabled s/ss post GEN10 after reading out the
+	 * registers.
 	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	WARN_ON_ONCE(mcr != dev_priv->info.mcr);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~mcr_slice_subslice_mask;
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+	 * expects mcr to be programed to a enabled slice/subslice pair
+	 * before any MMIO read into slice/subslice register
+	 */
+	mcr = dev_priv->info.mcr;
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
-- 
2.7.4

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Re: [PATCH v8 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 4/17/2018 2:05 PM, Yunwei Zhang wrote:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> References: HSD#1405586840, BSID#0575
>
> v2:
>   - use fls() instead of find_last_bit() (Chris)
>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Change the ordered of passing arguments and etc. (Ursulin)
> v7:
>   - Rebased.
> v8:
>   - Reviewed by Oscar
>   - Store default MCR value instead of calculate on the run. (Oscar)
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_device_info.c | 33 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h |  3 +++
>   drivers/gpu/drm/i915/intel_engine_cs.c   | 14 +++++++++++---
>   3 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a32ba72..2243a23 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -719,6 +719,36 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>   	return 0;
>   }
>   
> +static void wa_init_mcr(struct intel_device_info *info)

mcr_sanitize?

> +{
> +	struct drm_i915_private *dev_priv =
> +		container_of(info, struct drm_i915_private, info);
> +	u32 mcr;
> +	u32 mcr_slice_subslice_mask;
> +	u32 mcr_slice_subslice_select;
> +	u32 slice = fls(info->sseu.slice_mask);
> +	u32 subslice = fls(info->sseu.subslice_mask[slice]);
> +
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
> +					  GEN11_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
> +						GEN11_MCR_SUBSLICE(subslice);
> +	} else {
> +		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
> +					  GEN8_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
> +						GEN8_MCR_SUBSLICE(subslice);
> +	}
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr &= ~mcr_slice_subslice_mask;

Until here you are not applying any WA, only sanitizing what the MCR 
contains. The real WA is in the two following lines. That's where the 
WaProgramMgsrForCorrectSliceSpecificMmioReads label should be (and maybe 
a small comment noting that we are selecting a kind of random 
slice/subslice combination to make sure MMIO reads in a certaing range 
are valid).

> +	if (INTEL_GEN(dev_priv) >= 10)
> +		mcr |= mcr_slice_subslice_select;
> +
> +	info->mcr = mcr;

And now you also want to write the HW register back, otherwise you are 
not applying the WA!

> +}
> +
>   /**
>    * intel_device_info_runtime_init - initialize runtime info
>    * @info: intel device info struct
> @@ -851,6 +881,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>   	else if (INTEL_INFO(dev_priv)->gen >= 11)
>   		gen11_sseu_info_init(dev_priv);
>   
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl */
> +	wa_init_mcr(info);
> +
>   	/* Initialize command stream timestamp frequency */
>   	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>   }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 933e316..5449a15 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -176,6 +176,9 @@ struct intel_device_info {
>   	/* Slice/subslice/EU info */
>   	struct sseu_dev_info sseu;
>   
> +	/* MCR packet control */
> +	u32 mcr;

Use a better name for this, like default_mcr. I'll explain why in a 
second...

> +
>   	u32 cs_timestamp_frequency_khz;
>   
>   	struct color_luts {
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 1a83707..08798f2 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -831,18 +831,26 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>   
>   	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> +
>   	/*
>   	 * The HW expects the slice and sublice selectors to be reset to 0
> -	 * after reading out the registers.
> +	 * before GEN10 or to a enabled s/ss post GEN10 after reading out the
> +	 * registers.
>   	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +	WARN_ON_ONCE(mcr != dev_priv->info.mcr);

... if you call it default_mcr, you can skip the comment completely. 
It's very clear you are just making sure the MCR has the expected value.

>   	mcr &= ~mcr_slice_subslice_mask;
>   	mcr |= mcr_slice_subslice_select;
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	ret = I915_READ_FW(reg);
>   
> -	mcr &= ~mcr_slice_subslice_mask;
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl

No need for this label here, because this is not were the WA should be 
applied!! Hopefully, you already applied it before now.

> +	 * expects mcr to be programed to a enabled slice/subslice pair
> +	 * before any MMIO read into slice/subslice register
> +	 */
> +	mcr = dev_priv->info.mcr;

Same here: with a better naming, it's very clear you are just setting 
the MCR to the default value, so there is no need for any extra comment 
(and remove the following blank line, to show this goes together with 
the I915_WRITE_FW).

> +
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);

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Re: [PATCH v8 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 4/17/2018 2:34 PM, Oscar Mateo wrote:
>
>
> On 4/17/2018 2:05 PM, Yunwei Zhang wrote:
>> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any 
>> MMIO
>> read into Slice/Subslice specific registers, MCR packet control
>> register(0xFDC) needs to be programmed to point to any enabled
>> slice/subslice pair. Otherwise, incorrect value will be returned.
>>
>> However, that means each subsequent MMIO read will be forwarded to a
>> specific slice/subslice combination as read is unicast. This is OK since
>> slice/subslice specific register values are consistent in almost all 
>> cases
>> across slice/subslice. There are rare occasions such as INSTDONE that 
>> this
>> value will be dependent on slice/subslice combo, in such cases, we 
>> need to
>> program 0xFDC and recover this after. This is already covered by
>> read_subslice_reg.
>>
>> Also, 0xFDC will lose its information after TDR/engine reset/power state
>> change.
>>
>> References: HSD#1405586840, BSID#0575
>>
>> v2:
>>   - use fls() instead of find_last_bit() (Chris)
>>   - added INTEL_SSEU to extract sseu from device info. (Chris)
>> v3:
>>   - rebase on latest tip
>> v5:
>>   - Added references (Mika)
>>   - Change the ordered of passing arguments and etc. (Ursulin)
>> v7:
>>   - Rebased.
>> v8:
>>   - Reviewed by Oscar
>>   - Store default MCR value instead of calculate on the run. (Oscar)
>>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
>> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_device_info.c | 33 
>> ++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_device_info.h |  3 +++
>>   drivers/gpu/drm/i915/intel_engine_cs.c   | 14 +++++++++++---
>>   3 files changed, 47 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index a32ba72..2243a23 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -719,6 +719,36 @@ static u32 read_timestamp_frequency(struct 
>> drm_i915_private *dev_priv)
>>       return 0;
>>   }
>>   +static void wa_init_mcr(struct intel_device_info *info)
>
> mcr_sanitize?
>
>> +{
>> +    struct drm_i915_private *dev_priv =
>> +        container_of(info, struct drm_i915_private, info);
>> +    u32 mcr;
>> +    u32 mcr_slice_subslice_mask;
>> +    u32 mcr_slice_subslice_select;
>> +    u32 slice = fls(info->sseu.slice_mask);
>> +    u32 subslice = fls(info->sseu.subslice_mask[slice]);
>> +
>> +    if (INTEL_GEN(dev_priv) >= 11) {
>> +        mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>> +                      GEN11_MCR_SUBSLICE_MASK;
>> +        mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
>> +                        GEN11_MCR_SUBSLICE(subslice);
>> +    } else {
>> +        mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
>> +                      GEN8_MCR_SUBSLICE_MASK;
>> +        mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
>> +                        GEN8_MCR_SUBSLICE(subslice);
>> +    }
>> +
>> +    mcr = I915_READ(GEN8_MCR_SELECTOR);
>> +    mcr &= ~mcr_slice_subslice_mask;
>
> Until here you are not applying any WA, only sanitizing what the MCR 
> contains. The real WA is in the two following lines. That's where the 
> WaProgramMgsrForCorrectSliceSpecificMmioReads label should be (and 
> maybe a small comment noting that we are selecting a kind of random 
> slice/subslice combination to make sure MMIO reads in a certaing range 
> are valid).
>
>> +    if (INTEL_GEN(dev_priv) >= 10)
>> +        mcr |= mcr_slice_subslice_select;
>> +
>> +    info->mcr = mcr;
>

An extra thought: technically, you don't care about the whole MCR, only 
the bits in mcr_slice_subslice_mask. I doubt the other bits can change 
but, if you want to be thorough, store only those bits and avoid making 
assumptions about the rest in read_subslice_reg.

> And now you also want to write the HW register back, otherwise you are 
> not applying the WA!
>
>> +}
>> +
>>   /**
>>    * intel_device_info_runtime_init - initialize runtime info
>>    * @info: intel device info struct
>> @@ -851,6 +881,9 @@ void intel_device_info_runtime_init(struct 
>> intel_device_info *info)
>>       else if (INTEL_INFO(dev_priv)->gen >= 11)
>>           gen11_sseu_info_init(dev_priv);
>>   +    /* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl */
>> +    wa_init_mcr(info);
>> +
>>       /* Initialize command stream timestamp frequency */
>>       info->cs_timestamp_frequency_khz = 
>> read_timestamp_frequency(dev_priv);
>>   }
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
>> b/drivers/gpu/drm/i915/intel_device_info.h
>> index 933e316..5449a15 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -176,6 +176,9 @@ struct intel_device_info {
>>       /* Slice/subslice/EU info */
>>       struct sseu_dev_info sseu;
>>   +    /* MCR packet control */
>> +    u32 mcr;
>
> Use a better name for this, like default_mcr. I'll explain why in a 
> second...
>
>> +
>>       u32 cs_timestamp_frequency_khz;
>>         struct color_luts {
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
>> b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 1a83707..08798f2 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -831,18 +831,26 @@ read_subslice_reg(struct drm_i915_private 
>> *dev_priv, int slice,
>>       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>>         mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
>> +
>>       /*
>>        * The HW expects the slice and sublice selectors to be reset to 0
>> -     * after reading out the registers.
>> +     * before GEN10 or to a enabled s/ss post GEN10 after reading 
>> out the
>> +     * registers.
>>        */
>> -    WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
>> +    WARN_ON_ONCE(mcr != dev_priv->info.mcr);
>
> ... if you call it default_mcr, you can skip the comment completely. 
> It's very clear you are just making sure the MCR has the expected value.
>
>>       mcr &= ~mcr_slice_subslice_mask;
>>       mcr |= mcr_slice_subslice_select;
>>       I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>         ret = I915_READ_FW(reg);
>>   -    mcr &= ~mcr_slice_subslice_mask;
>> +    /*
>> +     * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
>
> No need for this label here, because this is not were the WA should be 
> applied!! Hopefully, you already applied it before now.
>
>> +     * expects mcr to be programed to a enabled slice/subslice pair
>> +     * before any MMIO read into slice/subslice register
>> +     */
>> +    mcr = dev_priv->info.mcr;
>
> Same here: with a better naming, it's very clear you are just setting 
> the MCR to the default value, so there is no need for any extra 
> comment (and remove the following blank line, to show this goes 
> together with the I915_WRITE_FW).
>
>> +
>>       I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>>         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
>

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[PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar
 - Store default MCR value instead of calculate on the run. (Oscar)
v9:
 - Changed naming and label fixes. (Oscar)
 - Store only the selector instead of whole MCR. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 35 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c   | 14 ++++++++-----
 3 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a32ba72..1a4288f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -719,6 +719,39 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static void sanitize_mcr(struct intel_device_info *info)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(info, struct drm_i915_private, info);
+	u32 mcr;
+	u32 mcr_slice_subslice_mask;
+	u32 mcr_slice_subslice_select;
+	u32 slice = fls(info->sseu.slice_mask);
+	u32 subslice = fls(info->sseu.subslice_mask[slice]);
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+					  GEN11_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+						GEN11_MCR_SUBSLICE(subslice);
+	} else {
+		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+					  GEN8_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+						GEN8_MCR_SUBSLICE(subslice);
+	}
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr &= ~mcr_slice_subslice_mask;
+
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl */
+	if (INTEL_GEN(dev_priv) >= 10)
+		mcr |= mcr_slice_subslice_select;
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+
+	info->default_mcr_ss_select = mcr_slice_subslice_select;
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @info: intel device info struct
@@ -851,6 +884,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	else if (INTEL_INFO(dev_priv)->gen >= 11)
 		gen11_sseu_info_init(dev_priv);
 
+	sanitize_mcr(info);
+
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 933e316..2c47a62 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -176,6 +176,9 @@ struct intel_device_info {
 	/* Slice/subslice/EU info */
 	struct sseu_dev_info sseu;
 
+	/* default selected slice/subslice in MCR packet control */
+	u32 default_mcr_ss_select;
+
 	u32 cs_timestamp_frequency_khz;
 
 	struct color_luts {
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a83707..1ba2826 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -831,18 +831,22 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
-	/*
-	 * The HW expects the slice and sublice selectors to be reset to 0
-	 * after reading out the registers.
-	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+
+	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
+		      dev_priv->info.default_mcr_ss_select);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
+	/*
+	 * HW expects MCR to be programed to a enabled slice/subslice pair
+	 * before any MMIO read into slice/subslice register
+	 */
 	mcr &= ~mcr_slice_subslice_mask;
+	mcr |= dev_priv->info.default_mcr_ss_select;
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
-- 
2.7.4

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Re: [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> References: HSD#1405586840, BSID#0575
>
> v2:
>   - use fls() instead of find_last_bit() (Chris)
>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Change the ordered of passing arguments and etc. (Ursulin)
> v7:
>   - Rebased.
> v8:
>   - Reviewed by Oscar
>   - Store default MCR value instead of calculate on the run. (Oscar)
> v9:
>   - Changed naming and label fixes. (Oscar)
>   - Store only the selector instead of whole MCR. (Oscar)
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_device_info.c | 35 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h |  3 +++
>   drivers/gpu/drm/i915/intel_engine_cs.c   | 14 ++++++++-----
>   3 files changed, 47 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a32ba72..1a4288f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -719,6 +719,39 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>   	return 0;
>   }
>   
> +static void sanitize_mcr(struct intel_device_info *info)
> +{
> +	struct drm_i915_private *dev_priv =
> +		container_of(info, struct drm_i915_private, info);
> +	u32 mcr;
> +	u32 mcr_slice_subslice_mask;
> +	u32 mcr_slice_subslice_select;
> +	u32 slice = fls(info->sseu.slice_mask);
> +	u32 subslice = fls(info->sseu.subslice_mask[slice]);
> +
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
> +					  GEN11_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
> +						GEN11_MCR_SUBSLICE(subslice);
> +	} else {
> +		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
> +					  GEN8_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
> +						GEN8_MCR_SUBSLICE(subslice);
> +	}
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr &= ~mcr_slice_subslice_mask;
> +
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl */
> +	if (INTEL_GEN(dev_priv) >= 10)
> +		mcr |= mcr_slice_subslice_select;

Blank line here. The I915_WRITE is both for the WA and for the 
sanitation of the register.

> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +
> +	info->default_mcr_ss_select = mcr_slice_subslice_select;
> +}
> +
>   /**
>    * intel_device_info_runtime_init - initialize runtime info
>    * @info: intel device info struct
> @@ -851,6 +884,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>   	else if (INTEL_INFO(dev_priv)->gen >= 11)
>   		gen11_sseu_info_init(dev_priv);
>   
> +	sanitize_mcr(info);
> +
>   	/* Initialize command stream timestamp frequency */
>   	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>   }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 933e316..2c47a62 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -176,6 +176,9 @@ struct intel_device_info {
>   	/* Slice/subslice/EU info */
>   	struct sseu_dev_info sseu;
>   
> +	/* default selected slice/subslice in MCR packet control */
> +	u32 default_mcr_ss_select;
> +

default_mcr_s_ss_select? (yes, I know we are not coherent with the 
meaning of 's' and 'ss' in many other places).

>   	u32 cs_timestamp_frequency_khz;
>   
>   	struct color_luts {
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 1a83707..1ba2826 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -831,18 +831,22 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>   
>   	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> -	/*
> -	 * The HW expects the slice and sublice selectors to be reset to 0
> -	 * after reading out the registers.
> -	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +
> +	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
> +		      dev_priv->info.default_mcr_ss_select);
>   	mcr &= ~mcr_slice_subslice_mask;
>   	mcr |= mcr_slice_subslice_select;
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	ret = I915_READ_FW(reg);
>   
> +	/*
> +	 * HW expects MCR to be programed to a enabled slice/subslice pair
> +	 * before any MMIO read into slice/subslice register
> +	 */

The comment above makes more sense in sanitize_mcr, together with the WA 
label. You can make it a bit more verbose with the info in the commit 
message. Something like this:

/*
  * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
  * Before any MMIO read into slice/subslice specific registers, MCR
  * packet control register needs to be programmed to point to any
  * enabled s/ss pair. Otherwise, incorrect values will be returned.
  * This means each subsequent MMIO read will be forwarded to an
  * specific s/ss combination, but this is OK since these registers
  * are consistent across s/ss in almost all cases. In the rare
  * occasions, such as INSTDONE, where this value is dependent
  * on s/ss combo, the read shoud be done with read_subslice_reg.
  */

I don't think any other comment is required here.

>   	mcr &= ~mcr_slice_subslice_mask;
> +	mcr |= dev_priv->info.default_mcr_ss_select;
> +
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);

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Re: [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Chris Wilson]

Quoting Oscar Mateo (2018-04-18 17:30:41)
> 
> 
> On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
> > +     /*
> > +      * HW expects MCR to be programed to a enabled slice/subslice pair
> > +      * before any MMIO read into slice/subslice register
> > +      */
> 
> The comment above makes more sense in sanitize_mcr, together with the WA 
> label. You can make it a bit more verbose with the info in the commit 
> message. Something like this:
> 
> /*
>   * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
>   * Before any MMIO read into slice/subslice specific registers, MCR
>   * packet control register needs to be programmed to point to any
>   * enabled s/ss pair. Otherwise, incorrect values will be returned.
>   * This means each subsequent MMIO read will be forwarded to an
>   * specific s/ss combination, but this is OK since these registers
>   * are consistent across s/ss in almost all cases. In the rare
>   * occasions, such as INSTDONE, where this value is dependent
>   * on s/ss combo, the read shoud be done with read_subslice_reg.
>   */
> 
> I don't think any other comment is required here.

Apart from the answer to the earlier question, what mmio read after this
point? If all slice/subslice register access is through this function,
what are you trying to protect? Very curious.
-Chris
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Re: [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 4/18/2018 9:38 AM, Chris Wilson wrote:
> Quoting Oscar Mateo (2018-04-18 17:30:41)
>>
>> On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
>>> +     /*
>>> +      * HW expects MCR to be programed to a enabled slice/subslice pair
>>> +      * before any MMIO read into slice/subslice register
>>> +      */
>> The comment above makes more sense in sanitize_mcr, together with the WA
>> label. You can make it a bit more verbose with the info in the commit
>> message. Something like this:
>>
>> /*
>>    * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
>>    * Before any MMIO read into slice/subslice specific registers, MCR
>>    * packet control register needs to be programmed to point to any
>>    * enabled s/ss pair. Otherwise, incorrect values will be returned.
>>    * This means each subsequent MMIO read will be forwarded to an
>>    * specific s/ss combination, but this is OK since these registers
>>    * are consistent across s/ss in almost all cases. In the rare
>>    * occasions, such as INSTDONE, where this value is dependent
>>    * on s/ss combo, the read shoud be done with read_subslice_reg.
>>    */
>>
>> I don't think any other comment is required here.
> Apart from the answer to the earlier question, what mmio read after this
> point? If all slice/subslice register access is through this function,
> what are you trying to protect? Very curious.
> -Chris

The problem is that the BSpec does not have a comprehensive list of 
registers that live in the slice/subslice, so it's difficult to know 
when this is going to become a problem. For example, I know from 
previous experience that the MOCS tables are replicated across slices 
(that's why we couldn't let UMD decide when to shutdown them: because 
the MOCS tables get lost as soon as you reconfigure the number of s/ss. 
The only way to do this in by poking in the context, so that the MOCS 
gets reprogrammed immediately after).
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Re: [PATCH v9 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 4/18/2018 9:45 AM, Oscar Mateo wrote:
>
>
> On 4/18/2018 9:38 AM, Chris Wilson wrote:
>> Quoting Oscar Mateo (2018-04-18 17:30:41)
>>>
>>> On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
>>>> +     /*
>>>> +      * HW expects MCR to be programed to a enabled slice/subslice 
>>>> pair
>>>> +      * before any MMIO read into slice/subslice register
>>>> +      */
>>> The comment above makes more sense in sanitize_mcr, together with 
>>> the WA
>>> label. You can make it a bit more verbose with the info in the commit
>>> message. Something like this:
>>>
>>> /*
>>>    * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
>>>    * Before any MMIO read into slice/subslice specific registers, MCR
>>>    * packet control register needs to be programmed to point to any
>>>    * enabled s/ss pair. Otherwise, incorrect values will be returned.
>>>    * This means each subsequent MMIO read will be forwarded to an
>>>    * specific s/ss combination, but this is OK since these registers
>>>    * are consistent across s/ss in almost all cases. In the rare
>>>    * occasions, such as INSTDONE, where this value is dependent
>>>    * on s/ss combo, the read shoud be done with read_subslice_reg.
>>>    */
>>>
>>> I don't think any other comment is required here.
>> Apart from the answer to the earlier question, what mmio read after this
>> point? If all slice/subslice register access is through this function,
>> what are you trying to protect? Very curious.
>> -Chris
>
> The problem is that the BSpec does not have a comprehensive list of 
> registers that live in the slice/subslice, so it's difficult to know 
> when this is going to become a problem. For example, I know from 
> previous experience that the MOCS tables are replicated across slices 
> (that's why we couldn't let UMD decide when to shutdown them: because 
> the MOCS tables get lost as soon as you reconfigure the number of 
> s/ss. The only way to do this in by poking in the context, so that the 
> MOCS gets reprogrammed immediately after).

This hasn't been an issue until know because the hardware would route 
your read to a valid s/ss combo whenever the MCR select was 0s. 
Apparently, this is not the case anymore...
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[PATCH v10 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar
 - Store default MCR value instead of calculate on the run. (Oscar)
v9:
 - Changed naming and label fixes. (Oscar)
 - Store only the selector instead of whole MCR. (Oscar)
v10:
 - Improved comments, naming and line breaknig. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 48 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  3 ++
 drivers/gpu/drm/i915/intel_engine_cs.c   | 10 +++----
 3 files changed, 56 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a32ba72..3791b52 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -719,6 +719,52 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+
+/*
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+ * Before any MMIO read into slice/subslice specific registers, MCR
+ * packet control register needs to be programmed to point to any
+ * enabled s/ss pair. Otherwise, incorrect values will be returned.
+ * This means each subsequent MMIO read will be forwarded to an
+ * specific s/ss combination, but this is OK since these registers
+ * are consistent across s/ss in almost all cases. In the rare
+ * occasions, such as INSTDONE, where this value is dependent
+ * on s/ss combo, the read should be done with read_subslice_reg.
+ */
+static void sanitize_mcr(struct intel_device_info *info)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(info, struct drm_i915_private, info);
+	u32 mcr;
+	u32 mcr_slice_subslice_mask;
+	u32 mcr_slice_subslice_select;
+	u32 slice = fls(info->sseu.slice_mask);
+	u32 subslice = fls(info->sseu.subslice_mask[slice]);
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+					  GEN11_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+						GEN11_MCR_SUBSLICE(subslice);
+	} else {
+		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+					  GEN8_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+						GEN8_MCR_SUBSLICE(subslice);
+	}
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr &= ~mcr_slice_subslice_mask;
+
+	/* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl */
+	if (INTEL_GEN(dev_priv) >= 10)
+		mcr |= mcr_slice_subslice_select;
+
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+
+	info->default_mcr_s_ss_select = mcr_slice_subslice_select;
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @info: intel device info struct
@@ -851,6 +897,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	else if (INTEL_INFO(dev_priv)->gen >= 11)
 		gen11_sseu_info_init(dev_priv);
 
+	sanitize_mcr(info);
+
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 933e316..2feccee 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -176,6 +176,9 @@ struct intel_device_info {
 	/* Slice/subslice/EU info */
 	struct sseu_dev_info sseu;
 
+	/* default selected slice/subslice in MCR packet control */
+	u32 default_mcr_s_ss_select;
+
 	u32 cs_timestamp_frequency_khz;
 
 	struct color_luts {
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a83707..2b24277 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -831,11 +831,9 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
-	/*
-	 * The HW expects the slice and sublice selectors to be reset to 0
-	 * after reading out the registers.
-	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+
+	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
+		      dev_priv->info.default_mcr_s_ss_select);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
@@ -843,6 +841,8 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	ret = I915_READ_FW(reg);
 
 	mcr &= ~mcr_slice_subslice_mask;
+	mcr |= dev_priv->info.default_mcr_s_ss_select;
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
-- 
2.7.4

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Re: [PATCH v10 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 4/18/2018 1:23 PM, Yunwei Zhang wrote:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> References: HSD#1405586840, BSID#0575
>
> v2:
>   - use fls() instead of find_last_bit() (Chris)
>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Change the ordered of passing arguments and etc. (Ursulin)
> v7:
>   - Rebased.
> v8:
>   - Reviewed by Oscar
>   - Store default MCR value instead of calculate on the run. (Oscar)
> v9:
>   - Changed naming and label fixes. (Oscar)
>   - Store only the selector instead of whole MCR. (Oscar)
> v10:
>   - Improved comments, naming and line breaknig. (Oscar)
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_device_info.c | 48 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h |  3 ++
>   drivers/gpu/drm/i915/intel_engine_cs.c   | 10 +++----
>   3 files changed, 56 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a32ba72..3791b52 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -719,6 +719,52 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>   	return 0;
>   }
>   
> +
> +/*
> + * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
> + * Before any MMIO read into slice/subslice specific registers, MCR
> + * packet control register needs to be programmed to point to any
> + * enabled s/ss pair. Otherwise, incorrect values will be returned.
> + * This means each subsequent MMIO read will be forwarded to an
> + * specific s/ss combination, but this is OK since these registers
> + * are consistent across s/ss in almost all cases. In the rare
> + * occasions, such as INSTDONE, where this value is dependent
> + * on s/ss combo, the read should be done with read_subslice_reg.
> + */

If you move the above comment block to the actual WA, which is:

if (INTEL_GEN(dev_priv) >= 10)
	mcr |= mcr_slice_subslice_select;


this patch is:

Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

this time for real :)

> +static void sanitize_mcr(struct intel_device_info *info)
> +{
> +	struct drm_i915_private *dev_priv =
> +		container_of(info, struct drm_i915_private, info);
> +	u32 mcr;
> +	u32 mcr_slice_subslice_mask;
> +	u32 mcr_slice_subslice_select;
> +	u32 slice = fls(info->sseu.slice_mask);
> +	u32 subslice = fls(info->sseu.subslice_mask[slice]);
> +
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
> +					  GEN11_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
> +						GEN11_MCR_SUBSLICE(subslice);
> +	} else {
> +		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
> +					  GEN8_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
> +						GEN8_MCR_SUBSLICE(subslice);
> +	}
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr &= ~mcr_slice_subslice_mask;
> +
> +	/* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl */
> +	if (INTEL_GEN(dev_priv) >= 10)
> +		mcr |= mcr_slice_subslice_select;
> +
> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +
> +	info->default_mcr_s_ss_select = mcr_slice_subslice_select;
> +}
> +
>   /**
>    * intel_device_info_runtime_init - initialize runtime info
>    * @info: intel device info struct
> @@ -851,6 +897,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>   	else if (INTEL_INFO(dev_priv)->gen >= 11)
>   		gen11_sseu_info_init(dev_priv);
>   
> +	sanitize_mcr(info);
> +
>   	/* Initialize command stream timestamp frequency */
>   	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>   }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 933e316..2feccee 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -176,6 +176,9 @@ struct intel_device_info {
>   	/* Slice/subslice/EU info */
>   	struct sseu_dev_info sseu;
>   
> +	/* default selected slice/subslice in MCR packet control */
> +	u32 default_mcr_s_ss_select;
> +
>   	u32 cs_timestamp_frequency_khz;
>   
>   	struct color_luts {
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 1a83707..2b24277 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -831,11 +831,9 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>   
>   	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> -	/*
> -	 * The HW expects the slice and sublice selectors to be reset to 0
> -	 * after reading out the registers.
> -	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +
> +	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
> +		      dev_priv->info.default_mcr_s_ss_select);
>   	mcr &= ~mcr_slice_subslice_mask;
>   	mcr |= mcr_slice_subslice_select;
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
> @@ -843,6 +841,8 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	ret = I915_READ_FW(reg);
>   
>   	mcr &= ~mcr_slice_subslice_mask;
> +	mcr |= dev_priv->info.default_mcr_s_ss_select;
> +
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);

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[PATCH v11 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar
 - Store default MCR value instead of calculate on the run. (Oscar)
v9:
 - Changed naming and label fixes. (Oscar)
 - Store only the selector instead of whole MCR. (Oscar)
v10:
 - Improved comments, naming and line breaknig. (Oscar)
v11:
 - Moved the comment to most relavent block. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 47 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  3 ++
 drivers/gpu/drm/i915/intel_engine_cs.c   | 10 +++----
 3 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a32ba72..ea62d45 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -719,6 +719,51 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+
+static void sanitize_mcr(struct intel_device_info *info)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(info, struct drm_i915_private, info);
+	u32 mcr;
+	u32 mcr_slice_subslice_mask;
+	u32 mcr_slice_subslice_select;
+	u32 slice = fls(info->sseu.slice_mask);
+	u32 subslice = fls(info->sseu.subslice_mask[slice]);
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+					  GEN11_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+						GEN11_MCR_SUBSLICE(subslice);
+	} else {
+		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+					  GEN8_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+						GEN8_MCR_SUBSLICE(subslice);
+	}
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr &= ~mcr_slice_subslice_mask;
+
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+	 * Before any MMIO read into slice/subslice specific registers, MCR
+	 * packet control register needs to be programmed to point to any
+	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
+	 * This means each subsequent MMIO read will be forwarded to an
+	 * specific s/ss combination, but this is OK since these registers
+	 * are consistent across s/ss in almost all cases. In the rare
+	 * occasions, such as INSTDONE, where this value is dependent
+	 * on s/ss combo, the read should be done with read_subslice_reg.
+	 */
+	if (INTEL_GEN(dev_priv) >= 10)
+		mcr |= mcr_slice_subslice_select;
+
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+
+	info->default_mcr_s_ss_select = mcr_slice_subslice_select;
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @info: intel device info struct
@@ -851,6 +896,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	else if (INTEL_INFO(dev_priv)->gen >= 11)
 		gen11_sseu_info_init(dev_priv);
 
+	sanitize_mcr(info);
+
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 933e316..2feccee 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -176,6 +176,9 @@ struct intel_device_info {
 	/* Slice/subslice/EU info */
 	struct sseu_dev_info sseu;
 
+	/* default selected slice/subslice in MCR packet control */
+	u32 default_mcr_s_ss_select;
+
 	u32 cs_timestamp_frequency_khz;
 
 	struct color_luts {
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a83707..2b24277 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -831,11 +831,9 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
-	/*
-	 * The HW expects the slice and sublice selectors to be reset to 0
-	 * after reading out the registers.
-	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+
+	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
+		      dev_priv->info.default_mcr_s_ss_select);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
@@ -843,6 +841,8 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	ret = I915_READ_FW(reg);
 
 	mcr &= ~mcr_slice_subslice_mask;
+	mcr |= dev_priv->info.default_mcr_s_ss_select;
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
-- 
2.7.4

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Re: [PATCH v11 1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo]

On 4/18/2018 3:01 PM, Yunwei Zhang wrote:
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
>
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg.
>
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
>
> References: HSD#1405586840, BSID#0575
>
> v2:
>   - use fls() instead of find_last_bit() (Chris)
>   - added INTEL_SSEU to extract sseu from device info. (Chris)
> v3:
>   - rebase on latest tip
> v5:
>   - Added references (Mika)
>   - Change the ordered of passing arguments and etc. (Ursulin)
> v7:
>   - Rebased.
> v8:
>   - Reviewed by Oscar
>   - Store default MCR value instead of calculate on the run. (Oscar)
> v9:
>   - Changed naming and label fixes. (Oscar)
>   - Store only the selector instead of whole MCR. (Oscar)
> v10:
>   - Improved comments, naming and line breaknig. (Oscar)
> v11:
>   - Moved the comment to most relavent block. (Oscar)
>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_device_info.c | 47 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h |  3 ++
>   drivers/gpu/drm/i915/intel_engine_cs.c   | 10 +++----
>   3 files changed, 55 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a32ba72..ea62d45 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -719,6 +719,51 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>   	return 0;
>   }
>   
> +
> +static void sanitize_mcr(struct intel_device_info *info)
> +{
> +	struct drm_i915_private *dev_priv =
> +		container_of(info, struct drm_i915_private, info);
> +	u32 mcr;
> +	u32 mcr_slice_subslice_mask;
> +	u32 mcr_slice_subslice_select;
> +	u32 slice = fls(info->sseu.slice_mask);
> +	u32 subslice = fls(info->sseu.subslice_mask[slice]);
> +
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
> +					  GEN11_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
> +						GEN11_MCR_SUBSLICE(subslice);
> +	} else {
> +		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
> +					  GEN8_MCR_SUBSLICE_MASK;
> +		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
> +						GEN8_MCR_SUBSLICE(subslice);
> +	}
> +
> +	mcr = I915_READ(GEN8_MCR_SELECTOR);
> +	mcr &= ~mcr_slice_subslice_mask;
> +
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
> +	 * Before any MMIO read into slice/subslice specific registers, MCR
> +	 * packet control register needs to be programmed to point to any
> +	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
> +	 * This means each subsequent MMIO read will be forwarded to an
> +	 * specific s/ss combination, but this is OK since these registers
> +	 * are consistent across s/ss in almost all cases. In the rare
> +	 * occasions, such as INSTDONE, where this value is dependent
> +	 * on s/ss combo, the read should be done with read_subslice_reg.
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 10)
> +		mcr |= mcr_slice_subslice_select;
> +
> +	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
> +
> +	info->default_mcr_s_ss_select = mcr_slice_subslice_select;

Sorry: forget my r-b, this is broken. For GENs that do not need the WA, 
info->default_mcr_s_ss_select should be 0

> +}
> +
>   /**
>    * intel_device_info_runtime_init - initialize runtime info
>    * @info: intel device info struct
> @@ -851,6 +896,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>   	else if (INTEL_INFO(dev_priv)->gen >= 11)
>   		gen11_sseu_info_init(dev_priv);
>   
> +	sanitize_mcr(info);
> +
>   	/* Initialize command stream timestamp frequency */
>   	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>   }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 933e316..2feccee 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -176,6 +176,9 @@ struct intel_device_info {
>   	/* Slice/subslice/EU info */
>   	struct sseu_dev_info sseu;
>   
> +	/* default selected slice/subslice in MCR packet control */
> +	u32 default_mcr_s_ss_select;
> +
>   	u32 cs_timestamp_frequency_khz;
>   
>   	struct color_luts {
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 1a83707..2b24277 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -831,11 +831,9 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
>   
>   	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> -	/*
> -	 * The HW expects the slice and sublice selectors to be reset to 0
> -	 * after reading out the registers.
> -	 */
> -	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
> +
> +	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
> +		      dev_priv->info.default_mcr_s_ss_select);
>   	mcr &= ~mcr_slice_subslice_mask;
>   	mcr |= mcr_slice_subslice_select;
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
> @@ -843,6 +841,8 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
>   	ret = I915_READ_FW(reg);
>   
>   	mcr &= ~mcr_slice_subslice_mask;
> +	mcr |= dev_priv->info.default_mcr_s_ss_select;
> +
>   	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
>   
>   	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);

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[PATCH v12 1/3] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
 - use fls() instead of find_last_bit() (Chris)
 - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
 - rebase on latest tip
v5:
 - Added references (Mika)
 - Change the ordered of passing arguments and etc. (Ursulin)
v7:
 - Rebased.
v8:
 - Reviewed by Oscar
 - Store default MCR value instead of calculate on the run. (Oscar)
v9:
 - Changed naming and label fixes. (Oscar)
 - Store only the selector instead of whole MCR. (Oscar)
v10:
 - Improved comments, naming and line breaknig. (Oscar)
v11:
 - Moved the comment to most relavent block. (Oscar)
v12:
 - set default s/ss selector to 0 for pre-GEN10. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 49 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  3 ++
 drivers/gpu/drm/i915/intel_engine_cs.c   | 10 +++----
 3 files changed, 57 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a32ba72..d917c9b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -719,6 +719,53 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static void sanitize_mcr(struct intel_device_info *info)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(info, struct drm_i915_private, info);
+	u32 mcr;
+	u32 mcr_slice_subslice_mask;
+	u32 mcr_slice_subslice_select;
+	u32 slice = fls(info->sseu.slice_mask);
+	u32 subslice = fls(info->sseu.subslice_mask[slice]);
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+					  GEN11_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+						GEN11_MCR_SUBSLICE(subslice);
+	} else {
+		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+					  GEN8_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+						GEN8_MCR_SUBSLICE(subslice);
+	}
+
+	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	mcr &= ~mcr_slice_subslice_mask;
+
+	info->default_mcr_s_ss_select = 0;
+
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+	 * Before any MMIO read into slice/subslice specific registers, MCR
+	 * packet control register needs to be programmed to point to any
+	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
+	 * This means each subsequent MMIO read will be forwarded to an
+	 * specific s/ss combination, but this is OK since these registers
+	 * are consistent across s/ss in almost all cases. In the rare
+	 * occasions, such as INSTDONE, where this value is dependent
+	 * on s/ss combo, the read should be done with read_subslice_reg.
+	 */
+	if (INTEL_GEN(dev_priv) >= 10) {
+		mcr |= mcr_slice_subslice_select;
+
+		info->default_mcr_s_ss_select = mcr_slice_subslice_select;
+	}
+
+	I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @info: intel device info struct
@@ -851,6 +898,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	else if (INTEL_INFO(dev_priv)->gen >= 11)
 		gen11_sseu_info_init(dev_priv);
 
+	sanitize_mcr(info);
+
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 933e316..2feccee 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -176,6 +176,9 @@ struct intel_device_info {
 	/* Slice/subslice/EU info */
 	struct sseu_dev_info sseu;
 
+	/* default selected slice/subslice in MCR packet control */
+	u32 default_mcr_s_ss_select;
+
 	u32 cs_timestamp_frequency_khz;
 
 	struct color_luts {
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1a83707..2b24277 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -831,11 +831,9 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
 	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
-	/*
-	 * The HW expects the slice and sublice selectors to be reset to 0
-	 * after reading out the registers.
-	 */
-	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+
+	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
+		      dev_priv->info.default_mcr_s_ss_select);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
@@ -843,6 +841,8 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	ret = I915_READ_FW(reg);
 
 	mcr &= ~mcr_slice_subslice_mask;
+	mcr |= dev_priv->info.default_mcr_s_ss_select;
+
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)
URL   : https://patchwork.freedesktop.org/series/40503/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
530daf66ff2f drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
4faf11aff784 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
-:71: CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
#71: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:829:
+			       | sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)
 			                                   ^

total: 0 errors, 0 warnings, 1 checks, 35 lines checked

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✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

Series 40503v3 series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/3/mbox/

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:436s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:440s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:385s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:539s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:296s
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:515s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:517s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:520s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:505s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:412s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:510s
fi-elk-e7500     total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  time:430s
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:318s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:534s
fi-hsw-4770      total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:411s
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:422s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:473s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:431s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:475s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:471s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:514s
fi-pnv-d510      total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  time:659s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:438s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:537s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:511s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:498s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:427s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:448s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:403s
Blacklisted hosts:
fi-cfl-s3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:567s
fi-glk-j4005     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:484s

bac611eda28af14ef7e2549932c440885bfe58bb drm-tip: 2018y-03m-26d-15h-45m-06s UTC integration manifest
4faf11aff784 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
530daf66ff2f drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8493/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev3)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

---- Possible new issues:

Test kms_rotation_crc:
        Subgroup cursor-rotation-180:
                fail       -> PASS       (shard-snb)

---- Known issues:

Test kms_flip:
        Subgroup plain-flip-ts-check:
                pass       -> FAIL       (shard-hsw) fdo#100368 +3
Test kms_plane_multiple:
        Subgroup atomic-pipe-a-tiling-x:
                fail       -> PASS       (shard-snb) fdo#103166
Test kms_rotation_crc:
        Subgroup primary-rotation-180:
                pass       -> FAIL       (shard-snb) fdo#103925

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925

shard-apl        total:3495 pass:1831 dwarn:1   dfail:0   fail:7   skip:1655 time:12810s
shard-hsw        total:3495 pass:1780 dwarn:1   dfail:0   fail:4   skip:1709 time:11592s
shard-snb        total:3495 pass:1374 dwarn:1   dfail:0   fail:3   skip:2117 time:6975s
Blacklisted hosts:
shard-kbl        total:3495 pass:1956 dwarn:1   dfail:0   fail:9   skip:1529 time:9631s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8493/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev5)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev5)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

Series 40503v5 series starting with [v5,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/5/mbox/

---- Known issues:

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                fail       -> PASS       (fi-gdg-551) fdo#102575
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (fi-snb-2520m) fdo#100368

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:431s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:448s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:382s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:545s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:299s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:515s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:530s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:512s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:409s
fi-cfl-s3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:569s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:508s
fi-cnl-y3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:582s
fi-elk-e7500     total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  time:428s
fi-gdg-551       total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 time:320s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:539s
fi-hsw-4770      total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:403s
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:423s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:473s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:433s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:473s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:471s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:516s
fi-pnv-d510      total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  time:658s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:444s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:535s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:508s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:491s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:429s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:445s
fi-snb-2520m     total:285  pass:244  dwarn:0   dfail:0   fail:1   skip:40  time:552s
Blacklisted hosts:
fi-cnl-psr       total:285  pass:248  dwarn:11  dfail:0   fail:0   skip:26  time:515s
fi-glk-j4005     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:488s

0539b52e05cd0abe697d45f2a2373ec42af7ebcb drm-tip: 2018y-03m-27d-18h-45m-40s UTC integration manifest
791751056113 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
4c68480f0be0 drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8512/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [v5,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev5)

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev5)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

---- Known issues:

Test kms_cursor_crc:
        Subgroup cursor-128x128-suspend:
                dmesg-warn -> PASS       (shard-snb) fdo#102365 +1
Test kms_flip:
        Subgroup 2x-dpms-vs-vblank-race-interruptible:
                fail       -> PASS       (shard-hsw) fdo#103060 +1
        Subgroup 2x-flip-vs-expired-vblank-interruptible:
                fail       -> PASS       (shard-hsw) fdo#102887 +1
Test kms_plane_multiple:
        Subgroup atomic-pipe-a-tiling-x:
                pass       -> FAIL       (shard-snb) fdo#103166
Test perf:
        Subgroup polling:
                fail       -> PASS       (shard-hsw) fdo#102252

fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apl        total:3495 pass:1831 dwarn:1   dfail:0   fail:7   skip:1655 time:12908s
shard-hsw        total:3495 pass:1782 dwarn:1   dfail:0   fail:2   skip:1709 time:11739s
shard-snb        total:3411 pass:1347 dwarn:1   dfail:0   fail:4   skip:2058 time:6819s
Blacklisted hosts:
shard-kbl        total:3495 pass:1953 dwarn:3   dfail:1   fail:9   skip:1529 time:9711s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8512/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev6)

[Patchwork]

== Series Details ==

Series: series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev6)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

Series 40503v6 series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/6/mbox/

---- Possible new issues:

Test drv_module_reload:
        Subgroup basic-reload-inject:
                pass       -> INCOMPLETE (fi-elk-e7500)

---- Known issues:

Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b-frame-sequence:
                fail       -> PASS       (fi-cfl-s3) fdo#103481

fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:429s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:441s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:381s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:539s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:296s
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:517s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:513s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:522s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:511s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:410s
fi-cfl-s3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:559s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:520s
fi-cnl-y3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:590s
fi-elk-e7500     total:284  pass:224  dwarn:1   dfail:0   fail:0   skip:58 
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:319s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:540s
fi-hsw-4770      total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:405s
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:423s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:463s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:435s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:472s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:464s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:507s
fi-pnv-d510      total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  time:659s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:439s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:531s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:503s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:505s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:432s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:445s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:398s
Blacklisted hosts:
fi-cnl-psr       total:285  pass:248  dwarn:11  dfail:0   fail:0   skip:26  time:524s
fi-glk-j4005     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:486s

d6e43ca115e525e6d53539be28100d2ee0958655 drm-tip: 2018y-03m-29d-12h-46m-03s UTC integration manifest
1689ed7a8137 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
5b5140ece582 drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8536/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev7)

[Patchwork]

== Series Details ==

Series: series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev7)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

Series 40503v7 series starting with [v6,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/7/mbox/

---- Possible new issues:

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> INCOMPLETE (fi-bxt-j4205)

---- Known issues:

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> INCOMPLETE (fi-skl-6700k2) fdo#104108
Test prime_vgem:
        Subgroup basic-fence-flip:
                fail       -> PASS       (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:435s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:441s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:387s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:532s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:296s
fi-bxt-j4205     total:242  pass:216  dwarn:0   dfail:0   fail:0   skip:25 
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:517s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:507s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:413s
fi-cfl-s3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:558s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:513s
fi-cnl-y3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:583s
fi-elk-e7500     total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  time:422s
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:317s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:536s
fi-hsw-4770      total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:401s
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:419s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:469s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:439s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:476s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:466s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:509s
fi-pnv-d510      total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  time:657s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:438s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:533s
fi-skl-6700k2    total:243  pass:222  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:511s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:430s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:446s
fi-snb-2520m     total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:558s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:408s
Blacklisted hosts:
fi-cnl-psr       total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  time:526s
fi-glk-j4005     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:485s

befd0b655b91ec3977909f136e663dcee41e5c56 drm-tip: 2018y-03m-29d-16h-19m-32s UTC integration manifest
92da09cfa7cd drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
d52cd4564412 drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8538/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for series starting with [v7,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)

[Patchwork]

== Series Details ==

Series: series starting with [v7,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)
URL   : https://patchwork.freedesktop.org/series/40503/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3655:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3657:16: warning: expression using sizeof(void)

Commit: drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [v7,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)

[Patchwork]

== Series Details ==

Series: series starting with [v7,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4058 -> Patchwork_8699 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8699 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8699, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/9/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8699:

  === IGT changes ===

    ==== Warnings ====

    igt@prime_vgem@basic-fence-flip:
      fi-cnl-y3:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_8699 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (35 -> 33) ==

  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4058 -> Patchwork_8699

  CI_DRM_4058: 241d827c86078c4709c00251d22ea8f7554e3e36 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4432: 8b77704db49167f7ebfd1c470d9c129d3b862cb6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8699: 5de6aa2fd60b7d1fd7a67cb846e4352ca40e7473 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4432: 93b35926a150e318439d2505901288594b3548f5 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

5de6aa2fd60b drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
d443c598258a drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8699/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [v7,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)

[Patchwork]

== Series Details ==

Series: series starting with [v7,1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4058_full -> Patchwork_8699_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8699_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8699_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/9/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8699_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render:
      shard-kbl:          PASS -> SKIP

    igt@gem_mocs_settings@mocs-rc6-ctx-render:
      shard-kbl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_8699_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      shard-hsw:          PASS -> FAIL (fdo#103928)

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-hsw:          PASS -> DMESG-WARN (fdo#102614) +1

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-hsw:          FAIL (fdo#105189) -> PASS

    igt@kms_flip@blocking-wf_vblank:
      shard-hsw:          FAIL (fdo#103928) -> PASS

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 4) ==

  Missing    (2): shard-glk shard-glkb 


== Build changes ==

    * Linux: CI_DRM_4058 -> Patchwork_8699

  CI_DRM_4058: 241d827c86078c4709c00251d22ea8f7554e3e36 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4432: 8b77704db49167f7ebfd1c470d9c129d3b862cb6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8699: 5de6aa2fd60b7d1fd7a67cb846e4352ca40e7473 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4432: 93b35926a150e318439d2505901288594b3548f5 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8699/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11)

[Patchwork]

== Series Details ==

Series: series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4059 -> Patchwork_8713 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8713 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8713, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/11/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8713:

  === IGT changes ===

    ==== Warnings ====

    igt@core_auth@basic-auth:
      fi-kbl-r:           PASS -> NOTRUN +257

    igt@drv_getparams_basic@basic-subslice-total:
      fi-snb-2600:        PASS -> NOTRUN +244

    igt@drv_hangman@error-state-basic:
      fi-elk-e7500:       PASS -> NOTRUN +181

    igt@gem_busy@basic-busy-default:
      fi-glk-j4005:       PASS -> NOTRUN +255

    igt@gem_close_race@basic-process:
      fi-ivb-3770:        PASS -> NOTRUN +251

    igt@gem_ctx_param@basic:
      fi-gdg-551:         SKIP -> NOTRUN +107

    igt@gem_exec_basic@basic-bsd1:
      fi-cfl-u:           SKIP -> NOTRUN +25

    igt@gem_exec_basic@basic-vebox:
      fi-ivb-3770:        SKIP -> NOTRUN +32

    igt@gem_exec_basic@gtt-bsd:
      fi-bwr-2160:        SKIP -> NOTRUN +104

    igt@gem_exec_basic@gtt-bsd2:
      fi-kbl-7500u:       SKIP -> NOTRUN +23
      fi-cnl-y3:          SKIP -> NOTRUN +25

    igt@gem_exec_basic@readonly-bsd:
      fi-pnv-d510:        SKIP -> NOTRUN +63

    igt@gem_exec_basic@readonly-bsd1:
      fi-snb-2520m:       SKIP -> NOTRUN +39

    igt@gem_exec_flush@basic-batch-kernel-default-cmd:
      fi-bxt-dsi:         SKIP -> NOTRUN +29

    igt@gem_exec_flush@basic-batch-kernel-default-wb:
      fi-kbl-7567u:       PASS -> NOTRUN +264

    igt@gem_exec_flush@basic-uc-rw-default:
      fi-byt-j1900:       PASS -> NOTRUN +249

    igt@gem_exec_gttfill@basic:
      fi-skl-gvtdvm:      SKIP -> NOTRUN +22

    igt@gem_exec_reloc@basic-cpu-active:
      fi-bsw-n3050:       PASS -> NOTRUN +238

    igt@gem_exec_reloc@basic-write-cpu-noreloc:
      fi-skl-6770hq:      PASS -> NOTRUN +264

    igt@gem_exec_reloc@basic-write-gtt-noreloc:
      fi-ivb-3520m:       PASS -> NOTRUN +253

    igt@gem_exec_store@basic-bsd1:
      fi-kbl-r:           SKIP -> NOTRUN +26

    igt@gem_exec_store@basic-bsd2:
      fi-hsw-4770:        SKIP -> NOTRUN +26

    igt@gem_flink_basic@basic:
      fi-gdg-551:         PASS -> NOTRUN +175

    igt@gem_mmap@basic-small-bo:
      fi-skl-gvtdvm:      PASS -> NOTRUN +261

    igt@gem_mmap_gtt@basic-read:
      fi-cnl-y3:          PASS -> NOTRUN +258

    igt@gem_mmap_gtt@basic-read-write-distinct:
      fi-hsw-4770:        PASS -> NOTRUN +257

    igt@gem_mmap_gtt@basic-small-bo:
      fi-kbl-7500u:       PASS -> NOTRUN +259

    igt@gem_mmap_gtt@basic-wc:
      fi-pnv-d510:        PASS -> NOTRUN +219

    igt@gem_mmap_gtt@basic-write:
      fi-cfl-8700k:       PASS -> NOTRUN +256

    igt@gem_mmap_gtt@basic-write-gtt:
      fi-blb-e6850:       PASS -> NOTRUN +219

    igt@gem_ringfill@basic-default-fd:
      fi-elk-e7500:       SKIP -> NOTRUN +46

    igt@gem_sync@basic-store-all:
      fi-byt-n2820:       PASS -> NOTRUN +245

    igt@gem_wait@basic-await-all:
      fi-glk-1:           PASS -> NOTRUN +256

    igt@gem_workarounds@basic-read:
      fi-snb-2600:        SKIP -> NOTRUN +39

    igt@gvt_basic@invalid-placeholder-test:
      fi-skl-6260u:       SKIP -> NOTRUN +19

    igt@kms_addfb_basic@addfb25-bad-modifier:
      fi-bdw-gvtdvm:      PASS -> NOTRUN +260

    igt@kms_addfb_basic@too-high:
      fi-bwr-2160:        PASS -> NOTRUN +179

    igt@kms_addfb_basic@unused-modifier:
      fi-bdw-5557u:       PASS -> NOTRUN +263

    igt@kms_chamelium@common-hpd-after-suspend:
      fi-ivb-3520m:       SKIP -> NOTRUN +28

    igt@kms_chamelium@dp-crc-fast:
      fi-skl-guc:         SKIP -> NOTRUN +27

    igt@kms_chamelium@dp-edid-read:
      fi-skl-6770hq:      SKIP -> NOTRUN +19
      fi-byt-n2820:       SKIP -> NOTRUN +38

    igt@kms_chamelium@dp-hpd-fast:
      fi-ilk-650:         SKIP -> NOTRUN +59

    igt@kms_chamelium@hdmi-crc-fast:
      fi-cfl-s3:          SKIP -> NOTRUN +25
      fi-bsw-n3050:       SKIP -> NOTRUN +45
      fi-byt-j1900:       SKIP -> NOTRUN +34

    igt@kms_chamelium@hdmi-edid-read:
      fi-glk-1:           SKIP -> NOTRUN +27
      fi-blb-e6850:       SKIP -> NOTRUN +63

    igt@kms_chamelium@vga-edid-read:
      fi-cfl-8700k:       SKIP -> NOTRUN +27
      fi-skl-6600u:       SKIP -> NOTRUN +26

    igt@kms_flip@basic-flip-vs-dpms:
      fi-ilk-650:         PASS -> NOTRUN +224

    igt@kms_flip@basic-plain-flip:
      fi-bxt-j4205:       PASS -> NOTRUN +255

    igt@kms_force_connector_basic@force-connector-state:
      fi-kbl-7567u:       SKIP -> NOTRUN +19

    igt@kms_force_connector_basic@prune-stale-modes:
      fi-glk-j4005:       SKIP -> NOTRUN +28
      fi-skl-6700k2:      SKIP -> NOTRUN +23

    igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
      fi-skl-6600u:       PASS -> NOTRUN +257

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       PASS -> NOTRUN +244

    igt@kms_sink_crc_basic:
      fi-bdw-gvtdvm:      SKIP -> NOTRUN +23

    igt@pm_backlight@basic-brightness:
      fi-bxt-j4205:       SKIP -> NOTRUN +28
      fi-bdw-5557u:       SKIP -> NOTRUN +20

    igt@pm_rpm@basic-rte:
      fi-skl-6260u:       PASS -> NOTRUN +264

    igt@prime_self_import@basic-llseek-bad:
      fi-skl-guc:         PASS -> NOTRUN +256

    igt@prime_self_import@basic-with_two_bos:
      fi-bxt-dsi:         PASS -> NOTRUN +254

    igt@prime_vgem@basic-busy-default:
      fi-cfl-u:           PASS -> NOTRUN +258

    igt@vgem_basic@create:
      fi-cfl-s3:          PASS -> NOTRUN +258

    igt@vgem_basic@mmap:
      fi-skl-6700k2:      PASS -> NOTRUN +260

    
== Known issues ==

  Here are the changes found in Patchwork_8713 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> NOTRUN +1

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         FAIL (fdo#102575) -> NOTRUN

    igt@gem_ringfill@basic-default-hang:
      fi-pnv-d510:        DMESG-WARN (fdo#101600) -> NOTRUN
      fi-blb-e6850:       DMESG-WARN (fdo#101600) -> NOTRUN

    igt@kms_chamelium@common-hpd-after-suspend:
      fi-kbl-7500u:       DMESG-WARN (fdo#102505) -> NOTRUN

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-elk-e7500:       INCOMPLETE (fdo#103989) -> NOTRUN

    
  fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
  fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (36 -> 33) ==

  Missing    (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4059 -> Patchwork_8713

  CI_DRM_4059: c1645edc253f2b52a8c94565a75b479a6782e75f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4435: ddbe5a4d8bb1780ecf07f72e815062d3bce8ff71 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8713: df4e21623c2821d6d8f7257c2c2ade9c779ad5eb @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4435: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

df4e21623c28 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
41c1206d1dc6 drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8713/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11)

[Patchwork]

== Series Details ==

Series: series starting with [v8,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev11)
URL   : https://patchwork.freedesktop.org/series/40503/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4059_full -> Patchwork_8713_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8713_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8713_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/11/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8713_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_busy@extended-parallel-bsd1:
      shard-hsw:          SKIP -> NOTRUN +890

    igt@gem_exec_params@dr1-dirt:
      shard-kbl:          PASS -> NOTRUN +1940

    igt@gem_pread@stolen-uncached:
      shard-kbl:          SKIP -> NOTRUN +700

    igt@gem_pwrite@display:
      shard-snb:          PASS -> NOTRUN +1377

    igt@kms_chv_cursor_fail@pipe-b-256x256-top-edge:
      shard-hsw:          PASS -> NOTRUN +1783

    igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
      shard-apl:          PASS -> NOTRUN +1834

    igt@perf_pmu@busy-start-vcs1:
      shard-snb:          SKIP -> NOTRUN +1298

    igt@prime_vgem@sync-bsd1:
      shard-apl:          SKIP -> NOTRUN +835

    
== Known issues ==

  Here are the changes found in Patchwork_8713_full that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@drv_selftest@mock_breadcrumbs:
      shard-hsw:          DMESG-FAIL (fdo#106085) -> NOTRUN
      shard-snb:          DMESG-FAIL (fdo#106085) -> NOTRUN
      shard-apl:          DMESG-FAIL (fdo#106085) -> NOTRUN
      shard-kbl:          DMESG-FAIL (fdo#106085) -> NOTRUN

    igt@drv_selftest@mock_scatterlist:
      shard-hsw:          DMESG-WARN (fdo#103667) -> NOTRUN
      shard-kbl:          DMESG-WARN (fdo#103667) -> NOTRUN
      shard-snb:          DMESG-WARN (fdo#103667) -> NOTRUN
      shard-apl:          DMESG-WARN (fdo#103667) -> NOTRUN

    igt@gem_ctx_isolation@vcs0-s3:
      shard-kbl:          INCOMPLETE (fdo#103665) -> NOTRUN

    igt@gem_exec_schedule@pi-ringfull-blt:
      shard-apl:          FAIL (fdo#103158) -> NOTRUN +3

    igt@gem_exec_schedule@pi-ringfull-bsd1:
      shard-kbl:          FAIL (fdo#103158) -> NOTRUN +4

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-hsw:          FAIL (fdo#102887) -> NOTRUN

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-apl:          FAIL (fdo#105363, fdo#102887) -> NOTRUN

    igt@kms_flip@modeset-vs-vblank-race:
      shard-hsw:          FAIL (fdo#103060) -> NOTRUN

    igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
      shard-snb:          FAIL (fdo#103167) -> NOTRUN

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> NOTRUN
      shard-hsw:          FAIL (fdo#99912) -> NOTRUN
      shard-snb:          FAIL (fdo#99912) -> NOTRUN

    igt@kms_sysfs_edid_timing:
      shard-hsw:          WARN (fdo#100047) -> NOTRUN
      shard-kbl:          FAIL (fdo#100047) -> NOTRUN

    igt@prime_vgem@coherency-gtt:
      shard-apl:          FAIL (fdo#100587) -> NOTRUN +1

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#106085 https://bugs.freedesktop.org/show_bug.cgi?id=106085
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 4) ==

  Missing    (2): shard-glk shard-glkb 


== Build changes ==

    * Linux: CI_DRM_4059 -> Patchwork_8713

  CI_DRM_4059: c1645edc253f2b52a8c94565a75b479a6782e75f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4435: ddbe5a4d8bb1780ecf07f72e815062d3bce8ff71 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8713: df4e21623c2821d6d8f7257c2c2ade9c779ad5eb @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4435: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8713/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v9,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev13)

[Patchwork]

== Series Details ==

Series: series starting with [v9,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev13)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4060 -> Patchwork_8715 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8715 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8715, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/13/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8715:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-cfl-u:           PASS -> DMESG-WARN
      fi-cfl-s3:          PASS -> DMESG-WARN
      fi-skl-6260u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-bdw-gvtdvm:      PASS -> DMESG-WARN
      fi-bxt-j4205:       PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-bdw-5557u:       PASS -> DMESG-WARN
      fi-kbl-r:           PASS -> DMESG-WARN
      fi-skl-guc:         PASS -> DMESG-WARN
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-glk-j4005:       PASS -> DMESG-WARN
      fi-skl-6600u:       PASS -> DMESG-WARN
      fi-bxt-dsi:         PASS -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN
      fi-bsw-n3050:       PASS -> DMESG-WARN
      fi-skl-6700k2:      PASS -> DMESG-WARN
      fi-skl-6770hq:      PASS -> DMESG-WARN

    igt@gem_ringfill@basic-default-hang:
      fi-cnl-y3:          PASS -> DMESG-WARN

    
    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_8715 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-skl-6770hq:      PASS -> FAIL (fdo#103481)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106097) +3

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-glk-j4005:       DMESG-WARN (fdo#106097) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS +1

    
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097


== Participating hosts (34 -> 32) ==

  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4060 -> Patchwork_8715

  CI_DRM_4060: 17148956c3830de3194c17693be76f85f05f692f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4441: 83ba5b7d3bde48b383df41792fc9c955a5a23bdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8715: 786bd5413210f9b90832be6184f27966545169ed @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4441: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

786bd5413210 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
a23646d90d7c drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8715/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v9,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev13)

[Patchwork]

== Series Details ==

Series: series starting with [v9,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev13)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4063 -> Patchwork_8724 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8724 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8724, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/13/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8724:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-cfl-u:           PASS -> DMESG-WARN
      fi-cfl-s3:          PASS -> DMESG-WARN
      fi-skl-6260u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-bdw-gvtdvm:      PASS -> DMESG-WARN
      fi-bxt-j4205:       PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-bdw-5557u:       PASS -> DMESG-WARN
      fi-kbl-r:           PASS -> DMESG-WARN
      fi-skl-guc:         PASS -> DMESG-WARN
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-glk-j4005:       PASS -> DMESG-WARN
      fi-skl-6600u:       PASS -> DMESG-WARN
      fi-bxt-dsi:         NOTRUN -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN
      fi-bsw-n3050:       PASS -> DMESG-WARN
      fi-skl-6700k2:      PASS -> DMESG-WARN
      fi-skl-6770hq:      PASS -> DMESG-WARN

    igt@gem_ringfill@basic-default-hang:
      fi-cnl-psr:         PASS -> DMESG-WARN
      fi-cnl-y3:          PASS -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_8724 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    igt@prime_vgem@basic-fence-flip:
      fi-ilk-650:         PASS -> FAIL (fdo#104008)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (34 -> 33) ==

  Additional (1): fi-bxt-dsi 
  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4063 -> Patchwork_8724

  CI_DRM_4063: 9bdf0998d567cbe94f712c8f3e8295fb0446e114 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4441: 83ba5b7d3bde48b383df41792fc9c955a5a23bdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8724: 685ad5887ea208c505a67e866f461bf9eca50e99 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4441: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

685ad5887ea2 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
84cff719abfe drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8724/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15)

[Patchwork]

== Series Details ==

Series: series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15)
URL   : https://patchwork.freedesktop.org/series/40503/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4d91b554a00a drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
-:61: CHECK:LINE_SPACING: Please don't use multiple blank lines
#61: FILE: drivers/gpu/drm/i915/intel_device_info.c:722:
 
+

total: 0 errors, 0 warnings, 1 checks, 91 lines checked
c243c40dcab2 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15)

[Patchwork]

== Series Details ==

Series: series starting with [v10,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev15)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8741 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8741 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8741, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/15/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8741:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-cfl-u:           PASS -> DMESG-WARN
      fi-cfl-s3:          PASS -> DMESG-WARN
      fi-skl-6260u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-bdw-gvtdvm:      PASS -> DMESG-WARN
      fi-bxt-j4205:       PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-bdw-5557u:       PASS -> DMESG-WARN
      fi-kbl-r:           PASS -> DMESG-WARN
      fi-skl-guc:         PASS -> DMESG-WARN
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-glk-j4005:       NOTRUN -> DMESG-WARN
      fi-skl-6600u:       PASS -> DMESG-WARN
      fi-bxt-dsi:         NOTRUN -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN
      fi-bsw-n3050:       PASS -> DMESG-WARN
      fi-skl-6700k2:      PASS -> DMESG-WARN
      fi-skl-6770hq:      PASS -> DMESG-WARN

    igt@gem_ringfill@basic-default-hang:
      fi-cnl-y3:          PASS -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_8741 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084) +1

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (33 -> 31) ==

  Additional (2): fi-glk-j4005 fi-bxt-dsi 
  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-glk-1 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4066 -> Patchwork_8741

  CI_DRM_4066: e1fbca4821d0700551df233285a5c28db09fd0f6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4441: 83ba5b7d3bde48b383df41792fc9c955a5a23bdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8741: c243c40dcab2358a6001f5edf03bb78a66f2e8cc @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4441: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

c243c40dcab2 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
4d91b554a00a drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8741/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16)

[Patchwork]

== Series Details ==

Series: series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16)
URL   : https://patchwork.freedesktop.org/series/40503/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0f9b8e8c4c75 drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads
-:63: CHECK:LINE_SPACING: Please don't use multiple blank lines
#63: FILE: drivers/gpu/drm/i915/intel_device_info.c:722:
 
+

total: 0 errors, 0 warnings, 1 checks, 90 lines checked
9960162c61d7 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
-:47: WARNING:BAD_SIGN_OFF: Duplicate signature
#47: 
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

total: 0 errors, 1 warnings, 0 checks, 50 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16)

[Patchwork]

== Series Details ==

Series: series starting with [v11,1/2] drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads (rev16)
URL   : https://patchwork.freedesktop.org/series/40503/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4066 -> Patchwork_8742 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8742 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8742, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/40503/revisions/16/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8742:

  === IGT changes ===

    ==== Possible regressions ====

    igt@debugfs_test@read_all_entries:
      fi-cfl-u:           PASS -> DMESG-WARN
      fi-cfl-s3:          PASS -> DMESG-WARN
      fi-skl-6260u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-bdw-gvtdvm:      PASS -> DMESG-WARN
      fi-bxt-j4205:       PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-bdw-5557u:       PASS -> DMESG-WARN
      fi-kbl-r:           PASS -> DMESG-WARN
      fi-skl-guc:         PASS -> DMESG-WARN
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-glk-j4005:       NOTRUN -> DMESG-WARN
      fi-skl-6600u:       PASS -> DMESG-WARN
      fi-bxt-dsi:         NOTRUN -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN
      fi-bsw-n3050:       PASS -> DMESG-WARN
      fi-skl-6700k2:      PASS -> DMESG-WARN
      fi-skl-6770hq:      PASS -> DMESG-WARN

    igt@gem_ringfill@basic-default-hang:
      fi-cnl-y3:          PASS -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_8742 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-ivb-3520m:       PASS -> DMESG-WARN (fdo#106084)

    
    ==== Possible fixes ====

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         FAIL (fdo#102575) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (33 -> 31) ==

  Additional (2): fi-glk-j4005 fi-bxt-dsi 
  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-glk-1 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4066 -> Patchwork_8742

  CI_DRM_4066: e1fbca4821d0700551df233285a5c28db09fd0f6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4441: 83ba5b7d3bde48b383df41792fc9c955a5a23bdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8742: 9960162c61d7419eb49300fa91164e0f5e32898b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4441: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

9960162c61d7 drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
0f9b8e8c4c75 drm/i915: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8742/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx