* [RESEND 0/4] Update imx7 clocks
@ 2018-03-28 6:46 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: linux-arm-kernel
Resent as a patcheset now.
I sent the initial patches as individual ones,
without specifying the order they need to be applied in.
https://lkml.org/lkml/2018/3/27/535
https://lkml.org/lkml/2018/3/27/536
https://lkml.org/lkml/2018/3/27/539
https://lkml.org/lkml/2018/3/27/542
Anson Huang (2):
clk: imx7d: Correct dram pll type
clk: imx7d: Correct ahb clk parent select
Dong Aisheng (1):
clk: imx7d: Move clks_init_on before any clock operations
Peter Chen (1):
clk: imx7d: Add USB clock information
drivers/clk/imx/clk-imx7d.c | 29 +++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 1/4] clk: imx7d: Add USB clock information
2018-03-28 6:46 ` Abel Vesa
@ 2018-03-28 6:46 ` Abel Vesa
-1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Abel Vesa
From: Peter Chen <peter.chen@freescale.com>
Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
which is the output of USBOTG2 PHY.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 89bfa75..39d110b 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -801,7 +801,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
- clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
+ clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
@@ -867,6 +867,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
+ clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0);
+ clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
+ clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
@@ -892,6 +895,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
/* set uart module clock's parent clock source that must be great then 80MHz */
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
+ /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
+ clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
+ clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
+
imx_register_uart_clocks(uart_clks);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* [RESEND 1/4] clk: imx7d: Add USB clock information
@ 2018-03-28 6:46 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Peter Chen <peter.chen@freescale.com>
Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
which is the output of USBOTG2 PHY.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 89bfa75..39d110b 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -801,7 +801,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
- clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
+ clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
@@ -867,6 +867,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
+ clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0);
+ clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
+ clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
@@ -892,6 +895,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
/* set uart module clock's parent clock source that must be great then 80MHz */
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
+ /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
+ clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
+ clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
+
imx_register_uart_clocks(uart_clks);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [RESEND 1/4] clk: imx7d: Add USB clock information
2018-03-28 6:46 ` Abel Vesa
(?)
@ 2018-04-06 18:20 ` Stephen Boyd
-1 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Abel Vesa
Quoting Abel Vesa (2018-03-27 23:46:35)
> From: Peter Chen <peter.chen@freescale.com>
>
> Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
> which is the output of USBOTG2 PHY.
>
> Signed-off-by: Peter Chen <peter.chen@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 1/4] clk: imx7d: Add USB clock information
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-03-27 23:46:35)
> From: Peter Chen <peter.chen@freescale.com>
>
> Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
> which is the output of USBOTG2 PHY.
>
> Signed-off-by: Peter Chen <peter.chen@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [RESEND 1/4] clk: imx7d: Add USB clock information
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Abel Vesa
Quoting Abel Vesa (2018-03-27 23:46:35)
> From: Peter Chen <peter.chen@freescale.com>
> =
> Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
> which is the output of USBOTG2 PHY.
> =
> Signed-off-by: Peter Chen <peter.chen@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: imx7d: Move clks_init_on before any clock operations
2018-03-28 6:46 ` Abel Vesa
@ 2018-03-28 6:46 ` Abel Vesa
-1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Dong Aisheng, Abel Vesa
From: Dong Aisheng <b29396@freescale.com>
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 89bfa75..9b17805 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
- clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
@@ -886,6 +879,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
+ clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
+
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-28 6:46 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Dong Aisheng <b29396@freescale.com>
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 89bfa75..9b17805 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
- clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
@@ -886,6 +879,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
+ clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
+
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH] clk: imx7d: Move clks_init_on before any clock operations
2018-03-28 6:46 ` Abel Vesa
(?)
@ 2018-03-28 6:51 ` Abel Vesa
-1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:51 UTC (permalink / raw)
To: Fabio Estevam
Cc: linux-arm-kernel, linux-clk, linux-kernel, dl-linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
b29396
On Wed, Mar 28, 2018 at 09:46:36AM +0300, Abel Vesa wrote:
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
>
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
> index 89bfa75..9b17805 100644
> --- a/drivers/clk/imx/clk-imx7d.c
> +++ b/drivers/clk/imx/clk-imx7d.c
> @@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
> clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
> clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
>
> - clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
> -
> clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
> clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
> clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
> @@ -886,6 +879,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
> for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
> clk_prepare_enable(clks[clks_init_on[i]]);
>
> + clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
> +
> /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
> clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
>
> --
> 2.7.4
>
Ignore this one please, mistakenly sent because of sending all the patches from the current folder.
The patchset applies on linux-next/master just fine without this one.
--
^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-28 6:51 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:51 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Mar 28, 2018 at 09:46:36AM +0300, Abel Vesa wrote:
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
>
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
> index 89bfa75..9b17805 100644
> --- a/drivers/clk/imx/clk-imx7d.c
> +++ b/drivers/clk/imx/clk-imx7d.c
> @@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
> clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
> clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
>
> - clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
> -
> clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
> clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
> clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
> @@ -886,6 +879,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
> for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
> clk_prepare_enable(clks[clks_init_on[i]]);
>
> + clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
> +
> /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
> clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
>
> --
> 2.7.4
>
Ignore this one please, mistakenly sent because of sending all the patches from the current folder.
The patchset applies on linux-next/master just fine without this one.
--
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-28 6:51 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:51 UTC (permalink / raw)
To: Fabio Estevam
Cc: linux-arm-kernel, linux-clk, linux-kernel, dl-linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
b29396
On Wed, Mar 28, 2018 at 09:46:36AM +0300, Abel Vesa wrote:
> From: Dong Aisheng <b29396@freescale.com>
>=20
> For init on clocks we should move it at the first place in imx7d_clocks_i=
nit()
> before any clock operations, else the clock operation may fail in case th=
e clock
> is still not on.
>=20
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>=20
> diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
> index 89bfa75..9b17805 100644
> --- a/drivers/clk/imx/clk-imx7d.c
> +++ b/drivers/clk/imx/clk-imx7d.c
> @@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_n=
ode *ccm_node)
> clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] =3D imx_clk_mux_flags("pll_audio_main=
_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_by=
pass_sel), CLK_SET_RATE_PARENT);
> clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] =3D imx_clk_mux_flags("pll_video_main=
_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_b=
ypass_sel), CLK_SET_RATE_PARENT);
> =20
> - clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN=
]);
> - clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MA=
IN]);
> - clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN=
]);
> - clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MA=
IN]);
> - clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_=
MAIN]);
> - clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_=
MAIN]);
> -
> clks[IMX7D_PLL_ARM_MAIN_CLK] =3D imx_clk_gate("pll_arm_main_clk", "pll_=
arm_main_bypass", base + 0x60, 13);
> clks[IMX7D_PLL_DRAM_MAIN_CLK] =3D imx_clk_gate("pll_dram_main_clk", "pl=
l_dram_main_bypass", base + 0x70, 13);
> clks[IMX7D_PLL_SYS_MAIN_CLK] =3D imx_clk_gate("pll_sys_main_clk", "pll_=
sys_main_bypass", base + 0xb0, 13);
> @@ -886,6 +879,13 @@ static void __init imx7d_clocks_init(struct device_n=
ode *ccm_node)
> for (i =3D 0; i < ARRAY_SIZE(clks_init_on); i++)
> clk_prepare_enable(clks[clks_init_on[i]]);
> =20
> + clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN=
]);
> + clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MA=
IN]);
> + clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN=
]);
> + clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MA=
IN]);
> + clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_=
MAIN]);
> + clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_=
MAIN]);
> +
> /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter =
freq */
> clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
> =20
> --=20
> 2.7.4
>=20
Ignore this one please, mistakenly sent because of sending all the patches =
from the current folder.
The patchset applies on linux-next/master just fine without this one.
-- =
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 2/4] clk: imx7d: Correct dram pll type
2018-03-28 6:46 ` Abel Vesa
@ 2018-03-28 6:46 ` Abel Vesa
-1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Anson Huang, Abel Vesa
From: Anson Huang <b20788@freescale.com>
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.
There is a test_div placed before DRAM PLL's gate, so
add this test div clk.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 39d110b..1cc485f 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -441,11 +441,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
- clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
+ clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
+ clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass",
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* [RESEND 2/4] clk: imx7d: Correct dram pll type
@ 2018-03-28 6:46 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Anson Huang <b20788@freescale.com>
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.
There is a test_div placed before DRAM PLL's gate, so
add this test div clk.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 39d110b..1cc485f 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -441,11 +441,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
- clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
+ clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
+ clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass",
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [RESEND 2/4] clk: imx7d: Correct dram pll type
2018-03-28 6:46 ` Abel Vesa
(?)
@ 2018-04-06 18:20 ` Stephen Boyd
-1 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: Abel Vesa, Abel Vesa, Anson Huang, linux-kernel,
Ranjani Vaidyanathan, linux-imx, Anson Huang, Daniel Baluta,
linux-clk, linux-arm-kernel
Quoting Abel Vesa (2018-03-27 23:46:37)
> From: Anson Huang <b20788@freescale.com>
>
> DRAM PLL is a audio/video type PLL, need to correct
> it to get correct ops of PLL.
>
> There is a test_div placed before DRAM PLL's gate, so
> add this test div clk.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 2/4] clk: imx7d: Correct dram pll type
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-03-27 23:46:37)
> From: Anson Huang <b20788@freescale.com>
>
> DRAM PLL is a audio/video type PLL, need to correct
> it to get correct ops of PLL.
>
> There is a test_div placed before DRAM PLL's gate, so
> add this test div clk.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [RESEND 2/4] clk: imx7d: Correct dram pll type
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: Abel Vesa, Abel Vesa, Anson Huang, linux-kernel,
Ranjani Vaidyanathan, linux-imx, Anson Huang, Daniel Baluta,
linux-clk, linux-arm-kernel
Quoting Abel Vesa (2018-03-27 23:46:37)
> From: Anson Huang <b20788@freescale.com>
> =
> DRAM PLL is a audio/video type PLL, need to correct
> it to get correct ops of PLL.
> =
> There is a test_div placed before DRAM PLL's gate, so
> add this test div clk.
> =
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 3/4] clk: imx7d: Correct ahb clk parent select
2018-03-28 6:46 ` Abel Vesa
@ 2018-03-28 6:46 ` Abel Vesa
-1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Anson Huang, Abel Vesa
From: Anson Huang <b20788@freescale.com>
Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 1cc485f..50da4cb 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -74,7 +74,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
- "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",
+ "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
"pll_video_post_div", };
static const char *dram_phym_sel[] = { "pll_dram_main_clk",
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* [RESEND 3/4] clk: imx7d: Correct ahb clk parent select
@ 2018-03-28 6:46 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Anson Huang <b20788@freescale.com>
Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 1cc485f..50da4cb 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -74,7 +74,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
- "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",
+ "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
"pll_video_post_div", };
static const char *dram_phym_sel[] = { "pll_dram_main_clk",
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [RESEND 3/4] clk: imx7d: Correct ahb clk parent select
2018-03-28 6:46 ` Abel Vesa
(?)
@ 2018-04-06 18:20 ` Stephen Boyd
-1 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Anson Huang, Abel Vesa
Quoting Abel Vesa (2018-03-27 23:46:38)
> From: Anson Huang <b20788@freescale.com>
>
> Design team change the ahb's clk parent options but
> did NOT update the DOC accordingly in time, so the
> AHB/IPG's clk rate in clk tree is incorrect, AHB is
> 67.5MHz and IPG is 33.75MHz, but using scope to
> monitor them, they are actually 135MHz and 67.5MHz,
> update the clk parent option to make clk tree info
> correct.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 3/4] clk: imx7d: Correct ahb clk parent select
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-03-27 23:46:38)
> From: Anson Huang <b20788@freescale.com>
>
> Design team change the ahb's clk parent options but
> did NOT update the DOC accordingly in time, so the
> AHB/IPG's clk rate in clk tree is incorrect, AHB is
> 67.5MHz and IPG is 33.75MHz, but using scope to
> monitor them, they are actually 135MHz and 67.5MHz,
> update the clk parent option to make clk tree info
> correct.
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [RESEND 3/4] clk: imx7d: Correct ahb clk parent select
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Anson Huang, Abel Vesa
Quoting Abel Vesa (2018-03-27 23:46:38)
> From: Anson Huang <b20788@freescale.com>
> =
> Design team change the ahb's clk parent options but
> did NOT update the DOC accordingly in time, so the
> AHB/IPG's clk rate in clk tree is incorrect, AHB is
> 67.5MHz and IPG is 33.75MHz, but using scope to
> monitor them, they are actually 135MHz and 67.5MHz,
> update the clk parent option to make clk tree info
> correct.
> =
> Signed-off-by: Anson Huang <b20788@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 4/4] clk: imx7d: Move clks_init_on before any clock operations
2018-03-28 6:46 ` Abel Vesa
@ 2018-03-28 6:46 ` Abel Vesa
-1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Dong Aisheng, Abel Vesa
From: Dong Aisheng <b29396@freescale.com>
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 50da4cb..975a20d 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
- clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
@@ -891,6 +884,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
+ clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
+
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* [RESEND 4/4] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-28 6:46 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Dong Aisheng <b29396@freescale.com>
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 50da4cb..975a20d 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
- clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
@@ -891,6 +884,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
+ clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
+
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [RESEND 4/4] clk: imx7d: Move clks_init_on before any clock operations
2018-03-28 6:46 ` Abel Vesa
(?)
@ 2018-04-06 18:20 ` Stephen Boyd
-1 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Dong Aisheng, Abel Vesa
Quoting Abel Vesa (2018-03-27 23:46:39)
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
>
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [RESEND 4/4] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-03-27 23:46:39)
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
>
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [RESEND 4/4] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-04-06 18:20 ` Stephen Boyd
0 siblings, 0 replies; 36+ messages in thread
From: Stephen Boyd @ 2018-04-06 18:20 UTC (permalink / raw)
To: Abel Vesa, Fabio Estevam, Irina Tirdea, Michael Turquette,
Peter Chen, Sascha Hauer, Shawn Guo
Cc: linux-arm-kernel, linux-clk, linux-kernel, linux-imx,
Anson Huang, Ranjani Vaidyanathan, Abel Vesa, Daniel Baluta,
Dong Aisheng, Abel Vesa
Quoting Abel Vesa (2018-03-27 23:46:39)
> From: Dong Aisheng <b29396@freescale.com>
> =
> For init on clocks we should move it at the first place in imx7d_clocks_i=
nit()
> before any clock operations, else the clock operation may fail in case th=
e clock
> is still not on.
> =
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-27 14:23 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-27 14:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Dong Aisheng <b29396@freescale.com>
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 89bfa75..9b17805 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
- clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
- clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
@@ -886,6 +879,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
+ clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
+ clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
+
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH] clk: imx7d: Move clks_init_on before any clock operations
2018-03-27 14:23 ` Abel Vesa
@ 2018-03-27 15:08 ` Fabio Estevam
-1 siblings, 0 replies; 36+ messages in thread
From: Fabio Estevam @ 2018-03-27 15:08 UTC (permalink / raw)
To: Abel Vesa
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea, Anson Huang,
linux-kernel, Ranjani Vaidyanathan, NXP Linux Team, Dong Aisheng,
linux-clk,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Abel,
On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
>
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Thanks for your patches.
You sent 4 patches today touching the same file.
Please annotate the sequence of the patches (1/4, 2/4, etc) so that
the maintainer can clearly know the order the patches should be
applied.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-27 15:08 ` Fabio Estevam
0 siblings, 0 replies; 36+ messages in thread
From: Fabio Estevam @ 2018-03-27 15:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi Abel,
On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
>
> Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> Signed-off-by: Dong Aisheng <b29396@freescale.com>
> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Thanks for your patches.
You sent 4 patches today touching the same file.
Please annotate the sequence of the patches (1/4, 2/4, etc) so that
the maintainer can clearly know the order the patches should be
applied.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: imx7d: Move clks_init_on before any clock operations
2018-03-27 15:08 ` Fabio Estevam
(?)
@ 2018-03-28 6:32 ` Abel Vesa
-1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:32 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea, Anson Huang,
linux-kernel, Ranjani Vaidyanathan, dl-linux-imx, b29396,
linux-clk,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Fabio,
On Tue, Mar 27, 2018 at 12:08:39PM -0300, Fabio Estevam wrote:
> Hi Abel,
>
> On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> > From: Dong Aisheng <b29396@freescale.com>
> >
> > For init on clocks we should move it at the first place in imx7d_clocks_init()
> > before any clock operations, else the clock operation may fail in case the clock
> > is still not on.
> >
> > Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> > Signed-off-by: Dong Aisheng <b29396@freescale.com>
> > Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
>
> Thanks for your patches.
>
> You sent 4 patches today touching the same file.
>
> Please annotate the sequence of the patches (1/4, 2/4, etc) so that
> the maintainer can clearly know the order the patches should be
> applied.
Yep, my bad. I'll resend as a patchset now.
--
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-28 6:32 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:32 UTC (permalink / raw)
To: linux-arm-kernel
Hi Fabio,
On Tue, Mar 27, 2018 at 12:08:39PM -0300, Fabio Estevam wrote:
> Hi Abel,
>
> On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> > From: Dong Aisheng <b29396@freescale.com>
> >
> > For init on clocks we should move it at the first place in imx7d_clocks_init()
> > before any clock operations, else the clock operation may fail in case the clock
> > is still not on.
> >
> > Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> > Signed-off-by: Dong Aisheng <b29396@freescale.com>
> > Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
>
> Thanks for your patches.
>
> You sent 4 patches today touching the same file.
>
> Please annotate the sequence of the patches (1/4, 2/4, etc) so that
> the maintainer can clearly know the order the patches should be
> applied.
Yep, my bad. I'll resend as a patchset now.
--
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-28 6:32 ` Abel Vesa
0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2018-03-28 6:32 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea, Anson Huang,
linux-kernel, Ranjani Vaidyanathan, dl-linux-imx, b29396,
linux-clk,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Fabio,
On Tue, Mar 27, 2018 at 12:08:39PM -0300, Fabio Estevam wrote:
> Hi Abel,
>=20
> On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> > From: Dong Aisheng <b29396@freescale.com>
> >
> > For init on clocks we should move it at the first place in imx7d_clocks=
_init()
> > before any clock operations, else the clock operation may fail in case =
the clock
> > is still not on.
> >
> > Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
> > Signed-off-by: Dong Aisheng <b29396@freescale.com>
> > Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
>=20
> Thanks for your patches.
>=20
> You sent 4 patches today touching the same file.
>=20
> Please annotate the sequence of the patches (1/4, 2/4, etc) so that
> the maintainer can clearly know the order the patches should be
> applied.
Yep, my bad. I'll resend as a patchset now.
-- =
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] clk: imx7d: Move clks_init_on before any clock operations
2018-03-27 14:23 ` Abel Vesa
@ 2018-03-28 12:14 ` Fabio Estevam
-1 siblings, 0 replies; 36+ messages in thread
From: Fabio Estevam @ 2018-03-28 12:14 UTC (permalink / raw)
To: Abel Vesa
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Michael Turquette,
Stephen Boyd, Peter Chen, Irina Tirdea, Anson Huang,
linux-kernel, Ranjani Vaidyanathan, NXP Linux Team, Dong Aisheng,
linux-clk,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Abel,
On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
The patch and the commit log does not match.
You are not moving the code block to the "first place" inside
imx7d_clocks_init(), so this is confusing.
Also, why does this need to be done only in the imx7d clock driver?
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] clk: imx7d: Move clks_init_on before any clock operations
@ 2018-03-28 12:14 ` Fabio Estevam
0 siblings, 0 replies; 36+ messages in thread
From: Fabio Estevam @ 2018-03-28 12:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi Abel,
On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> From: Dong Aisheng <b29396@freescale.com>
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the clock
> is still not on.
The patch and the commit log does not match.
You are not moving the code block to the "first place" inside
imx7d_clocks_init(), so this is confusing.
Also, why does this need to be done only in the imx7d clock driver?
^ permalink raw reply [flat|nested] 36+ messages in thread