All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] x86/cpuid: Add missing TLB cpuid values
@ 2018-04-23 16:14 Jacek Tomaka
  2018-04-25  9:00 ` [tip:x86/urgent] x86/cpu/intel: " tip-bot for jacek.tomaka@poczta.fm
  2018-04-26 19:45 ` tip-bot for jacek.tomaka@poczta.fm
  0 siblings, 2 replies; 5+ messages in thread
From: Jacek Tomaka @ 2018-04-23 16:14 UTC (permalink / raw)
  To: Thomas Gleixner, Ingo Molnar, linux-kernel; +Cc: jacek.tomaka

From: jacek.tomaka@poczta.fm

Make kernel print correct message upon boot on Intel Xeon Phi 7210 (and others).

Before:
[ 0.320005] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
After:
[ 0.320005] Last level dTLB entries: 4KB 256, 2MB 128, 4MB 128, 1GB 16

The entries do exist in the official Intel's documentation but the type column there is incorrect (states "Cache" where it should read "TLB")
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2a-manual.html

Signed-off-by: Jacek Tomaka <jacek.tomaka@poczta.fm>
---
 arch/x86/kernel/cpu/intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b9693b80fc21..21e6cc52d56f 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -835,6 +835,9 @@ static const struct _tlb_table intel_tlb_table[] = {
 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
+	{ 0x6b, TLB_DATA_4K, 		256, 	" TLB_DATA 4 KByte pages, 8-way associative" },
+	{ 0x6c, TLB_DATA_2M_4M, 	128, 	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
+	{ 0x6d, TLB_DATA_1G, 		16, 	" TLB_DATA 1 GByte pages, fully associative" },
 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [tip:x86/urgent] x86/cpu/intel: Add missing TLB cpuid values
  2018-04-23 16:14 [PATCH] x86/cpuid: Add missing TLB cpuid values Jacek Tomaka
@ 2018-04-25  9:00 ` tip-bot for jacek.tomaka@poczta.fm
       [not found]   ` <CAKVxXCU4G2JNL1dCh5BH7Sc8WjEOg72_jdt3hCwf5J4LU3Fi6A@mail.gmail.com>
  2018-04-26 19:45 ` tip-bot for jacek.tomaka@poczta.fm
  1 sibling, 1 reply; 5+ messages in thread
From: tip-bot for jacek.tomaka@poczta.fm @ 2018-04-25  9:00 UTC (permalink / raw)
  To: linux-tip-commits; +Cc: tglx, linux-kernel, mingo, hpa, jacek.tomaka

Commit-ID:  88ba3829dfd83219bb2b1954acb0c206a602ce83
Gitweb:     https://git.kernel.org/tip/88ba3829dfd83219bb2b1954acb0c206a602ce83
Author:     jacek.tomaka@poczta.fm <jacek.tomaka@poczta.fm>
AuthorDate: Tue, 24 Apr 2018 00:14:25 +0800
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 25 Apr 2018 10:56:23 +0200

x86/cpu/intel: Add missing TLB cpuid values

Make kernel print the correct number of TLB entries on Intel Xeon Phi 7210
(and others)

Before:
[ 0.320005] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
After:
[ 0.320005] Last level dTLB entries: 4KB 256, 2MB 128, 4MB 128, 1GB 16

The entries do exist in the official Intel SMD but the type column there is
incorrect (states "Cache" where it should read "TLB"), but the entries for
the values 0x6B, 0x6C and 0x6D are correctly described as 'Data TLB'.

Signed-off-by: Jacek Tomaka <jacek.tomaka@poczta.fm>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20180423161425.24366-1-jacekt@dugeo.com

---
 arch/x86/kernel/cpu/intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b9693b80fc21..55b646c43ef6 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -835,6 +835,9 @@ static const struct _tlb_table intel_tlb_table[] = {
 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
+	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
+	{ 0x6c, TLB_DATA_2M_4M,		128	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
+	{ 0x6d, TLB_DATA_1G,		16,	" TLB_DATA 1 GByte pages, fully associative" },
 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [tip:x86/urgent] x86/cpu/intel: Add missing TLB cpuid values
       [not found]   ` <CAKVxXCU4G2JNL1dCh5BH7Sc8WjEOg72_jdt3hCwf5J4LU3Fi6A@mail.gmail.com>
@ 2018-04-26 19:38     ` Thomas Gleixner
  2018-04-26 19:42       ` Thomas Gleixner
  0 siblings, 1 reply; 5+ messages in thread
From: Thomas Gleixner @ 2018-04-26 19:38 UTC (permalink / raw)
  To: Jacek Tomaka; +Cc: linux-tip-commits, linux-kernel, Jacek Tomaka, mingo, hpa

On Fri, 27 Apr 2018, Jacek Tomaka wrote:

> Hi Thomas,
> 
> Looks like the patch has lost a coma after 128.
> +       { 0x6c, TLB_DATA_2M_4M,         128     " TLB_DATA 2 MByte or 4
> MByte pages, 8-way associative" },
> should be :
> +       { 0x6c, TLB_DATA_2M_4M,         128,     " TLB_DATA 2 MByte or 4
> MByte pages, 8-way associative" },
> 
> Do you want me to resend the patch with your updates?

Nah. I fix it up as I fatfingered it when I cleaned up the whitespace
damage.

Thanks,

	tglx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [tip:x86/urgent] x86/cpu/intel: Add missing TLB cpuid values
  2018-04-26 19:38     ` Thomas Gleixner
@ 2018-04-26 19:42       ` Thomas Gleixner
  0 siblings, 0 replies; 5+ messages in thread
From: Thomas Gleixner @ 2018-04-26 19:42 UTC (permalink / raw)
  To: Jacek Tomaka; +Cc: linux-tip-commits, linux-kernel, Jacek Tomaka, mingo, hpa

On Thu, 26 Apr 2018, Thomas Gleixner wrote:
> On Fri, 27 Apr 2018, Jacek Tomaka wrote:
> 
> > Hi Thomas,
> > 
> > Looks like the patch has lost a coma after 128.
> > +       { 0x6c, TLB_DATA_2M_4M,         128     " TLB_DATA 2 MByte or 4
> > MByte pages, 8-way associative" },
> > should be :
> > +       { 0x6c, TLB_DATA_2M_4M,         128,     " TLB_DATA 2 MByte or 4
> > MByte pages, 8-way associative" },
> > 
> > Do you want me to resend the patch with your updates?
> 
> Nah. I fix it up as I fatfingered it when I cleaned up the whitespace
> damage.

As a bonus I enable INTEL support when compiling it.

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [tip:x86/urgent] x86/cpu/intel: Add missing TLB cpuid values
  2018-04-23 16:14 [PATCH] x86/cpuid: Add missing TLB cpuid values Jacek Tomaka
  2018-04-25  9:00 ` [tip:x86/urgent] x86/cpu/intel: " tip-bot for jacek.tomaka@poczta.fm
@ 2018-04-26 19:45 ` tip-bot for jacek.tomaka@poczta.fm
  1 sibling, 0 replies; 5+ messages in thread
From: tip-bot for jacek.tomaka@poczta.fm @ 2018-04-26 19:45 UTC (permalink / raw)
  To: linux-tip-commits; +Cc: linux-kernel, jacek.tomaka, mingo, tglx, hpa

Commit-ID:  b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a
Gitweb:     https://git.kernel.org/tip/b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a
Author:     jacek.tomaka@poczta.fm <jacek.tomaka@poczta.fm>
AuthorDate: Tue, 24 Apr 2018 00:14:25 +0800
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Thu, 26 Apr 2018 21:42:44 +0200

x86/cpu/intel: Add missing TLB cpuid values

Make kernel print the correct number of TLB entries on Intel Xeon Phi 7210
(and others)

Before:
[ 0.320005] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
After:
[ 0.320005] Last level dTLB entries: 4KB 256, 2MB 128, 4MB 128, 1GB 16

The entries do exist in the official Intel SMD but the type column there is
incorrect (states "Cache" where it should read "TLB"), but the entries for
the values 0x6B, 0x6C and 0x6D are correctly described as 'Data TLB'.

Signed-off-by: Jacek Tomaka <jacek.tomaka@poczta.fm>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20180423161425.24366-1-jacekt@dugeo.com
---
 arch/x86/kernel/cpu/intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b9693b80fc21..60d1897041da 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -835,6 +835,9 @@ static const struct _tlb_table intel_tlb_table[] = {
 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
+	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
+	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
+	{ 0x6d, TLB_DATA_1G,		16,	" TLB_DATA 1 GByte pages, fully associative" },
 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-04-26 19:46 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-23 16:14 [PATCH] x86/cpuid: Add missing TLB cpuid values Jacek Tomaka
2018-04-25  9:00 ` [tip:x86/urgent] x86/cpu/intel: " tip-bot for jacek.tomaka@poczta.fm
     [not found]   ` <CAKVxXCU4G2JNL1dCh5BH7Sc8WjEOg72_jdt3hCwf5J4LU3Fi6A@mail.gmail.com>
2018-04-26 19:38     ` Thomas Gleixner
2018-04-26 19:42       ` Thomas Gleixner
2018-04-26 19:45 ` tip-bot for jacek.tomaka@poczta.fm

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.