* [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 13:43 ` Chris Wilson
0 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 13:43 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
In the existing ABI, each engine operates its own timeline
(fence.context) and so should execute independently of any other. If we
install a blocker on all other engines, that should not affect execution
on the local engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
1 file changed, 82 insertions(+), 8 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 5d0f215b2..471275169 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -49,9 +49,9 @@
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
-static void store_dword(int fd, uint32_t ctx, unsigned ring,
- uint32_t target, uint32_t offset, uint32_t value,
- uint32_t cork, unsigned write_domain)
+static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[3];
@@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
batch[++i] = MI_BATCH_BUFFER_END;
gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
gem_execbuf(fd, &execbuf);
- gem_close(fd, obj[2].handle);
+
+ return obj[2].handle;
+}
+
+static void store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
+{
+ gem_close(fd, __store_dword(fd, ctx, ring,
+ target, offset, value,
+ cork, write_domain));
}
static uint32_t create_highest_priority(int fd)
@@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
munmap(ptr, 4096);
}
+static void independent(int fd, unsigned int engine)
+{
+ IGT_CORK_HANDLE(cork);
+ uint32_t scratch, plug, batch;
+ igt_spin_t *spin = NULL;
+ unsigned int other;
+ uint32_t *ptr;
+
+ igt_require(engine != 0);
+
+ scratch = gem_create(fd, 4096);
+ plug = igt_cork_plug(&cork, fd);
+
+ /* Check that we can submit to engine while all others are blocked */
+ for_each_physical_engine(fd, other) {
+ if (other == engine)
+ continue;
+
+ if (spin == NULL) {
+ spin = __igt_spin_batch_new(fd, 0, other, 0);
+ } else {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&obj),
+ .flags = other,
+ };
+ gem_execbuf(fd, &eb);
+ }
+
+ store_dword(fd, 0, other, scratch, 0, other, plug, 0);
+ }
+ igt_require(spin);
+
+ /* Same priority, but different timeline (as different engine) */
+ batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
+
+ unplug_show_queue(fd, &cork, engine);
+ gem_close(fd, plug);
+
+ gem_sync(fd, batch);
+ gem_close(fd, batch);
+ igt_assert(gem_bo_busy(fd, spin->handle));
+
+ ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
+ gem_close(fd, scratch);
+ igt_assert_eq(ptr[0], engine);
+
+ igt_spin_batch_free(fd, spin);
+ gem_quiescent_gpu(fd);
+
+ /* And we expect the others to have overwritten us, order unspecified */
+ igt_assert_neq(ptr[0], engine);
+ munmap(ptr, 4096);
+}
+
static void smoketest(int fd, unsigned ring, unsigned timeout)
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -1070,10 +1138,16 @@ igt_main
if (e->exec_id == 0)
continue;
- igt_subtest_f("fifo-%s", e->name) {
- igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
- igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
- fifo(fd, e->exec_id | e->flags);
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
+ igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
+ }
+
+ igt_subtest_f("fifo-%s", e->name)
+ fifo(fd, e->exec_id | e->flags);
+ igt_subtest_f("independent-%s", e->name)
+ independent(fd, e->exec_id | e->flags);
}
}
}
--
2.17.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 28+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
(?)
@ 2018-04-23 15:32 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2018-04-23 15:32 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: test/gem_exec_schedule: Check each engine is an independent timeline
URL : https://patchwork.freedesktop.org/series/42122/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4078 -> IGTPW_1292 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42122/revisions/1/mbox/
== Known issues ==
Here are the changes found in IGTPW_1292 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: PASS -> DMESG-WARN (fdo#105128)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-ivb-3520m: PASS -> DMESG-WARN (fdo#106084)
==== Possible fixes ====
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-gdg-551: FAIL (fdo#102575) -> PASS
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084
== Participating hosts (36 -> 33) ==
Missing (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq
== Build changes ==
* IGT: IGT_4444 -> IGTPW_1292
CI_DRM_4078: 9391010824b34ec58217f816ba5e314e7312191d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1292: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1292/
IGT_4444: dcc44347494231feabc588c2a76998cbc9afdf8c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4444: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ git://anongit.freedesktop.org/piglit
== Testlist changes ==
+igt@gem_exec_schedule@independent-blt
+igt@gem_exec_schedule@independent-bsd
+igt@gem_exec_schedule@independent-bsd1
+igt@gem_exec_schedule@independent-bsd2
+igt@gem_exec_schedule@independent-render
+igt@gem_exec_schedule@independent-vebox
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1292/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
@ 2018-04-23 15:37 ` Antonio Argenziano
-1 siblings, 0 replies; 28+ messages in thread
From: Antonio Argenziano @ 2018-04-23 15:37 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 23/04/18 06:43, Chris Wilson wrote:
> In the existing ABI, each engine operates its own timeline
> (fence.context) and so should execute independently of any other. If we
> install a blocker on all other engines, that should not affect execution
> on the local engine.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> +static void independent(int fd, unsigned int engine)
> +{
> + IGT_CORK_HANDLE(cork);
> + uint32_t scratch, plug, batch;
> + igt_spin_t *spin = NULL;
> + unsigned int other;
> + uint32_t *ptr;
> +
> + igt_require(engine != 0);
> +
> + scratch = gem_create(fd, 4096);
> + plug = igt_cork_plug(&cork, fd);
> +
> + /* Check that we can submit to engine while all others are blocked */
> + for_each_physical_engine(fd, other) {
> + if (other == engine)
> + continue;
> +
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> +
> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> + }
> + igt_require(spin);
> +
> + /* Same priority, but different timeline (as different engine) */
> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
It would be interesting to check that priority scheduling/preemption is
still happening on the free engine.
> +
> + unplug_show_queue(fd, &cork, engine);
> + gem_close(fd, plug);
> +
> + gem_sync(fd, batch);
> + gem_close(fd, batch);
> + igt_assert(gem_bo_busy(fd, spin->handle));
> +
> + ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
> + gem_close(fd, scratch);
> + igt_assert_eq(ptr[0], engine);
> +
> + igt_spin_batch_free(fd, spin);
> + gem_quiescent_gpu(fd);
> +
> + /* And we expect the others to have overwritten us, order unspecified */
> + igt_assert_neq(ptr[0], engine);
> + munmap(ptr, 4096);
> +}
> +
> static void smoketest(int fd, unsigned ring, unsigned timeout)
> {
> const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
> @@ -1070,10 +1138,16 @@ igt_main
> if (e->exec_id == 0)
> continue;
>
> - igt_subtest_f("fifo-%s", e->name) {
> - igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> - fifo(fd, e->exec_id | e->flags);
> + igt_subtest_group {
> + igt_fixture {
> + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
I thought that we added this to the subtests to have a constant list of
tests for all platforms.
Thanks,
Antonio
> + igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + }
> +
> + igt_subtest_f("fifo-%s", e->name)
> + fifo(fd, e->exec_id | e->flags);
> + igt_subtest_f("independent-%s", e->name)
> + independent(fd, e->exec_id | e->flags);
> }
> }
> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 15:37 ` Antonio Argenziano
0 siblings, 0 replies; 28+ messages in thread
From: Antonio Argenziano @ 2018-04-23 15:37 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
On 23/04/18 06:43, Chris Wilson wrote:
> In the existing ABI, each engine operates its own timeline
> (fence.context) and so should execute independently of any other. If we
> install a blocker on all other engines, that should not affect execution
> on the local engine.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> +static void independent(int fd, unsigned int engine)
> +{
> + IGT_CORK_HANDLE(cork);
> + uint32_t scratch, plug, batch;
> + igt_spin_t *spin = NULL;
> + unsigned int other;
> + uint32_t *ptr;
> +
> + igt_require(engine != 0);
> +
> + scratch = gem_create(fd, 4096);
> + plug = igt_cork_plug(&cork, fd);
> +
> + /* Check that we can submit to engine while all others are blocked */
> + for_each_physical_engine(fd, other) {
> + if (other == engine)
> + continue;
> +
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> +
> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> + }
> + igt_require(spin);
> +
> + /* Same priority, but different timeline (as different engine) */
> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
It would be interesting to check that priority scheduling/preemption is
still happening on the free engine.
> +
> + unplug_show_queue(fd, &cork, engine);
> + gem_close(fd, plug);
> +
> + gem_sync(fd, batch);
> + gem_close(fd, batch);
> + igt_assert(gem_bo_busy(fd, spin->handle));
> +
> + ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
> + gem_close(fd, scratch);
> + igt_assert_eq(ptr[0], engine);
> +
> + igt_spin_batch_free(fd, spin);
> + gem_quiescent_gpu(fd);
> +
> + /* And we expect the others to have overwritten us, order unspecified */
> + igt_assert_neq(ptr[0], engine);
> + munmap(ptr, 4096);
> +}
> +
> static void smoketest(int fd, unsigned ring, unsigned timeout)
> {
> const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
> @@ -1070,10 +1138,16 @@ igt_main
> if (e->exec_id == 0)
> continue;
>
> - igt_subtest_f("fifo-%s", e->name) {
> - igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> - fifo(fd, e->exec_id | e->flags);
> + igt_subtest_group {
> + igt_fixture {
> + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
I thought that we added this to the subtests to have a constant list of
tests for all platforms.
Thanks,
Antonio
> + igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + }
> +
> + igt_subtest_f("fifo-%s", e->name)
> + fifo(fd, e->exec_id | e->flags);
> + igt_subtest_f("independent-%s", e->name)
> + independent(fd, e->exec_id | e->flags);
> }
> }
> }
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 15:37 ` Antonio Argenziano
@ 2018-04-23 15:51 ` Chris Wilson
-1 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 15:51 UTC (permalink / raw)
To: Antonio Argenziano, intel-gfx; +Cc: igt-dev
Quoting Antonio Argenziano (2018-04-23 16:37:17)
>
>
> On 23/04/18 06:43, Chris Wilson wrote:
> > In the existing ABI, each engine operates its own timeline
> > (fence.context) and so should execute independently of any other. If we
> > install a blocker on all other engines, that should not affect execution
> > on the local engine.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> > +static void independent(int fd, unsigned int engine)
> > +{
> > + IGT_CORK_HANDLE(cork);
> > + uint32_t scratch, plug, batch;
> > + igt_spin_t *spin = NULL;
> > + unsigned int other;
> > + uint32_t *ptr;
> > +
> > + igt_require(engine != 0);
> > +
> > + scratch = gem_create(fd, 4096);
> > + plug = igt_cork_plug(&cork, fd);
> > +
> > + /* Check that we can submit to engine while all others are blocked */
> > + for_each_physical_engine(fd, other) {
> > + if (other == engine)
> > + continue;
> > +
> > + if (spin == NULL) {
> > + spin = __igt_spin_batch_new(fd, 0, other, 0);
> > + } else {
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = spin->handle,
> > + };
> > + struct drm_i915_gem_execbuffer2 eb = {
> > + .buffer_count = 1,
> > + .buffers_ptr = to_user_pointer(&obj),
> > + .flags = other,
> > + };
> > + gem_execbuf(fd, &eb);
> > + }
> > +
> > + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> > + }
> > + igt_require(spin);
> > +
> > + /* Same priority, but different timeline (as different engine) */
> > + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
>
> It would be interesting to check that priority scheduling/preemption is
> still happening on the free engine.
It's being run on machines without scheduling as well. Reordering tests
are later; not sure if I care about reordering while blocking, that's an
entirely different set of tests being worked on for queues.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 15:51 ` Chris Wilson
0 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 15:51 UTC (permalink / raw)
To: Antonio Argenziano, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Quoting Antonio Argenziano (2018-04-23 16:37:17)
>
>
> On 23/04/18 06:43, Chris Wilson wrote:
> > In the existing ABI, each engine operates its own timeline
> > (fence.context) and so should execute independently of any other. If we
> > install a blocker on all other engines, that should not affect execution
> > on the local engine.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> > +static void independent(int fd, unsigned int engine)
> > +{
> > + IGT_CORK_HANDLE(cork);
> > + uint32_t scratch, plug, batch;
> > + igt_spin_t *spin = NULL;
> > + unsigned int other;
> > + uint32_t *ptr;
> > +
> > + igt_require(engine != 0);
> > +
> > + scratch = gem_create(fd, 4096);
> > + plug = igt_cork_plug(&cork, fd);
> > +
> > + /* Check that we can submit to engine while all others are blocked */
> > + for_each_physical_engine(fd, other) {
> > + if (other == engine)
> > + continue;
> > +
> > + if (spin == NULL) {
> > + spin = __igt_spin_batch_new(fd, 0, other, 0);
> > + } else {
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = spin->handle,
> > + };
> > + struct drm_i915_gem_execbuffer2 eb = {
> > + .buffer_count = 1,
> > + .buffers_ptr = to_user_pointer(&obj),
> > + .flags = other,
> > + };
> > + gem_execbuf(fd, &eb);
> > + }
> > +
> > + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> > + }
> > + igt_require(spin);
> > +
> > + /* Same priority, but different timeline (as different engine) */
> > + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
>
> It would be interesting to check that priority scheduling/preemption is
> still happening on the free engine.
It's being run on machines without scheduling as well. Reordering tests
are later; not sure if I care about reordering while blocking, that's an
entirely different set of tests being worked on for queues.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 15:51 ` Chris Wilson
@ 2018-04-23 16:00 ` Antonio Argenziano
-1 siblings, 0 replies; 28+ messages in thread
From: Antonio Argenziano @ 2018-04-23 16:00 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 23/04/18 08:51, Chris Wilson wrote:
> Quoting Antonio Argenziano (2018-04-23 16:37:17)
>>
>>
>> On 23/04/18 06:43, Chris Wilson wrote:
>>> In the existing ABI, each engine operates its own timeline
>>> (fence.context) and so should execute independently of any other. If we
>>> install a blocker on all other engines, that should not affect execution
>>> on the local engine.
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>>> +static void independent(int fd, unsigned int engine)
>>> +{
>>> + IGT_CORK_HANDLE(cork);
>>> + uint32_t scratch, plug, batch;
>>> + igt_spin_t *spin = NULL;
>>> + unsigned int other;
>>> + uint32_t *ptr;
>>> +
>>> + igt_require(engine != 0);
>>> +
>>> + scratch = gem_create(fd, 4096);
>>> + plug = igt_cork_plug(&cork, fd);
>>> +
>>> + /* Check that we can submit to engine while all others are blocked */
>>> + for_each_physical_engine(fd, other) {
>>> + if (other == engine)
>>> + continue;
>>> +
>>> + if (spin == NULL) {
>>> + spin = __igt_spin_batch_new(fd, 0, other, 0);
>>> + } else {
>>> + struct drm_i915_gem_exec_object2 obj = {
>>> + .handle = spin->handle,
>>> + };
>>> + struct drm_i915_gem_execbuffer2 eb = {
>>> + .buffer_count = 1,
>>> + .buffers_ptr = to_user_pointer(&obj),
>>> + .flags = other,
>>> + };
>>> + gem_execbuf(fd, &eb);
>>> + }
>>> +
>>> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
>>> + }
>>> + igt_require(spin);
>>> +
>>> + /* Same priority, but different timeline (as different engine) */
>>> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
>>
>> It would be interesting to check that priority scheduling/preemption is
>> still happening on the free engine.
>
> It's being run on machines without scheduling as well. Reordering tests
> are later; not sure if I care about reordering while blocking, that's an
> entirely different set of tests being worked on for queues.
Cool, a different set of tests is what I had in mind as well :).
Oh BTW, with the igt_require in the subtests this is:
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
Thanks,
Antonio
> -Chris
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 16:00 ` Antonio Argenziano
0 siblings, 0 replies; 28+ messages in thread
From: Antonio Argenziano @ 2018-04-23 16:00 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
On 23/04/18 08:51, Chris Wilson wrote:
> Quoting Antonio Argenziano (2018-04-23 16:37:17)
>>
>>
>> On 23/04/18 06:43, Chris Wilson wrote:
>>> In the existing ABI, each engine operates its own timeline
>>> (fence.context) and so should execute independently of any other. If we
>>> install a blocker on all other engines, that should not affect execution
>>> on the local engine.
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>>> +static void independent(int fd, unsigned int engine)
>>> +{
>>> + IGT_CORK_HANDLE(cork);
>>> + uint32_t scratch, plug, batch;
>>> + igt_spin_t *spin = NULL;
>>> + unsigned int other;
>>> + uint32_t *ptr;
>>> +
>>> + igt_require(engine != 0);
>>> +
>>> + scratch = gem_create(fd, 4096);
>>> + plug = igt_cork_plug(&cork, fd);
>>> +
>>> + /* Check that we can submit to engine while all others are blocked */
>>> + for_each_physical_engine(fd, other) {
>>> + if (other == engine)
>>> + continue;
>>> +
>>> + if (spin == NULL) {
>>> + spin = __igt_spin_batch_new(fd, 0, other, 0);
>>> + } else {
>>> + struct drm_i915_gem_exec_object2 obj = {
>>> + .handle = spin->handle,
>>> + };
>>> + struct drm_i915_gem_execbuffer2 eb = {
>>> + .buffer_count = 1,
>>> + .buffers_ptr = to_user_pointer(&obj),
>>> + .flags = other,
>>> + };
>>> + gem_execbuf(fd, &eb);
>>> + }
>>> +
>>> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
>>> + }
>>> + igt_require(spin);
>>> +
>>> + /* Same priority, but different timeline (as different engine) */
>>> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
>>
>> It would be interesting to check that priority scheduling/preemption is
>> still happening on the free engine.
>
> It's being run on machines without scheduling as well. Reordering tests
> are later; not sure if I care about reordering while blocking, that's an
> entirely different set of tests being worked on for queues.
Cool, a different set of tests is what I had in mind as well :).
Oh BTW, with the igt_require in the subtests this is:
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
Thanks,
Antonio
> -Chris
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
@ 2018-04-23 16:52 ` Tvrtko Ursulin
-1 siblings, 0 replies; 28+ messages in thread
From: Tvrtko Ursulin @ 2018-04-23 16:52 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 23/04/2018 14:43, Chris Wilson wrote:
> In the existing ABI, each engine operates its own timeline
> (fence.context) and so should execute independently of any other. If we
> install a blocker on all other engines, that should not affect execution
> on the local engine.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
> 1 file changed, 82 insertions(+), 8 deletions(-)
>
> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> index 5d0f215b2..471275169 100644
> --- a/tests/gem_exec_schedule.c
> +++ b/tests/gem_exec_schedule.c
> @@ -49,9 +49,9 @@
>
> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
>
> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> - uint32_t target, uint32_t offset, uint32_t value,
> - uint32_t cork, unsigned write_domain)
> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> {
> const int gen = intel_gen(intel_get_drm_devid(fd));
> struct drm_i915_gem_exec_object2 obj[3];
> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> batch[++i] = MI_BATCH_BUFFER_END;
> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> gem_execbuf(fd, &execbuf);
> - gem_close(fd, obj[2].handle);
> +
> + return obj[2].handle;
> +}
> +
> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> +{
> + gem_close(fd, __store_dword(fd, ctx, ring,
> + target, offset, value,
> + cork, write_domain));
> }
>
> static uint32_t create_highest_priority(int fd)
> @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
> munmap(ptr, 4096);
> }
>
> +static void independent(int fd, unsigned int engine)
> +{
> + IGT_CORK_HANDLE(cork);
> + uint32_t scratch, plug, batch;
> + igt_spin_t *spin = NULL;
> + unsigned int other;
> + uint32_t *ptr;
> +
> + igt_require(engine != 0);
> +
> + scratch = gem_create(fd, 4096);
> + plug = igt_cork_plug(&cork, fd);
> +
> + /* Check that we can submit to engine while all others are blocked */
> + for_each_physical_engine(fd, other) {
> + if (other == engine)
> + continue;
> +
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> +
> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> + }
> + igt_require(spin);
> +
> + /* Same priority, but different timeline (as different engine) */
> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> +
> + unplug_show_queue(fd, &cork, engine);
> + gem_close(fd, plug);
> +
> + gem_sync(fd, batch);
> + gem_close(fd, batch);
Strictly speaking I think you need to use the poll-able spinner and wait
on it here, before the busy assert. It's unlikely, but spinners on
'other' engines are getting submitted async to the store dword batch on
'engine'.
> + igt_assert(gem_bo_busy(fd, spin->handle));
> +
> + ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
> + gem_close(fd, scratch);
> + igt_assert_eq(ptr[0], engine);
> +
> + igt_spin_batch_free(fd, spin);
> + gem_quiescent_gpu(fd);
> +
> + /* And we expect the others to have overwritten us, order unspecified */
> + igt_assert_neq(ptr[0], engine);
> + munmap(ptr, 4096);
> +}
> +
> static void smoketest(int fd, unsigned ring, unsigned timeout)
> {
> const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
> @@ -1070,10 +1138,16 @@ igt_main
> if (e->exec_id == 0)
> continue;
>
> - igt_subtest_f("fifo-%s", e->name) {
> - igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> - fifo(fd, e->exec_id | e->flags);
> + igt_subtest_group {
> + igt_fixture {
> + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> + igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + }
> +
> + igt_subtest_f("fifo-%s", e->name)
> + fifo(fd, e->exec_id | e->flags);
> + igt_subtest_f("independent-%s", e->name)
> + independent(fd, e->exec_id | e->flags);
> }
> }
> }
>
Apart from what Antonio already commented, and waiting on spinner, looks
OK to me.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 16:52 ` Tvrtko Ursulin
0 siblings, 0 replies; 28+ messages in thread
From: Tvrtko Ursulin @ 2018-04-23 16:52 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
On 23/04/2018 14:43, Chris Wilson wrote:
> In the existing ABI, each engine operates its own timeline
> (fence.context) and so should execute independently of any other. If we
> install a blocker on all other engines, that should not affect execution
> on the local engine.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
> 1 file changed, 82 insertions(+), 8 deletions(-)
>
> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> index 5d0f215b2..471275169 100644
> --- a/tests/gem_exec_schedule.c
> +++ b/tests/gem_exec_schedule.c
> @@ -49,9 +49,9 @@
>
> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
>
> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> - uint32_t target, uint32_t offset, uint32_t value,
> - uint32_t cork, unsigned write_domain)
> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> {
> const int gen = intel_gen(intel_get_drm_devid(fd));
> struct drm_i915_gem_exec_object2 obj[3];
> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> batch[++i] = MI_BATCH_BUFFER_END;
> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> gem_execbuf(fd, &execbuf);
> - gem_close(fd, obj[2].handle);
> +
> + return obj[2].handle;
> +}
> +
> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> +{
> + gem_close(fd, __store_dword(fd, ctx, ring,
> + target, offset, value,
> + cork, write_domain));
> }
>
> static uint32_t create_highest_priority(int fd)
> @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
> munmap(ptr, 4096);
> }
>
> +static void independent(int fd, unsigned int engine)
> +{
> + IGT_CORK_HANDLE(cork);
> + uint32_t scratch, plug, batch;
> + igt_spin_t *spin = NULL;
> + unsigned int other;
> + uint32_t *ptr;
> +
> + igt_require(engine != 0);
> +
> + scratch = gem_create(fd, 4096);
> + plug = igt_cork_plug(&cork, fd);
> +
> + /* Check that we can submit to engine while all others are blocked */
> + for_each_physical_engine(fd, other) {
> + if (other == engine)
> + continue;
> +
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> +
> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> + }
> + igt_require(spin);
> +
> + /* Same priority, but different timeline (as different engine) */
> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> +
> + unplug_show_queue(fd, &cork, engine);
> + gem_close(fd, plug);
> +
> + gem_sync(fd, batch);
> + gem_close(fd, batch);
Strictly speaking I think you need to use the poll-able spinner and wait
on it here, before the busy assert. It's unlikely, but spinners on
'other' engines are getting submitted async to the store dword batch on
'engine'.
> + igt_assert(gem_bo_busy(fd, spin->handle));
> +
> + ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
> + gem_close(fd, scratch);
> + igt_assert_eq(ptr[0], engine);
> +
> + igt_spin_batch_free(fd, spin);
> + gem_quiescent_gpu(fd);
> +
> + /* And we expect the others to have overwritten us, order unspecified */
> + igt_assert_neq(ptr[0], engine);
> + munmap(ptr, 4096);
> +}
> +
> static void smoketest(int fd, unsigned ring, unsigned timeout)
> {
> const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
> @@ -1070,10 +1138,16 @@ igt_main
> if (e->exec_id == 0)
> continue;
>
> - igt_subtest_f("fifo-%s", e->name) {
> - igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> - fifo(fd, e->exec_id | e->flags);
> + igt_subtest_group {
> + igt_fixture {
> + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> + igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + }
> +
> + igt_subtest_f("fifo-%s", e->name)
> + fifo(fd, e->exec_id | e->flags);
> + igt_subtest_f("independent-%s", e->name)
> + independent(fd, e->exec_id | e->flags);
> }
> }
> }
>
Apart from what Antonio already commented, and waiting on spinner, looks
OK to me.
Regards,
Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 16:52 ` Tvrtko Ursulin
@ 2018-04-23 17:08 ` Chris Wilson
-1 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 17:08 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev
Quoting Tvrtko Ursulin (2018-04-23 17:52:54)
>
> On 23/04/2018 14:43, Chris Wilson wrote:
> > In the existing ABI, each engine operates its own timeline
> > (fence.context) and so should execute independently of any other. If we
> > install a blocker on all other engines, that should not affect execution
> > on the local engine.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
> > 1 file changed, 82 insertions(+), 8 deletions(-)
> >
> > diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> > index 5d0f215b2..471275169 100644
> > --- a/tests/gem_exec_schedule.c
> > +++ b/tests/gem_exec_schedule.c
> > @@ -49,9 +49,9 @@
> >
> > IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
> >
> > -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> > - uint32_t target, uint32_t offset, uint32_t value,
> > - uint32_t cork, unsigned write_domain)
> > +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> > + uint32_t target, uint32_t offset, uint32_t value,
> > + uint32_t cork, unsigned write_domain)
> > {
> > const int gen = intel_gen(intel_get_drm_devid(fd));
> > struct drm_i915_gem_exec_object2 obj[3];
> > @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> > batch[++i] = MI_BATCH_BUFFER_END;
> > gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> > gem_execbuf(fd, &execbuf);
> > - gem_close(fd, obj[2].handle);
> > +
> > + return obj[2].handle;
> > +}
> > +
> > +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> > + uint32_t target, uint32_t offset, uint32_t value,
> > + uint32_t cork, unsigned write_domain)
> > +{
> > + gem_close(fd, __store_dword(fd, ctx, ring,
> > + target, offset, value,
> > + cork, write_domain));
> > }
> >
> > static uint32_t create_highest_priority(int fd)
> > @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
> > munmap(ptr, 4096);
> > }
> >
> > +static void independent(int fd, unsigned int engine)
> > +{
> > + IGT_CORK_HANDLE(cork);
> > + uint32_t scratch, plug, batch;
> > + igt_spin_t *spin = NULL;
> > + unsigned int other;
> > + uint32_t *ptr;
> > +
> > + igt_require(engine != 0);
> > +
> > + scratch = gem_create(fd, 4096);
> > + plug = igt_cork_plug(&cork, fd);
> > +
> > + /* Check that we can submit to engine while all others are blocked */
> > + for_each_physical_engine(fd, other) {
> > + if (other == engine)
> > + continue;
> > +
> > + if (spin == NULL) {
> > + spin = __igt_spin_batch_new(fd, 0, other, 0);
> > + } else {
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = spin->handle,
> > + };
> > + struct drm_i915_gem_execbuffer2 eb = {
> > + .buffer_count = 1,
> > + .buffers_ptr = to_user_pointer(&obj),
> > + .flags = other,
> > + };
> > + gem_execbuf(fd, &eb);
> > + }
> > +
> > + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> > + }
> > + igt_require(spin);
> > +
> > + /* Same priority, but different timeline (as different engine) */
> > + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> > +
> > + unplug_show_queue(fd, &cork, engine);
> > + gem_close(fd, plug);
> > +
> > + gem_sync(fd, batch);
> > + gem_close(fd, batch);
>
> Strictly speaking I think you need to use the poll-able spinner and wait
> on it here, before the busy assert. It's unlikely, but spinners on
> 'other' engines are getting submitted async to the store dword batch on
> 'engine'.
We've waited for its completion, so we know batch is idle and the others
are still busy. We then check its seqno is written to the scratch; so
using pollable here is redundant. And then we check that the others are
run after.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [Intel-gfx] [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 17:08 ` Chris Wilson
0 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 17:08 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev
Quoting Tvrtko Ursulin (2018-04-23 17:52:54)
>
> On 23/04/2018 14:43, Chris Wilson wrote:
> > In the existing ABI, each engine operates its own timeline
> > (fence.context) and so should execute independently of any other. If we
> > install a blocker on all other engines, that should not affect execution
> > on the local engine.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
> > 1 file changed, 82 insertions(+), 8 deletions(-)
> >
> > diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> > index 5d0f215b2..471275169 100644
> > --- a/tests/gem_exec_schedule.c
> > +++ b/tests/gem_exec_schedule.c
> > @@ -49,9 +49,9 @@
> >
> > IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
> >
> > -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> > - uint32_t target, uint32_t offset, uint32_t value,
> > - uint32_t cork, unsigned write_domain)
> > +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> > + uint32_t target, uint32_t offset, uint32_t value,
> > + uint32_t cork, unsigned write_domain)
> > {
> > const int gen = intel_gen(intel_get_drm_devid(fd));
> > struct drm_i915_gem_exec_object2 obj[3];
> > @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> > batch[++i] = MI_BATCH_BUFFER_END;
> > gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> > gem_execbuf(fd, &execbuf);
> > - gem_close(fd, obj[2].handle);
> > +
> > + return obj[2].handle;
> > +}
> > +
> > +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> > + uint32_t target, uint32_t offset, uint32_t value,
> > + uint32_t cork, unsigned write_domain)
> > +{
> > + gem_close(fd, __store_dword(fd, ctx, ring,
> > + target, offset, value,
> > + cork, write_domain));
> > }
> >
> > static uint32_t create_highest_priority(int fd)
> > @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
> > munmap(ptr, 4096);
> > }
> >
> > +static void independent(int fd, unsigned int engine)
> > +{
> > + IGT_CORK_HANDLE(cork);
> > + uint32_t scratch, plug, batch;
> > + igt_spin_t *spin = NULL;
> > + unsigned int other;
> > + uint32_t *ptr;
> > +
> > + igt_require(engine != 0);
> > +
> > + scratch = gem_create(fd, 4096);
> > + plug = igt_cork_plug(&cork, fd);
> > +
> > + /* Check that we can submit to engine while all others are blocked */
> > + for_each_physical_engine(fd, other) {
> > + if (other == engine)
> > + continue;
> > +
> > + if (spin == NULL) {
> > + spin = __igt_spin_batch_new(fd, 0, other, 0);
> > + } else {
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = spin->handle,
> > + };
> > + struct drm_i915_gem_execbuffer2 eb = {
> > + .buffer_count = 1,
> > + .buffers_ptr = to_user_pointer(&obj),
> > + .flags = other,
> > + };
> > + gem_execbuf(fd, &eb);
> > + }
> > +
> > + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> > + }
> > + igt_require(spin);
> > +
> > + /* Same priority, but different timeline (as different engine) */
> > + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> > +
> > + unplug_show_queue(fd, &cork, engine);
> > + gem_close(fd, plug);
> > +
> > + gem_sync(fd, batch);
> > + gem_close(fd, batch);
>
> Strictly speaking I think you need to use the poll-able spinner and wait
> on it here, before the busy assert. It's unlikely, but spinners on
> 'other' engines are getting submitted async to the store dword batch on
> 'engine'.
We've waited for its completion, so we know batch is idle and the others
are still busy. We then check its seqno is written to the scratch; so
using pollable here is redundant. And then we check that the others are
run after.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 17:08 ` [Intel-gfx] " Chris Wilson
@ 2018-04-24 8:55 ` Tvrtko Ursulin
-1 siblings, 0 replies; 28+ messages in thread
From: Tvrtko Ursulin @ 2018-04-24 8:55 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 23/04/2018 18:08, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-04-23 17:52:54)
>>
>> On 23/04/2018 14:43, Chris Wilson wrote:
>>> In the existing ABI, each engine operates its own timeline
>>> (fence.context) and so should execute independently of any other. If we
>>> install a blocker on all other engines, that should not affect execution
>>> on the local engine.
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>> tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
>>> 1 file changed, 82 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
>>> index 5d0f215b2..471275169 100644
>>> --- a/tests/gem_exec_schedule.c
>>> +++ b/tests/gem_exec_schedule.c
>>> @@ -49,9 +49,9 @@
>>>
>>> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
>>>
>>> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
>>> - uint32_t target, uint32_t offset, uint32_t value,
>>> - uint32_t cork, unsigned write_domain)
>>> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
>>> + uint32_t target, uint32_t offset, uint32_t value,
>>> + uint32_t cork, unsigned write_domain)
>>> {
>>> const int gen = intel_gen(intel_get_drm_devid(fd));
>>> struct drm_i915_gem_exec_object2 obj[3];
>>> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
>>> batch[++i] = MI_BATCH_BUFFER_END;
>>> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
>>> gem_execbuf(fd, &execbuf);
>>> - gem_close(fd, obj[2].handle);
>>> +
>>> + return obj[2].handle;
>>> +}
>>> +
>>> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
>>> + uint32_t target, uint32_t offset, uint32_t value,
>>> + uint32_t cork, unsigned write_domain)
>>> +{
>>> + gem_close(fd, __store_dword(fd, ctx, ring,
>>> + target, offset, value,
>>> + cork, write_domain));
>>> }
>>>
>>> static uint32_t create_highest_priority(int fd)
>>> @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
>>> munmap(ptr, 4096);
>>> }
>>>
>>> +static void independent(int fd, unsigned int engine)
>>> +{
>>> + IGT_CORK_HANDLE(cork);
>>> + uint32_t scratch, plug, batch;
>>> + igt_spin_t *spin = NULL;
>>> + unsigned int other;
>>> + uint32_t *ptr;
>>> +
>>> + igt_require(engine != 0);
>>> +
>>> + scratch = gem_create(fd, 4096);
>>> + plug = igt_cork_plug(&cork, fd);
>>> +
>>> + /* Check that we can submit to engine while all others are blocked */
>>> + for_each_physical_engine(fd, other) {
>>> + if (other == engine)
>>> + continue;
>>> +
>>> + if (spin == NULL) {
>>> + spin = __igt_spin_batch_new(fd, 0, other, 0);
>>> + } else {
>>> + struct drm_i915_gem_exec_object2 obj = {
>>> + .handle = spin->handle,
>>> + };
>>> + struct drm_i915_gem_execbuffer2 eb = {
>>> + .buffer_count = 1,
>>> + .buffers_ptr = to_user_pointer(&obj),
>>> + .flags = other,
>>> + };
>>> + gem_execbuf(fd, &eb);
>>> + }
>>> +
>>> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
>>> + }
>>> + igt_require(spin);
>>> +
>>> + /* Same priority, but different timeline (as different engine) */
>>> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
>>> +
>>> + unplug_show_queue(fd, &cork, engine);
>>> + gem_close(fd, plug);
>>> +
>>> + gem_sync(fd, batch);
>>> + gem_close(fd, batch);
>>
>> Strictly speaking I think you need to use the poll-able spinner and wait
>> on it here, before the busy assert. It's unlikely, but spinners on
>> 'other' engines are getting submitted async to the store dword batch on
>> 'engine'.
>
> We've waited for its completion, so we know batch is idle and the others
> are still busy. We then check its seqno is written to the scratch; so
> using pollable here is redundant. And then we check that the others are
> run after.
Yeah I was confused, thinking busy check on spinner could return false
if the respective tasklet on those engines hadn't ran yet - but of
course busy is true immediately after execbuf so as I said, total confusion.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-24 8:55 ` Tvrtko Ursulin
0 siblings, 0 replies; 28+ messages in thread
From: Tvrtko Ursulin @ 2018-04-24 8:55 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
On 23/04/2018 18:08, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-04-23 17:52:54)
>>
>> On 23/04/2018 14:43, Chris Wilson wrote:
>>> In the existing ABI, each engine operates its own timeline
>>> (fence.context) and so should execute independently of any other. If we
>>> install a blocker on all other engines, that should not affect execution
>>> on the local engine.
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>> tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
>>> 1 file changed, 82 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
>>> index 5d0f215b2..471275169 100644
>>> --- a/tests/gem_exec_schedule.c
>>> +++ b/tests/gem_exec_schedule.c
>>> @@ -49,9 +49,9 @@
>>>
>>> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
>>>
>>> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
>>> - uint32_t target, uint32_t offset, uint32_t value,
>>> - uint32_t cork, unsigned write_domain)
>>> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
>>> + uint32_t target, uint32_t offset, uint32_t value,
>>> + uint32_t cork, unsigned write_domain)
>>> {
>>> const int gen = intel_gen(intel_get_drm_devid(fd));
>>> struct drm_i915_gem_exec_object2 obj[3];
>>> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
>>> batch[++i] = MI_BATCH_BUFFER_END;
>>> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
>>> gem_execbuf(fd, &execbuf);
>>> - gem_close(fd, obj[2].handle);
>>> +
>>> + return obj[2].handle;
>>> +}
>>> +
>>> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
>>> + uint32_t target, uint32_t offset, uint32_t value,
>>> + uint32_t cork, unsigned write_domain)
>>> +{
>>> + gem_close(fd, __store_dword(fd, ctx, ring,
>>> + target, offset, value,
>>> + cork, write_domain));
>>> }
>>>
>>> static uint32_t create_highest_priority(int fd)
>>> @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
>>> munmap(ptr, 4096);
>>> }
>>>
>>> +static void independent(int fd, unsigned int engine)
>>> +{
>>> + IGT_CORK_HANDLE(cork);
>>> + uint32_t scratch, plug, batch;
>>> + igt_spin_t *spin = NULL;
>>> + unsigned int other;
>>> + uint32_t *ptr;
>>> +
>>> + igt_require(engine != 0);
>>> +
>>> + scratch = gem_create(fd, 4096);
>>> + plug = igt_cork_plug(&cork, fd);
>>> +
>>> + /* Check that we can submit to engine while all others are blocked */
>>> + for_each_physical_engine(fd, other) {
>>> + if (other == engine)
>>> + continue;
>>> +
>>> + if (spin == NULL) {
>>> + spin = __igt_spin_batch_new(fd, 0, other, 0);
>>> + } else {
>>> + struct drm_i915_gem_exec_object2 obj = {
>>> + .handle = spin->handle,
>>> + };
>>> + struct drm_i915_gem_execbuffer2 eb = {
>>> + .buffer_count = 1,
>>> + .buffers_ptr = to_user_pointer(&obj),
>>> + .flags = other,
>>> + };
>>> + gem_execbuf(fd, &eb);
>>> + }
>>> +
>>> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
>>> + }
>>> + igt_require(spin);
>>> +
>>> + /* Same priority, but different timeline (as different engine) */
>>> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
>>> +
>>> + unplug_show_queue(fd, &cork, engine);
>>> + gem_close(fd, plug);
>>> +
>>> + gem_sync(fd, batch);
>>> + gem_close(fd, batch);
>>
>> Strictly speaking I think you need to use the poll-able spinner and wait
>> on it here, before the busy assert. It's unlikely, but spinners on
>> 'other' engines are getting submitted async to the store dword batch on
>> 'engine'.
>
> We've waited for its completion, so we know batch is idle and the others
> are still busy. We then check its seqno is written to the scratch; so
> using pollable here is redundant. And then we check that the others are
> run after.
Yeah I was confused, thinking busy check on spinner could return false
if the respective tasklet on those engines hadn't ran yet - but of
course busy is true immediately after execbuf so as I said, total confusion.
Regards,
Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-24 8:55 ` Tvrtko Ursulin
@ 2018-04-24 9:23 ` Chris Wilson
-1 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-24 9:23 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev
Quoting Tvrtko Ursulin (2018-04-24 09:55:20)
>
> On 23/04/2018 18:08, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-04-23 17:52:54)
> >>
> >> On 23/04/2018 14:43, Chris Wilson wrote:
> >>> In the existing ABI, each engine operates its own timeline
> >>> (fence.context) and so should execute independently of any other. If we
> >>> install a blocker on all other engines, that should not affect execution
> >>> on the local engine.
> >>>
> >>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>> ---
> >>> tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
> >>> 1 file changed, 82 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> >>> index 5d0f215b2..471275169 100644
> >>> --- a/tests/gem_exec_schedule.c
> >>> +++ b/tests/gem_exec_schedule.c
> >>> @@ -49,9 +49,9 @@
> >>>
> >>> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
> >>>
> >>> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> - uint32_t target, uint32_t offset, uint32_t value,
> >>> - uint32_t cork, unsigned write_domain)
> >>> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> + uint32_t target, uint32_t offset, uint32_t value,
> >>> + uint32_t cork, unsigned write_domain)
> >>> {
> >>> const int gen = intel_gen(intel_get_drm_devid(fd));
> >>> struct drm_i915_gem_exec_object2 obj[3];
> >>> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> batch[++i] = MI_BATCH_BUFFER_END;
> >>> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> >>> gem_execbuf(fd, &execbuf);
> >>> - gem_close(fd, obj[2].handle);
> >>> +
> >>> + return obj[2].handle;
> >>> +}
> >>> +
> >>> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> + uint32_t target, uint32_t offset, uint32_t value,
> >>> + uint32_t cork, unsigned write_domain)
> >>> +{
> >>> + gem_close(fd, __store_dword(fd, ctx, ring,
> >>> + target, offset, value,
> >>> + cork, write_domain));
> >>> }
> >>>
> >>> static uint32_t create_highest_priority(int fd)
> >>> @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
> >>> munmap(ptr, 4096);
> >>> }
> >>>
> >>> +static void independent(int fd, unsigned int engine)
> >>> +{
> >>> + IGT_CORK_HANDLE(cork);
> >>> + uint32_t scratch, plug, batch;
> >>> + igt_spin_t *spin = NULL;
> >>> + unsigned int other;
> >>> + uint32_t *ptr;
> >>> +
> >>> + igt_require(engine != 0);
> >>> +
> >>> + scratch = gem_create(fd, 4096);
> >>> + plug = igt_cork_plug(&cork, fd);
> >>> +
> >>> + /* Check that we can submit to engine while all others are blocked */
> >>> + for_each_physical_engine(fd, other) {
> >>> + if (other == engine)
> >>> + continue;
> >>> +
> >>> + if (spin == NULL) {
> >>> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> >>> + } else {
> >>> + struct drm_i915_gem_exec_object2 obj = {
> >>> + .handle = spin->handle,
> >>> + };
> >>> + struct drm_i915_gem_execbuffer2 eb = {
> >>> + .buffer_count = 1,
> >>> + .buffers_ptr = to_user_pointer(&obj),
> >>> + .flags = other,
> >>> + };
> >>> + gem_execbuf(fd, &eb);
> >>> + }
> >>> +
> >>> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> >>> + }
> >>> + igt_require(spin);
> >>> +
> >>> + /* Same priority, but different timeline (as different engine) */
> >>> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> >>> +
> >>> + unplug_show_queue(fd, &cork, engine);
> >>> + gem_close(fd, plug);
> >>> +
> >>> + gem_sync(fd, batch);
> >>> + gem_close(fd, batch);
> >>
> >> Strictly speaking I think you need to use the poll-able spinner and wait
> >> on it here, before the busy assert. It's unlikely, but spinners on
> >> 'other' engines are getting submitted async to the store dword batch on
> >> 'engine'.
> >
> > We've waited for its completion, so we know batch is idle and the others
> > are still busy. We then check its seqno is written to the scratch; so
> > using pollable here is redundant. And then we check that the others are
> > run after.
>
> Yeah I was confused, thinking busy check on spinner could return false
> if the respective tasklet on those engines hadn't ran yet - but of
> course busy is true immediately after execbuf so as I said, total confusion.
So having checked the logic should produce N-1 blocked engines and
ourselves free to complete; care for the r-b so we can add it to the mix
of tests?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [Intel-gfx] [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-24 9:23 ` Chris Wilson
0 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-24 9:23 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: igt-dev
Quoting Tvrtko Ursulin (2018-04-24 09:55:20)
>
> On 23/04/2018 18:08, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-04-23 17:52:54)
> >>
> >> On 23/04/2018 14:43, Chris Wilson wrote:
> >>> In the existing ABI, each engine operates its own timeline
> >>> (fence.context) and so should execute independently of any other. If we
> >>> install a blocker on all other engines, that should not affect execution
> >>> on the local engine.
> >>>
> >>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>> ---
> >>> tests/gem_exec_schedule.c | 90 +++++++++++++++++++++++++++++++++++----
> >>> 1 file changed, 82 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> >>> index 5d0f215b2..471275169 100644
> >>> --- a/tests/gem_exec_schedule.c
> >>> +++ b/tests/gem_exec_schedule.c
> >>> @@ -49,9 +49,9 @@
> >>>
> >>> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
> >>>
> >>> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> - uint32_t target, uint32_t offset, uint32_t value,
> >>> - uint32_t cork, unsigned write_domain)
> >>> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> + uint32_t target, uint32_t offset, uint32_t value,
> >>> + uint32_t cork, unsigned write_domain)
> >>> {
> >>> const int gen = intel_gen(intel_get_drm_devid(fd));
> >>> struct drm_i915_gem_exec_object2 obj[3];
> >>> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> batch[++i] = MI_BATCH_BUFFER_END;
> >>> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> >>> gem_execbuf(fd, &execbuf);
> >>> - gem_close(fd, obj[2].handle);
> >>> +
> >>> + return obj[2].handle;
> >>> +}
> >>> +
> >>> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> >>> + uint32_t target, uint32_t offset, uint32_t value,
> >>> + uint32_t cork, unsigned write_domain)
> >>> +{
> >>> + gem_close(fd, __store_dword(fd, ctx, ring,
> >>> + target, offset, value,
> >>> + cork, write_domain));
> >>> }
> >>>
> >>> static uint32_t create_highest_priority(int fd)
> >>> @@ -161,6 +171,64 @@ static void fifo(int fd, unsigned ring)
> >>> munmap(ptr, 4096);
> >>> }
> >>>
> >>> +static void independent(int fd, unsigned int engine)
> >>> +{
> >>> + IGT_CORK_HANDLE(cork);
> >>> + uint32_t scratch, plug, batch;
> >>> + igt_spin_t *spin = NULL;
> >>> + unsigned int other;
> >>> + uint32_t *ptr;
> >>> +
> >>> + igt_require(engine != 0);
> >>> +
> >>> + scratch = gem_create(fd, 4096);
> >>> + plug = igt_cork_plug(&cork, fd);
> >>> +
> >>> + /* Check that we can submit to engine while all others are blocked */
> >>> + for_each_physical_engine(fd, other) {
> >>> + if (other == engine)
> >>> + continue;
> >>> +
> >>> + if (spin == NULL) {
> >>> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> >>> + } else {
> >>> + struct drm_i915_gem_exec_object2 obj = {
> >>> + .handle = spin->handle,
> >>> + };
> >>> + struct drm_i915_gem_execbuffer2 eb = {
> >>> + .buffer_count = 1,
> >>> + .buffers_ptr = to_user_pointer(&obj),
> >>> + .flags = other,
> >>> + };
> >>> + gem_execbuf(fd, &eb);
> >>> + }
> >>> +
> >>> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> >>> + }
> >>> + igt_require(spin);
> >>> +
> >>> + /* Same priority, but different timeline (as different engine) */
> >>> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> >>> +
> >>> + unplug_show_queue(fd, &cork, engine);
> >>> + gem_close(fd, plug);
> >>> +
> >>> + gem_sync(fd, batch);
> >>> + gem_close(fd, batch);
> >>
> >> Strictly speaking I think you need to use the poll-able spinner and wait
> >> on it here, before the busy assert. It's unlikely, but spinners on
> >> 'other' engines are getting submitted async to the store dword batch on
> >> 'engine'.
> >
> > We've waited for its completion, so we know batch is idle and the others
> > are still busy. We then check its seqno is written to the scratch; so
> > using pollable here is redundant. And then we check that the others are
> > run after.
>
> Yeah I was confused, thinking busy check on spinner could return false
> if the respective tasklet on those engines hadn't ran yet - but of
> course busy is true immediately after execbuf so as I said, total confusion.
So having checked the logic should produce N-1 blocked engines and
ourselves free to complete; care for the r-b so we can add it to the mix
of tests?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
` (3 preceding siblings ...)
(?)
@ 2018-04-23 18:22 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2018-04-23 18:22 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: test/gem_exec_schedule: Check each engine is an independent timeline
URL : https://patchwork.freedesktop.org/series/42122/
State : success
== Summary ==
= CI Bug Log - changes from IGT_4444_full -> IGTPW_1292_full =
== Summary - WARNING ==
Minor unknown changes coming with IGTPW_1292_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_1292_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42122/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in IGTPW_1292_full:
=== IGT changes ===
==== Possible regressions ====
{igt@gem_exec_schedule@independent-blt}:
shard-hsw: NOTRUN -> FAIL +3
{igt@gem_exec_schedule@independent-render}:
shard-snb: NOTRUN -> FAIL +1
==== Warnings ====
igt@gem_mocs_settings@mocs-rc6-blt:
shard-kbl: SKIP -> PASS +1
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: PASS -> SKIP +1
== Known issues ==
Here are the changes found in IGTPW_1292_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_gtt:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023)
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-hsw: PASS -> FAIL (fdo#102887)
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-apl: PASS -> FAIL (fdo#106087)
igt@kms_frontbuffer_tracking@fbc-tilingchange:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_vblank@pipe-c-accuracy-idle:
shard-hsw: PASS -> FAIL (fdo#102583)
==== Possible fixes ====
igt@kms_flip@2x-dpms-vs-vblank-race:
shard-hsw: FAIL (fdo#103060) -> PASS
igt@kms_flip@2x-plain-flip-ts-check-interruptible:
shard-hsw: FAIL (fdo#100368) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
== Participating hosts (5 -> 4) ==
Missing (1): shard-glkb
== Build changes ==
* IGT: IGT_4444 -> IGTPW_1292
* Linux: CI_DRM_4076 -> CI_DRM_4078
CI_DRM_4076: 01b171f6df7b2b55b3c1b851d40741179fa2a722 @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_4078: 9391010824b34ec58217f816ba5e314e7312191d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1292: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1292/
IGT_4444: dcc44347494231feabc588c2a76998cbc9afdf8c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4444: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1292/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH igt v2] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
@ 2018-04-23 20:33 ` Chris Wilson
-1 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 20:33 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In the existing ABI, each engine operates its own timeline
(fence.context) and so should execute independently of any other. If we
install a blocker on all other engines, that should not affect execution
on the local engine.
v2: Move the requirements checks from the fixture to subtest so that
the test list is stable (Antonio)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
---
tests/gem_exec_schedule.c | 89 +++++++++++++++++++++++++++++++++++++--
1 file changed, 85 insertions(+), 4 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 5d0f215b2..8e82f113f 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -49,9 +49,9 @@
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
-static void store_dword(int fd, uint32_t ctx, unsigned ring,
- uint32_t target, uint32_t offset, uint32_t value,
- uint32_t cork, unsigned write_domain)
+static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[3];
@@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
batch[++i] = MI_BATCH_BUFFER_END;
gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
gem_execbuf(fd, &execbuf);
- gem_close(fd, obj[2].handle);
+
+ return obj[2].handle;
+}
+
+static void store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
+{
+ gem_close(fd, __store_dword(fd, ctx, ring,
+ target, offset, value,
+ cork, write_domain));
}
static uint32_t create_highest_priority(int fd)
@@ -161,6 +171,71 @@ static void fifo(int fd, unsigned ring)
munmap(ptr, 4096);
}
+static void independent(int fd, unsigned int engine)
+{
+ IGT_CORK_HANDLE(cork);
+ uint32_t scratch, plug, batch;
+ igt_spin_t *spin = NULL;
+ unsigned int other;
+ uint32_t *ptr;
+
+ igt_require(engine != 0);
+
+ scratch = gem_create(fd, 4096);
+ ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
+ igt_assert_eq(ptr[0], 0);
+
+ plug = igt_cork_plug(&cork, fd);
+
+ /* Check that we can submit to engine while all others are blocked */
+ for_each_physical_engine(fd, other) {
+ if (other == engine)
+ continue;
+
+ if (spin == NULL) {
+ spin = __igt_spin_batch_new(fd, 0, other, 0);
+ } else {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&obj),
+ .flags = other,
+ };
+ gem_execbuf(fd, &eb);
+ }
+
+ store_dword(fd, 0, other, scratch, 0, other, plug, 0);
+ }
+ igt_require(spin);
+
+ /* Same priority, but different timeline (as different engine) */
+ batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
+
+ unplug_show_queue(fd, &cork, engine);
+ gem_close(fd, plug);
+
+ gem_sync(fd, batch);
+ igt_assert(!gem_bo_busy(fd, batch));
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ gem_close(fd, batch);
+
+ /* Only the local engine should be free to complete. */
+ igt_assert(gem_bo_busy(fd, scratch));
+ igt_assert_eq(ptr[0], engine);
+
+ igt_spin_batch_free(fd, spin);
+ gem_quiescent_gpu(fd);
+
+ /* And we expect the others to have overwritten us, order unspecified */
+ igt_assert(!gem_bo_busy(fd, scratch));
+ igt_assert_neq(ptr[0], engine);
+
+ gem_close(fd, scratch);
+ munmap(ptr, 4096);
+}
+
static void smoketest(int fd, unsigned ring, unsigned timeout)
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -1075,6 +1150,12 @@ igt_main
igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
fifo(fd, e->exec_id | e->flags);
}
+
+ igt_subtest_f("independent-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
+ igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
+ independent(fd, e->exec_id | e->flags);
+ }
}
}
--
2.17.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread* [igt-dev] [PATCH igt v2] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 20:33 ` Chris Wilson
0 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 20:33 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
In the existing ABI, each engine operates its own timeline
(fence.context) and so should execute independently of any other. If we
install a blocker on all other engines, that should not affect execution
on the local engine.
v2: Move the requirements checks from the fixture to subtest so that
the test list is stable (Antonio)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
---
tests/gem_exec_schedule.c | 89 +++++++++++++++++++++++++++++++++++++--
1 file changed, 85 insertions(+), 4 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 5d0f215b2..8e82f113f 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -49,9 +49,9 @@
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
-static void store_dword(int fd, uint32_t ctx, unsigned ring,
- uint32_t target, uint32_t offset, uint32_t value,
- uint32_t cork, unsigned write_domain)
+static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[3];
@@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
batch[++i] = MI_BATCH_BUFFER_END;
gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
gem_execbuf(fd, &execbuf);
- gem_close(fd, obj[2].handle);
+
+ return obj[2].handle;
+}
+
+static void store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
+{
+ gem_close(fd, __store_dword(fd, ctx, ring,
+ target, offset, value,
+ cork, write_domain));
}
static uint32_t create_highest_priority(int fd)
@@ -161,6 +171,71 @@ static void fifo(int fd, unsigned ring)
munmap(ptr, 4096);
}
+static void independent(int fd, unsigned int engine)
+{
+ IGT_CORK_HANDLE(cork);
+ uint32_t scratch, plug, batch;
+ igt_spin_t *spin = NULL;
+ unsigned int other;
+ uint32_t *ptr;
+
+ igt_require(engine != 0);
+
+ scratch = gem_create(fd, 4096);
+ ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
+ igt_assert_eq(ptr[0], 0);
+
+ plug = igt_cork_plug(&cork, fd);
+
+ /* Check that we can submit to engine while all others are blocked */
+ for_each_physical_engine(fd, other) {
+ if (other == engine)
+ continue;
+
+ if (spin == NULL) {
+ spin = __igt_spin_batch_new(fd, 0, other, 0);
+ } else {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&obj),
+ .flags = other,
+ };
+ gem_execbuf(fd, &eb);
+ }
+
+ store_dword(fd, 0, other, scratch, 0, other, plug, 0);
+ }
+ igt_require(spin);
+
+ /* Same priority, but different timeline (as different engine) */
+ batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
+
+ unplug_show_queue(fd, &cork, engine);
+ gem_close(fd, plug);
+
+ gem_sync(fd, batch);
+ igt_assert(!gem_bo_busy(fd, batch));
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ gem_close(fd, batch);
+
+ /* Only the local engine should be free to complete. */
+ igt_assert(gem_bo_busy(fd, scratch));
+ igt_assert_eq(ptr[0], engine);
+
+ igt_spin_batch_free(fd, spin);
+ gem_quiescent_gpu(fd);
+
+ /* And we expect the others to have overwritten us, order unspecified */
+ igt_assert(!gem_bo_busy(fd, scratch));
+ igt_assert_neq(ptr[0], engine);
+
+ gem_close(fd, scratch);
+ munmap(ptr, 4096);
+}
+
static void smoketest(int fd, unsigned ring, unsigned timeout)
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -1075,6 +1150,12 @@ igt_main
igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
fifo(fd, e->exec_id | e->flags);
}
+
+ igt_subtest_f("independent-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
+ igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
+ independent(fd, e->exec_id | e->flags);
+ }
}
}
--
2.17.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 20:33 ` [igt-dev] " Chris Wilson
@ 2018-04-23 23:16 ` Chris Wilson
-1 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 23:16 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In the existing ABI, each engine operates its own timeline
(fence.context) and so should execute independently of any other. If we
install a blocker on all other engines, that should not affect execution
on the local engine.
v2: Move the requirements checks from the fixture to subtest so that
the test list is stable (Antonio)
v3: Protect SNB from the evil MI_STORE_DWORD.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
---
tests/gem_exec_schedule.c | 96 ++++++++++++++++++++++++++++++++++++---
1 file changed, 90 insertions(+), 6 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 5d0f215b2..1f43147f7 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -49,9 +49,9 @@
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
-static void store_dword(int fd, uint32_t ctx, unsigned ring,
- uint32_t target, uint32_t offset, uint32_t value,
- uint32_t cork, unsigned write_domain)
+static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[3];
@@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
batch[++i] = MI_BATCH_BUFFER_END;
gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
gem_execbuf(fd, &execbuf);
- gem_close(fd, obj[2].handle);
+
+ return obj[2].handle;
+}
+
+static void store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
+{
+ gem_close(fd, __store_dword(fd, ctx, ring,
+ target, offset, value,
+ cork, write_domain));
}
static uint32_t create_highest_priority(int fd)
@@ -161,6 +171,74 @@ static void fifo(int fd, unsigned ring)
munmap(ptr, 4096);
}
+static void independent(int fd, unsigned int engine)
+{
+ IGT_CORK_HANDLE(cork);
+ uint32_t scratch, plug, batch;
+ igt_spin_t *spin = NULL;
+ unsigned int other;
+ uint32_t *ptr;
+
+ igt_require(engine != 0);
+
+ scratch = gem_create(fd, 4096);
+ ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
+ igt_assert_eq(ptr[0], 0);
+
+ plug = igt_cork_plug(&cork, fd);
+
+ /* Check that we can submit to engine while all others are blocked */
+ for_each_physical_engine(fd, other) {
+ if (other == engine)
+ continue;
+
+ if (!gem_can_store_dword(fd, other))
+ continue;
+
+ if (spin == NULL) {
+ spin = __igt_spin_batch_new(fd, 0, other, 0);
+ } else {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&obj),
+ .flags = other,
+ };
+ gem_execbuf(fd, &eb);
+ }
+
+ store_dword(fd, 0, other, scratch, 0, other, plug, 0);
+ }
+ igt_require(spin);
+
+ /* Same priority, but different timeline (as different engine) */
+ batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
+
+ unplug_show_queue(fd, &cork, engine);
+ gem_close(fd, plug);
+
+ gem_sync(fd, batch);
+ igt_assert(!gem_bo_busy(fd, batch));
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ gem_close(fd, batch);
+
+ /* Only the local engine should be free to complete. */
+ igt_assert(gem_bo_busy(fd, scratch));
+ igt_assert_eq(ptr[0], engine);
+
+ igt_spin_batch_free(fd, spin);
+ gem_quiescent_gpu(fd);
+
+ /* And we expect the others to have overwritten us, order unspecified */
+ igt_assert(!gem_bo_busy(fd, scratch));
+ igt_assert_neq(ptr[0], engine);
+
+ munmap(ptr, 4096);
+ gem_close(fd, scratch);
+}
+
static void smoketest(int fd, unsigned ring, unsigned timeout)
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -1072,9 +1150,15 @@ igt_main
igt_subtest_f("fifo-%s", e->name) {
igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
- igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
+ igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
fifo(fd, e->exec_id | e->flags);
}
+
+ igt_subtest_f("independent-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
+ igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+ independent(fd, e->exec_id | e->flags);
+ }
}
}
@@ -1094,7 +1178,7 @@ igt_main
igt_subtest_group {
igt_fixture {
igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
- igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
+ igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
}
igt_subtest_f("in-order-%s", e->name)
--
2.17.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread* [igt-dev] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-23 23:16 ` Chris Wilson
0 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2018-04-23 23:16 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
In the existing ABI, each engine operates its own timeline
(fence.context) and so should execute independently of any other. If we
install a blocker on all other engines, that should not affect execution
on the local engine.
v2: Move the requirements checks from the fixture to subtest so that
the test list is stable (Antonio)
v3: Protect SNB from the evil MI_STORE_DWORD.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
---
tests/gem_exec_schedule.c | 96 ++++++++++++++++++++++++++++++++++++---
1 file changed, 90 insertions(+), 6 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 5d0f215b2..1f43147f7 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -49,9 +49,9 @@
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
-static void store_dword(int fd, uint32_t ctx, unsigned ring,
- uint32_t target, uint32_t offset, uint32_t value,
- uint32_t cork, unsigned write_domain)
+static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[3];
@@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
batch[++i] = MI_BATCH_BUFFER_END;
gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
gem_execbuf(fd, &execbuf);
- gem_close(fd, obj[2].handle);
+
+ return obj[2].handle;
+}
+
+static void store_dword(int fd, uint32_t ctx, unsigned ring,
+ uint32_t target, uint32_t offset, uint32_t value,
+ uint32_t cork, unsigned write_domain)
+{
+ gem_close(fd, __store_dword(fd, ctx, ring,
+ target, offset, value,
+ cork, write_domain));
}
static uint32_t create_highest_priority(int fd)
@@ -161,6 +171,74 @@ static void fifo(int fd, unsigned ring)
munmap(ptr, 4096);
}
+static void independent(int fd, unsigned int engine)
+{
+ IGT_CORK_HANDLE(cork);
+ uint32_t scratch, plug, batch;
+ igt_spin_t *spin = NULL;
+ unsigned int other;
+ uint32_t *ptr;
+
+ igt_require(engine != 0);
+
+ scratch = gem_create(fd, 4096);
+ ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
+ igt_assert_eq(ptr[0], 0);
+
+ plug = igt_cork_plug(&cork, fd);
+
+ /* Check that we can submit to engine while all others are blocked */
+ for_each_physical_engine(fd, other) {
+ if (other == engine)
+ continue;
+
+ if (!gem_can_store_dword(fd, other))
+ continue;
+
+ if (spin == NULL) {
+ spin = __igt_spin_batch_new(fd, 0, other, 0);
+ } else {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&obj),
+ .flags = other,
+ };
+ gem_execbuf(fd, &eb);
+ }
+
+ store_dword(fd, 0, other, scratch, 0, other, plug, 0);
+ }
+ igt_require(spin);
+
+ /* Same priority, but different timeline (as different engine) */
+ batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
+
+ unplug_show_queue(fd, &cork, engine);
+ gem_close(fd, plug);
+
+ gem_sync(fd, batch);
+ igt_assert(!gem_bo_busy(fd, batch));
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ gem_close(fd, batch);
+
+ /* Only the local engine should be free to complete. */
+ igt_assert(gem_bo_busy(fd, scratch));
+ igt_assert_eq(ptr[0], engine);
+
+ igt_spin_batch_free(fd, spin);
+ gem_quiescent_gpu(fd);
+
+ /* And we expect the others to have overwritten us, order unspecified */
+ igt_assert(!gem_bo_busy(fd, scratch));
+ igt_assert_neq(ptr[0], engine);
+
+ munmap(ptr, 4096);
+ gem_close(fd, scratch);
+}
+
static void smoketest(int fd, unsigned ring, unsigned timeout)
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -1072,9 +1150,15 @@ igt_main
igt_subtest_f("fifo-%s", e->name) {
igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
- igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
+ igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
fifo(fd, e->exec_id | e->flags);
}
+
+ igt_subtest_f("independent-%s", e->name) {
+ igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
+ igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+ independent(fd, e->exec_id | e->flags);
+ }
}
}
@@ -1094,7 +1178,7 @@ igt_main
igt_subtest_group {
igt_fixture {
igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
- igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
+ igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
}
igt_subtest_f("in-order-%s", e->name)
--
2.17.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
2018-04-23 23:16 ` [igt-dev] " Chris Wilson
@ 2018-04-24 9:29 ` Tvrtko Ursulin
-1 siblings, 0 replies; 28+ messages in thread
From: Tvrtko Ursulin @ 2018-04-24 9:29 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 24/04/2018 00:16, Chris Wilson wrote:
> In the existing ABI, each engine operates its own timeline
> (fence.context) and so should execute independently of any other. If we
> install a blocker on all other engines, that should not affect execution
> on the local engine.
>
> v2: Move the requirements checks from the fixture to subtest so that
> the test list is stable (Antonio)
> v3: Protect SNB from the evil MI_STORE_DWORD.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> ---
> tests/gem_exec_schedule.c | 96 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 90 insertions(+), 6 deletions(-)
>
> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> index 5d0f215b2..1f43147f7 100644
> --- a/tests/gem_exec_schedule.c
> +++ b/tests/gem_exec_schedule.c
> @@ -49,9 +49,9 @@
>
> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
>
> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> - uint32_t target, uint32_t offset, uint32_t value,
> - uint32_t cork, unsigned write_domain)
> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> {
> const int gen = intel_gen(intel_get_drm_devid(fd));
> struct drm_i915_gem_exec_object2 obj[3];
> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> batch[++i] = MI_BATCH_BUFFER_END;
> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> gem_execbuf(fd, &execbuf);
> - gem_close(fd, obj[2].handle);
> +
> + return obj[2].handle;
> +}
> +
> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> +{
> + gem_close(fd, __store_dword(fd, ctx, ring,
> + target, offset, value,
> + cork, write_domain));
> }
>
> static uint32_t create_highest_priority(int fd)
> @@ -161,6 +171,74 @@ static void fifo(int fd, unsigned ring)
> munmap(ptr, 4096);
> }
>
> +static void independent(int fd, unsigned int engine)
> +{
> + IGT_CORK_HANDLE(cork);
> + uint32_t scratch, plug, batch;
> + igt_spin_t *spin = NULL;
> + unsigned int other;
> + uint32_t *ptr;
> +
> + igt_require(engine != 0);
> +
> + scratch = gem_create(fd, 4096);
> + ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
> + igt_assert_eq(ptr[0], 0);
> +
> + plug = igt_cork_plug(&cork, fd);
> +
> + /* Check that we can submit to engine while all others are blocked */
> + for_each_physical_engine(fd, other) {
> + if (other == engine)
> + continue;
> +
> + if (!gem_can_store_dword(fd, other))
> + continue;
> +
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> +
> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> + }
> + igt_require(spin);
> +
> + /* Same priority, but different timeline (as different engine) */
> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> +
> + unplug_show_queue(fd, &cork, engine);
> + gem_close(fd, plug);
> +
> + gem_sync(fd, batch);
> + igt_assert(!gem_bo_busy(fd, batch));
> + igt_assert(gem_bo_busy(fd, spin->handle));
> + gem_close(fd, batch);
> +
> + /* Only the local engine should be free to complete. */
> + igt_assert(gem_bo_busy(fd, scratch));
> + igt_assert_eq(ptr[0], engine);
> +
> + igt_spin_batch_free(fd, spin);
> + gem_quiescent_gpu(fd);
> +
> + /* And we expect the others to have overwritten us, order unspecified */
> + igt_assert(!gem_bo_busy(fd, scratch));
> + igt_assert_neq(ptr[0], engine);
> +
> + munmap(ptr, 4096);
> + gem_close(fd, scratch);
> +}
> +
> static void smoketest(int fd, unsigned ring, unsigned timeout)
> {
> const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
> @@ -1072,9 +1150,15 @@ igt_main
>
> igt_subtest_f("fifo-%s", e->name) {
> igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> fifo(fd, e->exec_id | e->flags);
> }
> +
> + igt_subtest_f("independent-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> + igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> + independent(fd, e->exec_id | e->flags);
> + }
> }
> }
>
> @@ -1094,7 +1178,7 @@ igt_main
> igt_subtest_group {
> igt_fixture {
> igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> }
>
> igt_subtest_f("in-order-%s", e->name)
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [igt-dev] [Intel-gfx] [PATCH igt] test/gem_exec_schedule: Check each engine is an independent timeline
@ 2018-04-24 9:29 ` Tvrtko Ursulin
0 siblings, 0 replies; 28+ messages in thread
From: Tvrtko Ursulin @ 2018-04-24 9:29 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 24/04/2018 00:16, Chris Wilson wrote:
> In the existing ABI, each engine operates its own timeline
> (fence.context) and so should execute independently of any other. If we
> install a blocker on all other engines, that should not affect execution
> on the local engine.
>
> v2: Move the requirements checks from the fixture to subtest so that
> the test list is stable (Antonio)
> v3: Protect SNB from the evil MI_STORE_DWORD.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> ---
> tests/gem_exec_schedule.c | 96 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 90 insertions(+), 6 deletions(-)
>
> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> index 5d0f215b2..1f43147f7 100644
> --- a/tests/gem_exec_schedule.c
> +++ b/tests/gem_exec_schedule.c
> @@ -49,9 +49,9 @@
>
> IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
>
> -static void store_dword(int fd, uint32_t ctx, unsigned ring,
> - uint32_t target, uint32_t offset, uint32_t value,
> - uint32_t cork, unsigned write_domain)
> +static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> {
> const int gen = intel_gen(intel_get_drm_devid(fd));
> struct drm_i915_gem_exec_object2 obj[3];
> @@ -100,7 +100,17 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
> batch[++i] = MI_BATCH_BUFFER_END;
> gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
> gem_execbuf(fd, &execbuf);
> - gem_close(fd, obj[2].handle);
> +
> + return obj[2].handle;
> +}
> +
> +static void store_dword(int fd, uint32_t ctx, unsigned ring,
> + uint32_t target, uint32_t offset, uint32_t value,
> + uint32_t cork, unsigned write_domain)
> +{
> + gem_close(fd, __store_dword(fd, ctx, ring,
> + target, offset, value,
> + cork, write_domain));
> }
>
> static uint32_t create_highest_priority(int fd)
> @@ -161,6 +171,74 @@ static void fifo(int fd, unsigned ring)
> munmap(ptr, 4096);
> }
>
> +static void independent(int fd, unsigned int engine)
> +{
> + IGT_CORK_HANDLE(cork);
> + uint32_t scratch, plug, batch;
> + igt_spin_t *spin = NULL;
> + unsigned int other;
> + uint32_t *ptr;
> +
> + igt_require(engine != 0);
> +
> + scratch = gem_create(fd, 4096);
> + ptr = gem_mmap__gtt(fd, scratch, 4096, PROT_READ);
> + igt_assert_eq(ptr[0], 0);
> +
> + plug = igt_cork_plug(&cork, fd);
> +
> + /* Check that we can submit to engine while all others are blocked */
> + for_each_physical_engine(fd, other) {
> + if (other == engine)
> + continue;
> +
> + if (!gem_can_store_dword(fd, other))
> + continue;
> +
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, 0, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> +
> + store_dword(fd, 0, other, scratch, 0, other, plug, 0);
> + }
> + igt_require(spin);
> +
> + /* Same priority, but different timeline (as different engine) */
> + batch = __store_dword(fd, 0, engine, scratch, 0, engine, plug, 0);
> +
> + unplug_show_queue(fd, &cork, engine);
> + gem_close(fd, plug);
> +
> + gem_sync(fd, batch);
> + igt_assert(!gem_bo_busy(fd, batch));
> + igt_assert(gem_bo_busy(fd, spin->handle));
> + gem_close(fd, batch);
> +
> + /* Only the local engine should be free to complete. */
> + igt_assert(gem_bo_busy(fd, scratch));
> + igt_assert_eq(ptr[0], engine);
> +
> + igt_spin_batch_free(fd, spin);
> + gem_quiescent_gpu(fd);
> +
> + /* And we expect the others to have overwritten us, order unspecified */
> + igt_assert(!gem_bo_busy(fd, scratch));
> + igt_assert_neq(ptr[0], engine);
> +
> + munmap(ptr, 4096);
> + gem_close(fd, scratch);
> +}
> +
> static void smoketest(int fd, unsigned ring, unsigned timeout)
> {
> const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
> @@ -1072,9 +1150,15 @@ igt_main
>
> igt_subtest_f("fifo-%s", e->name) {
> igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> fifo(fd, e->exec_id | e->flags);
> }
> +
> + igt_subtest_f("independent-%s", e->name) {
> + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> + igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> + independent(fd, e->exec_id | e->flags);
> + }
> }
> }
>
> @@ -1094,7 +1178,7 @@ igt_main
> igt_subtest_group {
> igt_fixture {
> igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> - igt_require(gem_can_store_dword(fd, e->exec_id) | e->flags);
> + igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> }
>
> igt_subtest_f("in-order-%s", e->name)
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for test/gem_exec_schedule: Check each engine is an independent timeline (rev2)
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
` (5 preceding siblings ...)
(?)
@ 2018-04-23 21:04 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2018-04-23 21:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: test/gem_exec_schedule: Check each engine is an independent timeline (rev2)
URL : https://patchwork.freedesktop.org/series/42122/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4081 -> IGTPW_1294 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42122/revisions/2/mbox/
== Known issues ==
Here are the changes found in IGTPW_1294 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-cfl-s3: PASS -> FAIL (fdo#103928, fdo#100368)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-cnl-y3: PASS -> DMESG-WARN (fdo#104951)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-ivb-3520m: PASS -> DMESG-WARN (fdo#106084)
fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951)
==== Possible fixes ====
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-gdg-551: FAIL (fdo#102575) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084
== Participating hosts (35 -> 33) ==
Additional (1): fi-glk-j4005
Missing (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq
== Build changes ==
* IGT: IGT_4444 -> IGTPW_1294
CI_DRM_4081: fb7048acaac8ece5ebc53f9b748b76cdcef60fa3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1294: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1294/
IGT_4444: dcc44347494231feabc588c2a76998cbc9afdf8c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4444: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ git://anongit.freedesktop.org/piglit
== Testlist changes ==
+igt@gem_exec_schedule@independent-blt
+igt@gem_exec_schedule@independent-bsd
+igt@gem_exec_schedule@independent-bsd1
+igt@gem_exec_schedule@independent-bsd2
+igt@gem_exec_schedule@independent-render
+igt@gem_exec_schedule@independent-vebox
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1294/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* [igt-dev] ✓ Fi.CI.IGT: success for test/gem_exec_schedule: Check each engine is an independent timeline (rev2)
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
` (6 preceding siblings ...)
(?)
@ 2018-04-23 22:20 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2018-04-23 22:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: test/gem_exec_schedule: Check each engine is an independent timeline (rev2)
URL : https://patchwork.freedesktop.org/series/42122/
State : success
== Summary ==
= CI Bug Log - changes from IGT_4444_full -> IGTPW_1294_full =
== Summary - WARNING ==
Minor unknown changes coming with IGTPW_1294_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_1294_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42122/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in IGTPW_1294_full:
=== IGT changes ===
==== Warnings ====
igt@gem_mocs_settings@mocs-rc6-blt:
shard-kbl: SKIP -> PASS +1
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in IGTPW_1294_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
{igt@gem_exec_schedule@independent-blt}:
shard-snb: NOTRUN -> INCOMPLETE (fdo#105411)
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023)
igt@kms_flip@2x-plain-flip-fb-recreate:
shard-hsw: PASS -> FAIL (fdo#103928)
igt@kms_flip@dpms-vs-vblank-race-interruptible:
shard-hsw: PASS -> FAIL (fdo#103060)
igt@perf@polling:
shard-hsw: PASS -> FAIL (fdo#102252)
==== Possible fixes ====
igt@kms_flip@2x-dpms-vs-vblank-race:
shard-hsw: FAIL (fdo#103060) -> PASS
igt@kms_flip@2x-plain-flip-ts-check-interruptible:
shard-hsw: FAIL (fdo#100368) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
== Participating hosts (5 -> 4) ==
Missing (1): shard-glkb
== Build changes ==
* IGT: IGT_4444 -> IGTPW_1294
* Linux: CI_DRM_4076 -> CI_DRM_4081
CI_DRM_4076: 01b171f6df7b2b55b3c1b851d40741179fa2a722 @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_4081: fb7048acaac8ece5ebc53f9b748b76cdcef60fa3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1294: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1294/
IGT_4444: dcc44347494231feabc588c2a76998cbc9afdf8c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4444: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1294/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for test/gem_exec_schedule: Check each engine is an independent timeline (rev3)
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
` (7 preceding siblings ...)
(?)
@ 2018-04-24 0:30 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2018-04-24 0:30 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: test/gem_exec_schedule: Check each engine is an independent timeline (rev3)
URL : https://patchwork.freedesktop.org/series/42122/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4082 -> IGTPW_1295 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42122/revisions/3/mbox/
== Known issues ==
Here are the changes found in IGTPW_1295 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-gdg-551: PASS -> FAIL (fdo#102575)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-cnl-psr: PASS -> INCOMPLETE (fdo#105086)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)
==== Possible fixes ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086
== Participating hosts (36 -> 33) ==
Missing (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq
== Build changes ==
* IGT: IGT_4444 -> IGTPW_1295
CI_DRM_4082: 0600266ef9b8407e0dc281acb6b754eba8178c91 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1295: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1295/
IGT_4444: dcc44347494231feabc588c2a76998cbc9afdf8c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4444: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ git://anongit.freedesktop.org/piglit
== Testlist changes ==
+igt@gem_exec_schedule@independent-blt
+igt@gem_exec_schedule@independent-bsd
+igt@gem_exec_schedule@independent-bsd1
+igt@gem_exec_schedule@independent-bsd2
+igt@gem_exec_schedule@independent-render
+igt@gem_exec_schedule@independent-vebox
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1295/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread* [igt-dev] ✓ Fi.CI.IGT: success for test/gem_exec_schedule: Check each engine is an independent timeline (rev3)
2018-04-23 13:43 ` [igt-dev] " Chris Wilson
` (8 preceding siblings ...)
(?)
@ 2018-04-24 1:30 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2018-04-24 1:30 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: test/gem_exec_schedule: Check each engine is an independent timeline (rev3)
URL : https://patchwork.freedesktop.org/series/42122/
State : success
== Summary ==
= CI Bug Log - changes from IGT_4444_full -> IGTPW_1295_full =
== Summary - WARNING ==
Minor unknown changes coming with IGTPW_1295_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_1295_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42122/revisions/3/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in IGTPW_1295_full:
=== IGT changes ===
==== Warnings ====
igt@gem_mocs_settings@mocs-rc6-blt:
shard-kbl: SKIP -> PASS +1
== Known issues ==
Here are the changes found in IGTPW_1295_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@modeset-vs-vblank-race-interruptible:
shard-hsw: PASS -> FAIL (fdo#103060)
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-hsw: PASS -> FAIL (fdo#103928)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
igt@kms_rotation_crc@primary-rotation-180:
shard-hsw: PASS -> FAIL (fdo#103925)
igt@kms_vblank@pipe-c-accuracy-idle:
shard-hsw: PASS -> FAIL (fdo#102583)
igt@perf_pmu@interrupts-sync:
shard-apl: PASS -> FAIL (fdo#104485)
igt@perf_pmu@rc6-runtime-pm-long:
shard-kbl: PASS -> FAIL (fdo#105010)
==== Possible fixes ====
igt@kms_flip@2x-dpms-vs-vblank-race:
shard-hsw: FAIL (fdo#103060) -> PASS
igt@kms_flip@2x-plain-flip-ts-check-interruptible:
shard-hsw: FAIL (fdo#100368) -> PASS
igt@kms_setmode@basic:
shard-hsw: FAIL (fdo#99912) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104485 https://bugs.freedesktop.org/show_bug.cgi?id=104485
fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 4) ==
Missing (1): shard-glkb
== Build changes ==
* IGT: IGT_4444 -> IGTPW_1295
* Linux: CI_DRM_4076 -> CI_DRM_4082
CI_DRM_4076: 01b171f6df7b2b55b3c1b851d40741179fa2a722 @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_4082: 0600266ef9b8407e0dc281acb6b754eba8178c91 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1295: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1295/
IGT_4444: dcc44347494231feabc588c2a76998cbc9afdf8c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4444: a2f486679f467cd6e82578384f56d4aabaa8cf2e @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1295/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 28+ messages in thread