* [PATCH] drm/i915/psr: vbt change for psr
@ 2018-05-23 3:05 vathsala nagaraju
2018-05-23 3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: vathsala nagaraju @ 2018-05-23 3:05 UTC (permalink / raw)
To: intel-gfx
Cc: Jani Nikula, Maulik V Vaghela, Dhinakaran Pandiyan, Rodrigo Vivi,
Puthikorn Voravootivat
From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.
There is RCR inplace for GOP team to provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to gen9_bc and version 209+ to unblock google.
Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.
bspec 20131
v2: (Jani and Rodrigo)
move the 165 version check to intel_bios.c
v3: Jani
Move the abstraction to intel_bios.
v4: Jani
Rename tp*_wakeup_time to have "us" suffix.
For values outside range[0-3],default to max 2500us.
Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
Handle option 2 in default condition.
Print oustide range value.
For negetive values default to 2500us.
v6: Jani
Handle default first and then fall through for case 2.
v7: Rodrigo
Apply this change for IS_GEN9_BC and vbt version > 209
v8: Puthik
Add new function vbt_psr_to_us.
v9: Jani
Change to v7 version as it's more readable.
DK
add comment /*fall through*/ after case2.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 8 +++----
drivers/gpu/drm/i915/intel_bios.c | 48 +++++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_psr.c | 39 +++++++++++++++----------------
4 files changed, 72 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380..dcfa791 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1078,8 +1078,8 @@ struct intel_vbt_data {
bool require_aux_wakeup;
int idle_frames;
enum psr_lines_to_wait lines_to_wait;
- int tp1_wakeup_time;
- int tp2_tp3_wakeup_time;
+ int tp1_wakeup_time_us;
+ int tp2_tp3_wakeup_time_us;
} psr;
struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb..513b4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4088,10 +4088,10 @@ enum {
#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */
#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
-#define EDP_PSR2_TP2_TIME_500 (0<<8)
-#define EDP_PSR2_TP2_TIME_100 (1<<8)
-#define EDP_PSR2_TP2_TIME_2500 (2<<8)
-#define EDP_PSR2_TP2_TIME_50 (3<<8)
+#define EDP_PSR2_TP2_TIME_500us (0<<8)
+#define EDP_PSR2_TP2_TIME_100us (1<<8)
+#define EDP_PSR2_TP2_TIME_2500us (2<<8)
+#define EDP_PSR2_TP2_TIME_50us (3<<8)
#define EDP_PSR2_TP2_TIME_MASK (3<<8)
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 54270bd..417f656 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -688,8 +688,52 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
break;
}
- dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
- dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+ /*
+ * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+ * Old decimal value is wake up time in multiples of 100 us.
+ */
+ if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
+ switch (psr_table->tp1_wakeup_time) {
+ case 0:
+ dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+ break;
+ case 1:
+ dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+ break;
+ case 3:
+ dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+ break;
+ default:
+ DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+ psr_table->tp1_wakeup_time);
+ /* fallthrough */
+ case 2:
+ dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+ break;
+ }
+
+ switch (psr_table->tp2_tp3_wakeup_time) {
+ case 0:
+ dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+ break;
+ case 1:
+ dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+ break;
+ case 3:
+ dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+ break;
+ default:
+ DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+ psr_table->tp2_tp3_wakeup_time);
+ /* fallthrough */
+ case 2:
+ dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+ break;
+ }
+ } else {
+ dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+ dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+ }
}
static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2f..d64f039 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
if (dev_priv->psr.link_standby)
val |= EDP_PSR_LINK_STANDBY;
- if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
- val |= EDP_PSR_TP1_TIME_2500us;
- else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
- val |= EDP_PSR_TP1_TIME_500us;
- else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+ if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+ val |= EDP_PSR_TP1_TIME_0us;
+ else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
val |= EDP_PSR_TP1_TIME_100us;
+ else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+ val |= EDP_PSR_TP1_TIME_500us;
else
- val |= EDP_PSR_TP1_TIME_0us;
+ val |= EDP_PSR_TP1_TIME_2500us;
- if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
- val |= EDP_PSR_TP2_TP3_TIME_2500us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
- val |= EDP_PSR_TP2_TP3_TIME_500us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+ if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+ val |= EDP_PSR_TP2_TP3_TIME_0us;
+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR_TP2_TP3_TIME_100us;
+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+ val |= EDP_PSR_TP2_TP3_TIME_500us;
else
- val |= EDP_PSR_TP2_TP3_TIME_0us;
+ val |= EDP_PSR_TP2_TP3_TIME_2500us;
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
- if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
- val |= EDP_PSR2_TP2_TIME_2500;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
- val |= EDP_PSR2_TP2_TIME_500;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
- val |= EDP_PSR2_TP2_TIME_100;
+ if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+ dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+ val |= EDP_PSR2_TP2_TIME_50us;
+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+ val |= EDP_PSR2_TP2_TIME_100us;
+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+ val |= EDP_PSR2_TP2_TIME_500us;
else
- val |= EDP_PSR2_TP2_TIME_50;
+ val |= EDP_PSR2_TP2_TIME_2500us;
I915_WRITE(EDP_PSR2_CTL, val);
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10)
2018-05-23 3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
@ 2018-05-23 3:24 ` Patchwork
2018-05-23 3:45 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-05-23 3:24 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: vbt change for psr (rev10)
URL : https://patchwork.freedesktop.org/series/41289/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
46c7737a0d9a drm/i915/psr: vbt change for psr
-:85: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#85: FILE: drivers/gpu/drm/i915/i915_reg.h:4091:
+#define EDP_PSR2_TP2_TIME_500us (0<<8)
^
-:86: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#86: FILE: drivers/gpu/drm/i915/i915_reg.h:4092:
+#define EDP_PSR2_TP2_TIME_100us (1<<8)
^
-:87: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:4093:
+#define EDP_PSR2_TP2_TIME_2500us (2<<8)
^
-:88: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#88: FILE: drivers/gpu/drm/i915/i915_reg.h:4094:
+#define EDP_PSR2_TP2_TIME_50us (3<<8)
^
-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/intel_bios.c:704:
+ DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+ psr_table->tp1_wakeup_time);
-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/intel_bios.c:723:
+ DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+ psr_table->tp2_tp3_wakeup_time);
total: 0 errors, 0 warnings, 6 checks, 135 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/psr: vbt change for psr (rev10)
2018-05-23 3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
2018-05-23 3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
@ 2018-05-23 3:45 ` Patchwork
2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-05-23 3:45 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: vbt change for psr (rev10)
URL : https://patchwork.freedesktop.org/series/41289/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4222 -> Patchwork_9090 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9090 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9090, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/10/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9090:
=== IGT changes ===
==== Possible regressions ====
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: PASS -> FAIL
== Known issues ==
Here are the changes found in Patchwork_9090 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
==== Possible fixes ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-skl-6770hq: FAIL (fdo#103928, fdo#100368) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-FAIL (fdo#106103, fdo#102614) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
== Participating hosts (44 -> 39) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4222 -> Patchwork_9090
CI_DRM_4222: e783c316409040dab016975896e718fc36cbd8e6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4492: 0b381c7d1067a4fe520b72d4d391d4920834cbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9090: 46c7737a0d9a5e7256fa23032816fe97c2059da0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4492: 53aa71861efe0095405673c98ff15f6dcf268901 @ git://anongit.freedesktop.org/piglit
== Linux commits ==
46c7737a0d9a drm/i915/psr: vbt change for psr
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9090/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/psr: vbt change for psr
2018-05-23 3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
2018-05-23 3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
2018-05-23 3:45 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-05-23 10:03 ` Jani Nikula
2018-05-23 12:55 ` Nagaraju, Vathsala
2 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2018-05-23 10:03 UTC (permalink / raw)
To: vathsala nagaraju, intel-gfx
Cc: Maulik V Vaghela, Dhinakaran Pandiyan, Rodrigo Vivi,
Puthikorn Voravootivat
On Wed, 23 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not mention from which VBT version this
> change was added to vbt.bsf file, we cannot depend on bdb->version check
> to change for all the platforms.
>
> There is RCR inplace for GOP team to provide the version number
> to make generic change. Since Kabylake with bdb version 209 is having this
> change, limiting this change to gen9_bc and version 209+ to unblock google.
>
> Tested on skl(bdb version 203,without options) and
> kabylake(bdb version 209,212) having new options.
>
> bspec 20131
>
> v2: (Jani and Rodrigo)
> move the 165 version check to intel_bios.c
> v3: Jani
> Move the abstraction to intel_bios.
> v4: Jani
> Rename tp*_wakeup_time to have "us" suffix.
> For values outside range[0-3],default to max 2500us.
> Old decimal value was wake up time in multiples of 100us.
> v5: Jani and Rodrigo
> Handle option 2 in default condition.
> Print oustide range value.
> For negetive values default to 2500us.
> v6: Jani
> Handle default first and then fall through for case 2.
> v7: Rodrigo
> Apply this change for IS_GEN9_BC and vbt version > 209
> v8: Puthik
> Add new function vbt_psr_to_us.
> v9: Jani
> Change to v7 version as it's more readable.
> DK
> add comment /*fall through*/ after case2.
Why did you send this again? Did you change something? I already
reviewed the version from yesterday.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/psr: vbt change for psr
2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
@ 2018-05-23 12:55 ` Nagaraju, Vathsala
2018-05-23 13:10 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Nagaraju, Vathsala @ 2018-05-23 12:55 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan,
Rodrigo Vivi
On 5/23/2018 3:33 PM, Jani Nikula wrote:
> On Wed, 23 May 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to gen9_bc and version 209+ to unblock google.
>>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>> move the 165 version check to intel_bios.c
>> v3: Jani
>> Move the abstraction to intel_bios.
>> v4: Jani
>> Rename tp*_wakeup_time to have "us" suffix.
>> For values outside range[0-3],default to max 2500us.
>> Old decimal value was wake up time in multiples of 100us.
>> v5: Jani and Rodrigo
>> Handle option 2 in default condition.
>> Print oustide range value.
>> For negetive values default to 2500us.
>> v6: Jani
>> Handle default first and then fall through for case 2.
>> v7: Rodrigo
>> Apply this change for IS_GEN9_BC and vbt version > 209
>> v8: Puthik
>> Add new function vbt_psr_to_us.
>> v9: Jani
>> Change to v7 version as it's more readable.
>> DK
>> add comment /*fall through*/ after case2.
> Why did you send this again? Did you change something? I already
> reviewed the version from yesterday.
no code change, added only rb tag by you and resent it.
> BR,
> Jani.
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/psr: vbt change for psr
2018-05-23 12:55 ` Nagaraju, Vathsala
@ 2018-05-23 13:10 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2018-05-23 13:10 UTC (permalink / raw)
To: Nagaraju, Vathsala, intel-gfx
Cc: Puthikorn Voravootivat, Maulik V Vaghela, Dhinakaran Pandiyan,
Rodrigo Vivi
On Wed, 23 May 2018, "Nagaraju, Vathsala" <vathsala.nagaraju@intel.com> wrote:
> On 5/23/2018 3:33 PM, Jani Nikula wrote:
>> Why did you send this again? Did you change something? I already
>> reviewed the version from yesterday.
> no code change, added only rb tag by you and resent it.
For future reference, you should *not* resend for that.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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2018-05-23 3:05 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
2018-05-23 3:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: vbt change for psr (rev10) Patchwork
2018-05-23 3:45 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-23 10:03 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
2018-05-23 12:55 ` Nagaraju, Vathsala
2018-05-23 13:10 ` Jani Nikula
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