* [PATCH 2/6] drm/amdgpu: move ih definitions into amdgpu_ih header
[not found] ` <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
@ 2018-08-02 11:08 ` Huang Rui
2018-08-02 11:08 ` [PATCH 3/6] drm/amdgpu: move sdma definitions into amdgpu_sdma header Huang Rui
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Huang Rui @ 2018-08-02 11:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Huang Rui
Demangle amdgpu.h
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14 --------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 17c0afe..90717bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -319,16 +319,6 @@ struct amdgpu_vm_pte_funcs {
uint32_t incr, uint64_t flags);
};
-/* provided by the ih block */
-struct amdgpu_ih_funcs {
- /* ring read/write ptr handling, called from interrupt context */
- u32 (*get_wptr)(struct amdgpu_device *adev);
- bool (*prescreen_iv)(struct amdgpu_device *adev);
- void (*decode_iv)(struct amdgpu_device *adev,
- struct amdgpu_iv_entry *entry);
- void (*set_rptr)(struct amdgpu_device *adev);
-};
-
/*
* BIOS.
*/
@@ -1464,10 +1454,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
-#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
-#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
-#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
-#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 0e01f11..a23e1c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -76,6 +76,21 @@ struct amdgpu_iv_entry {
const uint32_t *iv_entry;
};
+/* provided by the ih block */
+struct amdgpu_ih_funcs {
+ /* ring read/write ptr handling, called from interrupt context */
+ u32 (*get_wptr)(struct amdgpu_device *adev);
+ bool (*prescreen_iv)(struct amdgpu_device *adev);
+ void (*decode_iv)(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry);
+ void (*set_rptr)(struct amdgpu_device *adev);
+};
+
+#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
+#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
+#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
+#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
+
int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
bool use_bus_addr);
void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/6] drm/amdgpu: move sdma definitions into amdgpu_sdma header
[not found] ` <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2018-08-02 11:08 ` [PATCH 2/6] drm/amdgpu: move ih definitions into amdgpu_ih header Huang Rui
@ 2018-08-02 11:08 ` Huang Rui
2018-08-02 11:08 ` [PATCH 4/6] drm/amdgpu: move firmware definitions into amdgpu_ucode header Huang Rui
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Huang Rui @ 2018-08-02 11:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Huang Rui
Demangle amdgpu.h.
Furthermore, SDMA is used for moving and clearing the data buffer, so the header
also need be included in ttm.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 87 +-------------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 44 ++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 101 +++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 +
5 files changed, 148 insertions(+), 86 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index bfd332c..e610656 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -108,6 +108,7 @@ amdgpu-y += \
# add async DMA block
amdgpu-y += \
+ amdgpu_sdma.o \
sdma_v2_4.o \
sdma_v3_0.o \
sdma_v4_0.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 90717bd..40f502c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -70,6 +70,7 @@
#include "amdgpu_mn.h"
#include "amdgpu_gmc.h"
#include "amdgpu_gfx.h"
+#include "amdgpu_sdma.h"
#include "amdgpu_dm.h"
#include "amdgpu_virt.h"
#include "amdgpu_gart.h"
@@ -149,9 +150,6 @@ extern int amdgpu_cik_support;
#define AMDGPUFB_CONN_LIMIT 4
#define AMDGPU_BIOS_NUM_SCRATCH 16
-/* max number of IP instances */
-#define AMDGPU_MAX_SDMA_INSTANCES 2
-
/* hard reset data */
#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
@@ -199,13 +197,6 @@ enum amdgpu_cp_irq {
AMDGPU_CP_IRQ_LAST
};
-enum amdgpu_sdma_irq {
- AMDGPU_SDMA_IRQ_TRAP0 = 0,
- AMDGPU_SDMA_IRQ_TRAP1,
-
- AMDGPU_SDMA_IRQ_LAST
-};
-
enum amdgpu_thermal_irq {
AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
@@ -265,39 +256,6 @@ amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
const struct amdgpu_ip_block_version *ip_block_version);
-/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
-struct amdgpu_buffer_funcs {
- /* maximum bytes in a single operation */
- uint32_t copy_max_bytes;
-
- /* number of dw to reserve per operation */
- unsigned copy_num_dw;
-
- /* used for buffer migration */
- void (*emit_copy_buffer)(struct amdgpu_ib *ib,
- /* src addr in bytes */
- uint64_t src_offset,
- /* dst addr in bytes */
- uint64_t dst_offset,
- /* number of byte to transfer */
- uint32_t byte_count);
-
- /* maximum bytes in a single operation */
- uint32_t fill_max_bytes;
-
- /* number of dw to reserve per operation */
- unsigned fill_num_dw;
-
- /* used for buffer clearing */
- void (*emit_fill_buffer)(struct amdgpu_ib *ib,
- /* value to write to memory */
- uint32_t src_data,
- /* dst addr in bytes */
- uint64_t dst_offset,
- /* number of byte to fill */
- uint32_t byte_count);
-};
-
/* provided by hw blocks that can write ptes, e.g., sdma */
struct amdgpu_vm_pte_funcs {
/* number of dw to reserve per operation */
@@ -757,31 +715,6 @@ int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
/*
- * SDMA
- */
-struct amdgpu_sdma_instance {
- /* SDMA firmware */
- const struct firmware *fw;
- uint32_t fw_version;
- uint32_t feature_version;
-
- struct amdgpu_ring ring;
- bool burst_nop;
-};
-
-struct amdgpu_sdma {
- struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
-#ifdef CONFIG_DRM_AMDGPU_SI
- //SI DMA has a difference trap irq number for the second engine
- struct amdgpu_irq_src trap_irq_1;
-#endif
- struct amdgpu_irq_src trap_irq;
- struct amdgpu_irq_src illegal_inst_irq;
- int num_instances;
- uint32_t srbm_soft_reset;
-};
-
-/*
* Firmware
*/
enum amdgpu_firmware_load_type {
@@ -1388,22 +1321,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
-static inline struct amdgpu_sdma_instance *
-amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
-{
- struct amdgpu_device *adev = ring->adev;
- int i;
-
- for (i = 0; i < adev->sdma.num_instances; i++)
- if (&adev->sdma.instance[i].ring == ring)
- break;
-
- if (i < AMDGPU_MAX_SDMA_INSTANCES)
- return &adev->sdma.instance[i];
- else
- return NULL;
-}
-
/*
* ASICs macro.
*/
@@ -1465,8 +1382,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
-#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
-#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
new file mode 100644
index 0000000..bc9244b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include <drm/drmP.h>
+#include "amdgpu.h"
+#include "amdgpu_sdma.h"
+
+/*
+ * GPU SDMA IP block helpers function.
+ */
+
+struct amdgpu_sdma_instance * amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++)
+ if (&adev->sdma.instance[i].ring == ring)
+ break;
+
+ if (i < AMDGPU_MAX_SDMA_INSTANCES)
+ return &adev->sdma.instance[i];
+ else
+ return NULL;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
new file mode 100644
index 0000000..d17503f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_SDMA_H__
+#define __AMDGPU_SDMA_H__
+
+/* max number of IP instances */
+#define AMDGPU_MAX_SDMA_INSTANCES 2
+
+enum amdgpu_sdma_irq {
+ AMDGPU_SDMA_IRQ_TRAP0 = 0,
+ AMDGPU_SDMA_IRQ_TRAP1,
+
+ AMDGPU_SDMA_IRQ_LAST
+};
+
+struct amdgpu_sdma_instance {
+ /* SDMA firmware */
+ const struct firmware *fw;
+ uint32_t fw_version;
+ uint32_t feature_version;
+
+ struct amdgpu_ring ring;
+ bool burst_nop;
+};
+
+struct amdgpu_sdma {
+ struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
+#ifdef CONFIG_DRM_AMDGPU_SI
+ //SI DMA has a difference trap irq number for the second engine
+ struct amdgpu_irq_src trap_irq_1;
+#endif
+ struct amdgpu_irq_src trap_irq;
+ struct amdgpu_irq_src illegal_inst_irq;
+ int num_instances;
+ uint32_t srbm_soft_reset;
+};
+
+/*
+ * Provided by hw blocks that can move/clear data. e.g., gfx or sdma
+ * But currently, we use sdma to move data.
+ */
+struct amdgpu_buffer_funcs {
+ /* maximum bytes in a single operation */
+ uint32_t copy_max_bytes;
+
+ /* number of dw to reserve per operation */
+ unsigned copy_num_dw;
+
+ /* used for buffer migration */
+ void (*emit_copy_buffer)(struct amdgpu_ib *ib,
+ /* src addr in bytes */
+ uint64_t src_offset,
+ /* dst addr in bytes */
+ uint64_t dst_offset,
+ /* number of byte to transfer */
+ uint32_t byte_count);
+
+ /* maximum bytes in a single operation */
+ uint32_t fill_max_bytes;
+
+ /* number of dw to reserve per operation */
+ unsigned fill_num_dw;
+
+ /* used for buffer clearing */
+ void (*emit_fill_buffer)(struct amdgpu_ib *ib,
+ /* value to write to memory */
+ uint32_t src_data,
+ /* dst addr in bytes */
+ uint64_t dst_offset,
+ /* number of byte to fill */
+ uint32_t byte_count);
+};
+
+#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
+#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
+
+struct amdgpu_sdma_instance *
+amdgpu_get_sdma_instance(struct amdgpu_ring *ring);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index fcf4212..c6611cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -47,6 +47,7 @@
#include "amdgpu_object.h"
#include "amdgpu_trace.h"
#include "amdgpu_amdkfd.h"
+#include "amdgpu_sdma.h"
#include "bif/bif_4_1_d.h"
#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/6] drm/amdgpu: move firmware definitions into amdgpu_ucode header
[not found] ` <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2018-08-02 11:08 ` [PATCH 2/6] drm/amdgpu: move ih definitions into amdgpu_ih header Huang Rui
2018-08-02 11:08 ` [PATCH 3/6] drm/amdgpu: move sdma definitions into amdgpu_sdma header Huang Rui
@ 2018-08-02 11:08 ` Huang Rui
2018-08-02 11:08 ` [PATCH 5/6] drm/amdgpu: move psp macro into amdgpu_ucode into amdgpu_psp header Huang Rui
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Huang Rui @ 2018-08-02 11:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Huang Rui
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 27 ---------------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 24 ++++++++++++++++++++++++
2 files changed, 24 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 40f502c..afb7761 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -715,33 +715,6 @@ int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
/*
- * Firmware
- */
-enum amdgpu_firmware_load_type {
- AMDGPU_FW_LOAD_DIRECT = 0,
- AMDGPU_FW_LOAD_SMU,
- AMDGPU_FW_LOAD_PSP,
-};
-
-struct amdgpu_firmware {
- struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
- enum amdgpu_firmware_load_type load_type;
- struct amdgpu_bo *fw_buf;
- unsigned int fw_size;
- unsigned int max_ucodes;
- /* firmwares are loaded by psp instead of smu from vega10 */
- const struct amdgpu_psp_funcs *funcs;
- struct amdgpu_bo *rbuf;
- struct mutex mutex;
-
- /* gpu info firmware data pointer */
- const struct firmware *gpu_info_fw;
-
- void *fw_buf_ptr;
- uint64_t fw_buf_mc;
-};
-
-/*
* Benchmarking
*/
void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 08e3857..11e81a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -204,6 +204,12 @@ enum AMDGPU_UCODE_STATUS {
AMDGPU_UCODE_STATUS_LOADED,
};
+enum amdgpu_firmware_load_type {
+ AMDGPU_FW_LOAD_DIRECT = 0,
+ AMDGPU_FW_LOAD_SMU,
+ AMDGPU_FW_LOAD_PSP,
+};
+
/* conform to smu_ucode_xfer_cz.h */
#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
@@ -228,6 +234,24 @@ struct amdgpu_firmware_info {
uint32_t ucode_size;
};
+struct amdgpu_firmware {
+ struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
+ enum amdgpu_firmware_load_type load_type;
+ struct amdgpu_bo *fw_buf;
+ unsigned int fw_size;
+ unsigned int max_ucodes;
+ /* firmwares are loaded by psp instead of smu from vega10 */
+ const struct amdgpu_psp_funcs *funcs;
+ struct amdgpu_bo *rbuf;
+ struct mutex mutex;
+
+ /* gpu info firmware data pointer */
+ const struct firmware *gpu_info_fw;
+
+ void *fw_buf_ptr;
+ uint64_t fw_buf_mc;
+};
+
void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 5/6] drm/amdgpu: move psp macro into amdgpu_ucode into amdgpu_psp header
[not found] ` <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-08-02 11:08 ` [PATCH 4/6] drm/amdgpu: move firmware definitions into amdgpu_ucode header Huang Rui
@ 2018-08-02 11:08 ` Huang Rui
[not found] ` <1533208095-15055-5-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2018-08-02 11:08 ` [PATCH 6/6] drm/amdgpu: move gem definitions into amdgpu_gem header Huang Rui
2018-08-02 11:44 ` [PATCH 1/6] drm/amdgpu: move gfx definitions into amdgpu_gfx header Christian König
5 siblings, 1 reply; 8+ messages in thread
From: Huang Rui @ 2018-08-02 11:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Huang Rui
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 29 +++++++++++++++++------------
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index afb7761..bf7633a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1356,7 +1356,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
-#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
/* Common functions */
int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 1292096..967712f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -63,13 +63,16 @@ struct psp_funcs
int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd);
int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
- int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
+ int (*ring_create)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
int (*ring_stop)(struct psp_context *psp,
enum psp_ring_type ring_type);
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
- int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index);
+ int (*cmd_submit)(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ int index);
bool (*compare_sram_data)(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
enum AMDGPU_UCODE_ID ucode_type);
@@ -83,11 +86,11 @@ struct psp_context
struct psp_ring km_ring;
struct psp_gfx_cmd_resp *cmd;
- const struct psp_funcs *funcs;
+ const struct psp_funcs *funcs;
/* fence buffer */
- struct amdgpu_bo *fw_pri_bo;
- uint64_t fw_pri_mc_addr;
+ struct amdgpu_bo *fw_pri_bo;
+ uint64_t fw_pri_mc_addr;
void *fw_pri_buf;
/* sos firmware */
@@ -100,8 +103,8 @@ struct psp_context
uint8_t *sos_start_addr;
/* tmr buffer */
- struct amdgpu_bo *tmr_bo;
- uint64_t tmr_mc_addr;
+ struct amdgpu_bo *tmr_bo;
+ uint64_t tmr_mc_addr;
void *tmr_buf;
/* asd firmware and buffer */
@@ -110,13 +113,13 @@ struct psp_context
uint32_t asd_feature_version;
uint32_t asd_ucode_size;
uint8_t *asd_start_addr;
- struct amdgpu_bo *asd_shared_bo;
- uint64_t asd_shared_mc_addr;
+ struct amdgpu_bo *asd_shared_bo;
+ uint64_t asd_shared_mc_addr;
void *asd_shared_buf;
/* fence buffer */
- struct amdgpu_bo *fence_buf_bo;
- uint64_t fence_buf_mc_addr;
+ struct amdgpu_bo *fence_buf_bo;
+ uint64_t fence_buf_mc_addr;
void *fence_buf;
/* cmd buffer */
@@ -150,6 +153,8 @@ struct amdgpu_psp_funcs {
#define psp_mode1_reset(psp) \
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
+#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
+
extern const struct amd_ip_funcs psp_ip_funcs;
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 6/6] drm/amdgpu: move gem definitions into amdgpu_gem header
[not found] ` <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-08-02 11:08 ` [PATCH 5/6] drm/amdgpu: move psp macro into amdgpu_ucode into amdgpu_psp header Huang Rui
@ 2018-08-02 11:08 ` Huang Rui
2018-08-02 11:44 ` [PATCH 1/6] drm/amdgpu: move gfx definitions into amdgpu_gfx header Christian König
5 siblings, 0 replies; 8+ messages in thread
From: Huang Rui @ 2018-08-02 11:08 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Huang Rui
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 62 +--------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 92 +++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
11 files changed, 102 insertions(+), 61 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bf7633a..eca55fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -77,6 +77,7 @@
#include "amdgpu_debugfs.h"
#include "amdgpu_job.h"
#include "amdgpu_bo_list.h"
+#include "amdgpu_gem.h"
/*
* Modules parameters.
@@ -302,34 +303,6 @@ struct amdgpu_clock {
uint32_t max_pixel_clock;
};
-/*
- * GEM.
- */
-
-#define AMDGPU_GEM_DOMAIN_MAX 0x3
-#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
-
-void amdgpu_gem_object_free(struct drm_gem_object *obj);
-int amdgpu_gem_object_open(struct drm_gem_object *obj,
- struct drm_file *file_priv);
-void amdgpu_gem_object_close(struct drm_gem_object *obj,
- struct drm_file *file_priv);
-unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
-struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
-struct drm_gem_object *
-amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
- struct dma_buf_attachment *attach,
- struct sg_table *sg);
-struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
- struct drm_gem_object *gobj,
- int flags);
-struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
- struct dma_buf *dma_buf);
-struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
-void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
-void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
-int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
-
/* sub-allocation manager, it has to be protected by another lock.
* By conception this is an helper for other part of the driver
* like the indirect buffer or semaphore, which both have their
@@ -379,22 +352,6 @@ struct amdgpu_sa_bo {
struct dma_fence *fence;
};
-/*
- * GEM objects.
- */
-void amdgpu_gem_force_release(struct amdgpu_device *adev);
-int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
- int alignment, u32 initial_domain,
- u64 flags, enum ttm_bo_type type,
- struct reservation_object *resv,
- struct drm_gem_object **obj);
-
-int amdgpu_mode_dumb_create(struct drm_file *file_priv,
- struct drm_device *dev,
- struct drm_mode_create_dumb *args);
-int amdgpu_mode_dumb_mmap(struct drm_file *filp,
- struct drm_device *dev,
- uint32_t handle, uint64_t *offset_p);
int amdgpu_fence_slab_init(void);
void amdgpu_fence_slab_fini(void);
@@ -791,23 +748,9 @@ struct amdgpu_asic_funcs {
/*
* IOCTL.
*/
-int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
-int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
-int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
-int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
-int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
-int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
-int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
@@ -815,9 +758,6 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *fi
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
-int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp);
-
int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 502b94f..e12871d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -32,6 +32,7 @@
#include "amdgpu.h"
#include "amdgpu_trace.h"
#include "amdgpu_gmc.h"
+#include "amdgpu_gem.h"
static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
struct drm_amdgpu_cs_chunk_fence *data,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8843a06..75c9433 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -36,6 +36,7 @@
#include "amdgpu.h"
#include "amdgpu_irq.h"
+#include "amdgpu_gem.h"
#include "amdgpu_amdkfd.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 69c5d22..5cbde74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -33,6 +33,7 @@
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "cikd.h"
+#include "amdgpu_gem.h"
#include <drm/drm_fb_helper.h>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
new file mode 100644
index 0000000..d63daba
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __AMDGPU_GEM_H__
+#define __AMDGPU_GEM_H__
+
+#include <drm/amdgpu_drm.h>
+#include <drm/drm_gem.h>
+
+/*
+ * GEM.
+ */
+
+#define AMDGPU_GEM_DOMAIN_MAX 0x3
+#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
+
+void amdgpu_gem_object_free(struct drm_gem_object *obj);
+int amdgpu_gem_object_open(struct drm_gem_object *obj,
+ struct drm_file *file_priv);
+void amdgpu_gem_object_close(struct drm_gem_object *obj,
+ struct drm_file *file_priv);
+unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
+struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
+struct drm_gem_object *
+amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sg);
+struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
+ struct drm_gem_object *gobj,
+ int flags);
+struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
+ struct dma_buf *dma_buf);
+struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
+void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
+void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
+int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
+
+/*
+ * GEM objects.
+ */
+void amdgpu_gem_force_release(struct amdgpu_device *adev);
+int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
+ int alignment, u32 initial_domain,
+ u64 flags, enum ttm_bo_type type,
+ struct reservation_object *resv,
+ struct drm_gem_object **obj);
+
+int amdgpu_mode_dumb_create(struct drm_file *file_priv,
+ struct drm_device *dev,
+ struct drm_mode_create_dumb *args);
+int amdgpu_mode_dumb_mmap(struct drm_file *filp,
+ struct drm_device *dev,
+ uint32_t handle, uint64_t *offset_p);
+
+int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+
+int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5b26e04..ccc9c8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -37,6 +37,7 @@
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include "amdgpu_amdkfd.h"
+#include "amdgpu_gem.h"
/**
* amdgpu_driver_unload_kms - Main unload function for KMS.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 1c5d97f..2686297 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -35,6 +35,7 @@
#include "amdgpu.h"
#include "amdgpu_display.h"
+#include "amdgpu_gem.h"
#include <drm/amdgpu_drm.h>
#include <linux/dma-buf.h>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 75317f2..c14cf1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -26,6 +26,7 @@
#include "amdgpu.h"
#include "gmc_v6_0.h"
#include "amdgpu_ucode.h"
+#include "amdgpu_gem.h"
#include "bif/bif_3_0_d.h"
#include "bif/bif_3_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 54339a9..0c3a161 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -28,6 +28,7 @@
#include "cik.h"
#include "gmc_v7_0.h"
#include "amdgpu_ucode.h"
+#include "amdgpu_gem.h"
#include "bif/bif_4_1_d.h"
#include "bif/bif_4_1_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 75f3ffb..274c932 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -26,6 +26,7 @@
#include "amdgpu.h"
#include "gmc_v8_0.h"
#include "amdgpu_ucode.h"
+#include "amdgpu_gem.h"
#include "gmc/gmc_8_1_d.h"
#include "gmc/gmc_8_1_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 399a5db..ed467de 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -25,6 +25,7 @@
#include "amdgpu.h"
#include "gmc_v9_0.h"
#include "amdgpu_atomfirmware.h"
+#include "amdgpu_gem.h"
#include "hdp/hdp_4_0_offset.h"
#include "hdp/hdp_4_0_sh_mask.h"
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/6] drm/amdgpu: move gfx definitions into amdgpu_gfx header
[not found] ` <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2018-08-02 11:08 ` [PATCH 6/6] drm/amdgpu: move gem definitions into amdgpu_gem header Huang Rui
@ 2018-08-02 11:44 ` Christian König
5 siblings, 0 replies; 8+ messages in thread
From: Christian König @ 2018-08-02 11:44 UTC (permalink / raw)
To: Huang Rui, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 02.08.2018 um 13:08 schrieb Huang Rui:
> Demangle amdgpu.h
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com> for the whole series.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 276 +------------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 34 +++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 343 ++++++++++++++++++++++++++++----
> 3 files changed, 336 insertions(+), 317 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 95af917..17c0afe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -69,6 +69,7 @@
> #include "amdgpu_vcn.h"
> #include "amdgpu_mn.h"
> #include "amdgpu_gmc.h"
> +#include "amdgpu_gfx.h"
> #include "amdgpu_dm.h"
> #include "amdgpu_virt.h"
> #include "amdgpu_gart.h"
> @@ -171,13 +172,6 @@ extern int amdgpu_cik_support;
> #define AMDGPU_RESET_VCE (1 << 13)
> #define AMDGPU_RESET_VCE1 (1 << 14)
>
> -/* GFX current status */
> -#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
> -#define AMDGPU_GFX_SAFE_MODE 0x00000001L
> -#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
> -#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
> -#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
> -
> /* max cursor sizes (in pixels) */
> #define CIK_CURSOR_WIDTH 128
> #define CIK_CURSOR_HEIGHT 128
> @@ -690,271 +684,6 @@ struct amdgpu_fpriv {
> struct amdgpu_ctx_mgr ctx_mgr;
> };
>
> -/*
> - * GFX stuff
> - */
> -#include "clearstate_defs.h"
> -
> -struct amdgpu_rlc_funcs {
> - void (*enter_safe_mode)(struct amdgpu_device *adev);
> - void (*exit_safe_mode)(struct amdgpu_device *adev);
> -};
> -
> -struct amdgpu_rlc {
> - /* for power gating */
> - struct amdgpu_bo *save_restore_obj;
> - uint64_t save_restore_gpu_addr;
> - volatile uint32_t *sr_ptr;
> - const u32 *reg_list;
> - u32 reg_list_size;
> - /* for clear state */
> - struct amdgpu_bo *clear_state_obj;
> - uint64_t clear_state_gpu_addr;
> - volatile uint32_t *cs_ptr;
> - const struct cs_section_def *cs_data;
> - u32 clear_state_size;
> - /* for cp tables */
> - struct amdgpu_bo *cp_table_obj;
> - uint64_t cp_table_gpu_addr;
> - volatile uint32_t *cp_table_ptr;
> - u32 cp_table_size;
> -
> - /* safe mode for updating CG/PG state */
> - bool in_safe_mode;
> - const struct amdgpu_rlc_funcs *funcs;
> -
> - /* for firmware data */
> - u32 save_and_restore_offset;
> - u32 clear_state_descriptor_offset;
> - u32 avail_scratch_ram_locations;
> - u32 reg_restore_list_size;
> - u32 reg_list_format_start;
> - u32 reg_list_format_separate_start;
> - u32 starting_offsets_start;
> - u32 reg_list_format_size_bytes;
> - u32 reg_list_size_bytes;
> - u32 reg_list_format_direct_reg_list_length;
> - u32 save_restore_list_cntl_size_bytes;
> - u32 save_restore_list_gpm_size_bytes;
> - u32 save_restore_list_srm_size_bytes;
> -
> - u32 *register_list_format;
> - u32 *register_restore;
> - u8 *save_restore_list_cntl;
> - u8 *save_restore_list_gpm;
> - u8 *save_restore_list_srm;
> -
> - bool is_rlc_v2_1;
> -};
> -
> -#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
> -
> -struct amdgpu_mec {
> - struct amdgpu_bo *hpd_eop_obj;
> - u64 hpd_eop_gpu_addr;
> - struct amdgpu_bo *mec_fw_obj;
> - u64 mec_fw_gpu_addr;
> - u32 num_mec;
> - u32 num_pipe_per_mec;
> - u32 num_queue_per_pipe;
> - void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
> -
> - /* These are the resources for which amdgpu takes ownership */
> - DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
> -};
> -
> -struct amdgpu_kiq {
> - u64 eop_gpu_addr;
> - struct amdgpu_bo *eop_obj;
> - spinlock_t ring_lock;
> - struct amdgpu_ring ring;
> - struct amdgpu_irq_src irq;
> -};
> -
> -/*
> - * GPU scratch registers structures, functions & helpers
> - */
> -struct amdgpu_scratch {
> - unsigned num_reg;
> - uint32_t reg_base;
> - uint32_t free_mask;
> -};
> -
> -/*
> - * GFX configurations
> - */
> -#define AMDGPU_GFX_MAX_SE 4
> -#define AMDGPU_GFX_MAX_SH_PER_SE 2
> -
> -struct amdgpu_rb_config {
> - uint32_t rb_backend_disable;
> - uint32_t user_rb_backend_disable;
> - uint32_t raster_config;
> - uint32_t raster_config_1;
> -};
> -
> -struct gb_addr_config {
> - uint16_t pipe_interleave_size;
> - uint8_t num_pipes;
> - uint8_t max_compress_frags;
> - uint8_t num_banks;
> - uint8_t num_se;
> - uint8_t num_rb_per_se;
> -};
> -
> -struct amdgpu_gfx_config {
> - unsigned max_shader_engines;
> - unsigned max_tile_pipes;
> - unsigned max_cu_per_sh;
> - unsigned max_sh_per_se;
> - unsigned max_backends_per_se;
> - unsigned max_texture_channel_caches;
> - unsigned max_gprs;
> - unsigned max_gs_threads;
> - unsigned max_hw_contexts;
> - unsigned sc_prim_fifo_size_frontend;
> - unsigned sc_prim_fifo_size_backend;
> - unsigned sc_hiz_tile_fifo_size;
> - unsigned sc_earlyz_tile_fifo_size;
> -
> - unsigned num_tile_pipes;
> - unsigned backend_enable_mask;
> - unsigned mem_max_burst_length_bytes;
> - unsigned mem_row_size_in_kb;
> - unsigned shader_engine_tile_size;
> - unsigned num_gpus;
> - unsigned multi_gpu_tile_size;
> - unsigned mc_arb_ramcfg;
> - unsigned gb_addr_config;
> - unsigned num_rbs;
> - unsigned gs_vgt_table_depth;
> - unsigned gs_prim_buffer_depth;
> -
> - uint32_t tile_mode_array[32];
> - uint32_t macrotile_mode_array[16];
> -
> - struct gb_addr_config gb_addr_config_fields;
> - struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
> -
> - /* gfx configure feature */
> - uint32_t double_offchip_lds_buf;
> - /* cached value of DB_DEBUG2 */
> - uint32_t db_debug2;
> -};
> -
> -struct amdgpu_cu_info {
> - uint32_t simd_per_cu;
> - uint32_t max_waves_per_simd;
> - uint32_t wave_front_size;
> - uint32_t max_scratch_slots_per_cu;
> - uint32_t lds_size;
> -
> - /* total active CU number */
> - uint32_t number;
> - uint32_t ao_cu_mask;
> - uint32_t ao_cu_bitmap[4][4];
> - uint32_t bitmap[4][4];
> -};
> -
> -struct amdgpu_gfx_funcs {
> - /* get the gpu clock counter */
> - uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
> - void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
> - void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
> - void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
> - void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
> - void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue);
> -};
> -
> -struct amdgpu_ngg_buf {
> - struct amdgpu_bo *bo;
> - uint64_t gpu_addr;
> - uint32_t size;
> - uint32_t bo_size;
> -};
> -
> -enum {
> - NGG_PRIM = 0,
> - NGG_POS,
> - NGG_CNTL,
> - NGG_PARAM,
> - NGG_BUF_MAX
> -};
> -
> -struct amdgpu_ngg {
> - struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
> - uint32_t gds_reserve_addr;
> - uint32_t gds_reserve_size;
> - bool init;
> -};
> -
> -struct sq_work {
> - struct work_struct work;
> - unsigned ih_data;
> -};
> -
> -struct amdgpu_gfx {
> - struct mutex gpu_clock_mutex;
> - struct amdgpu_gfx_config config;
> - struct amdgpu_rlc rlc;
> - struct amdgpu_mec mec;
> - struct amdgpu_kiq kiq;
> - struct amdgpu_scratch scratch;
> - const struct firmware *me_fw; /* ME firmware */
> - uint32_t me_fw_version;
> - const struct firmware *pfp_fw; /* PFP firmware */
> - uint32_t pfp_fw_version;
> - const struct firmware *ce_fw; /* CE firmware */
> - uint32_t ce_fw_version;
> - const struct firmware *rlc_fw; /* RLC firmware */
> - uint32_t rlc_fw_version;
> - const struct firmware *mec_fw; /* MEC firmware */
> - uint32_t mec_fw_version;
> - const struct firmware *mec2_fw; /* MEC2 firmware */
> - uint32_t mec2_fw_version;
> - uint32_t me_feature_version;
> - uint32_t ce_feature_version;
> - uint32_t pfp_feature_version;
> - uint32_t rlc_feature_version;
> - uint32_t rlc_srlc_fw_version;
> - uint32_t rlc_srlc_feature_version;
> - uint32_t rlc_srlg_fw_version;
> - uint32_t rlc_srlg_feature_version;
> - uint32_t rlc_srls_fw_version;
> - uint32_t rlc_srls_feature_version;
> - uint32_t mec_feature_version;
> - uint32_t mec2_feature_version;
> - struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
> - unsigned num_gfx_rings;
> - struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
> - unsigned num_compute_rings;
> - struct amdgpu_irq_src eop_irq;
> - struct amdgpu_irq_src priv_reg_irq;
> - struct amdgpu_irq_src priv_inst_irq;
> - struct amdgpu_irq_src cp_ecc_error_irq;
> - struct amdgpu_irq_src sq_irq;
> - struct sq_work sq_work;
> -
> - /* gfx status */
> - uint32_t gfx_current_status;
> - /* ce ram size*/
> - unsigned ce_ram_size;
> - struct amdgpu_cu_info cu_info;
> - const struct amdgpu_gfx_funcs *funcs;
> -
> - /* reset mask */
> - uint32_t grbm_soft_reset;
> - uint32_t srbm_soft_reset;
> - /* s3/s4 mask */
> - bool in_suspend;
> - /* NGG */
> - struct amdgpu_ngg ngg;
> -
> - /* pipe reservation */
> - struct mutex pipe_reserve_mutex;
> - DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
> -};
> -
> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> unsigned size, struct amdgpu_ib *ib);
> void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
> @@ -1752,11 +1481,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
> #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
> #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
> #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
> -#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
> -#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
> #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
> #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
> -#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
>
> /* Common functions */
> int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 239bf2a..b393cf0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -27,8 +27,40 @@
> #include "amdgpu_gfx.h"
>
> /*
> - * GPU scratch registers helpers function.
> + * GPU GFX IP block helpers function.
> */
> +
> +int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
> + int pipe, int queue)
> +{
> + int bit = 0;
> +
> + bit += mec * adev->gfx.mec.num_pipe_per_mec
> + * adev->gfx.mec.num_queue_per_pipe;
> + bit += pipe * adev->gfx.mec.num_queue_per_pipe;
> + bit += queue;
> +
> + return bit;
> +}
> +
> +void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
> + int *mec, int *pipe, int *queue)
> +{
> + *queue = bit % adev->gfx.mec.num_queue_per_pipe;
> + *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
> + % adev->gfx.mec.num_pipe_per_mec;
> + *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
> + / adev->gfx.mec.num_pipe_per_mec;
> +
> +}
> +
> +bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
> + int mec, int pipe, int queue)
> +{
> + return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
> + adev->gfx.mec.queue_bitmap);
> +}
> +
> /**
> * amdgpu_gfx_scratch_get - Allocate a scratch register
> *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 1f27905..9291ed7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -24,28 +24,290 @@
> #ifndef __AMDGPU_GFX_H__
> #define __AMDGPU_GFX_H__
>
> -int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
> -void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
> +/*
> + * GFX stuff
> + */
> +#include "clearstate_defs.h"
> +#include "amdgpu_ring.h"
>
> -void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
> - unsigned max_sh);
> +/* GFX current status */
> +#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
> +#define AMDGPU_GFX_SAFE_MODE 0x00000001L
> +#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
> +#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
> +#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
>
> -void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
>
> -int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
> - struct amdgpu_ring *ring,
> - struct amdgpu_irq_src *irq);
> +struct amdgpu_rlc_funcs {
> + void (*enter_safe_mode)(struct amdgpu_device *adev);
> + void (*exit_safe_mode)(struct amdgpu_device *adev);
> +};
>
> -void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
> - struct amdgpu_irq_src *irq);
> +struct amdgpu_rlc {
> + /* for power gating */
> + struct amdgpu_bo *save_restore_obj;
> + uint64_t save_restore_gpu_addr;
> + volatile uint32_t *sr_ptr;
> + const u32 *reg_list;
> + u32 reg_list_size;
> + /* for clear state */
> + struct amdgpu_bo *clear_state_obj;
> + uint64_t clear_state_gpu_addr;
> + volatile uint32_t *cs_ptr;
> + const struct cs_section_def *cs_data;
> + u32 clear_state_size;
> + /* for cp tables */
> + struct amdgpu_bo *cp_table_obj;
> + uint64_t cp_table_gpu_addr;
> + volatile uint32_t *cp_table_ptr;
> + u32 cp_table_size;
>
> -void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
> -int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
> - unsigned hpd_size);
> + /* safe mode for updating CG/PG state */
> + bool in_safe_mode;
> + const struct amdgpu_rlc_funcs *funcs;
>
> -int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
> - unsigned mqd_size);
> -void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
> + /* for firmware data */
> + u32 save_and_restore_offset;
> + u32 clear_state_descriptor_offset;
> + u32 avail_scratch_ram_locations;
> + u32 reg_restore_list_size;
> + u32 reg_list_format_start;
> + u32 reg_list_format_separate_start;
> + u32 starting_offsets_start;
> + u32 reg_list_format_size_bytes;
> + u32 reg_list_size_bytes;
> + u32 reg_list_format_direct_reg_list_length;
> + u32 save_restore_list_cntl_size_bytes;
> + u32 save_restore_list_gpm_size_bytes;
> + u32 save_restore_list_srm_size_bytes;
> +
> + u32 *register_list_format;
> + u32 *register_restore;
> + u8 *save_restore_list_cntl;
> + u8 *save_restore_list_gpm;
> + u8 *save_restore_list_srm;
> +
> + bool is_rlc_v2_1;
> +};
> +
> +#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
> +
> +struct amdgpu_mec {
> + struct amdgpu_bo *hpd_eop_obj;
> + u64 hpd_eop_gpu_addr;
> + struct amdgpu_bo *mec_fw_obj;
> + u64 mec_fw_gpu_addr;
> + u32 num_mec;
> + u32 num_pipe_per_mec;
> + u32 num_queue_per_pipe;
> + void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
> +
> + /* These are the resources for which amdgpu takes ownership */
> + DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
> +};
> +
> +struct amdgpu_kiq {
> + u64 eop_gpu_addr;
> + struct amdgpu_bo *eop_obj;
> + spinlock_t ring_lock;
> + struct amdgpu_ring ring;
> + struct amdgpu_irq_src irq;
> +};
> +
> +/*
> + * GPU scratch registers structures, functions & helpers
> + */
> +struct amdgpu_scratch {
> + unsigned num_reg;
> + uint32_t reg_base;
> + uint32_t free_mask;
> +};
> +
> +/*
> + * GFX configurations
> + */
> +#define AMDGPU_GFX_MAX_SE 4
> +#define AMDGPU_GFX_MAX_SH_PER_SE 2
> +
> +struct amdgpu_rb_config {
> + uint32_t rb_backend_disable;
> + uint32_t user_rb_backend_disable;
> + uint32_t raster_config;
> + uint32_t raster_config_1;
> +};
> +
> +struct gb_addr_config {
> + uint16_t pipe_interleave_size;
> + uint8_t num_pipes;
> + uint8_t max_compress_frags;
> + uint8_t num_banks;
> + uint8_t num_se;
> + uint8_t num_rb_per_se;
> +};
> +
> +struct amdgpu_gfx_config {
> + unsigned max_shader_engines;
> + unsigned max_tile_pipes;
> + unsigned max_cu_per_sh;
> + unsigned max_sh_per_se;
> + unsigned max_backends_per_se;
> + unsigned max_texture_channel_caches;
> + unsigned max_gprs;
> + unsigned max_gs_threads;
> + unsigned max_hw_contexts;
> + unsigned sc_prim_fifo_size_frontend;
> + unsigned sc_prim_fifo_size_backend;
> + unsigned sc_hiz_tile_fifo_size;
> + unsigned sc_earlyz_tile_fifo_size;
> +
> + unsigned num_tile_pipes;
> + unsigned backend_enable_mask;
> + unsigned mem_max_burst_length_bytes;
> + unsigned mem_row_size_in_kb;
> + unsigned shader_engine_tile_size;
> + unsigned num_gpus;
> + unsigned multi_gpu_tile_size;
> + unsigned mc_arb_ramcfg;
> + unsigned gb_addr_config;
> + unsigned num_rbs;
> + unsigned gs_vgt_table_depth;
> + unsigned gs_prim_buffer_depth;
> +
> + uint32_t tile_mode_array[32];
> + uint32_t macrotile_mode_array[16];
> +
> + struct gb_addr_config gb_addr_config_fields;
> + struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
> +
> + /* gfx configure feature */
> + uint32_t double_offchip_lds_buf;
> + /* cached value of DB_DEBUG2 */
> + uint32_t db_debug2;
> +};
> +
> +struct amdgpu_cu_info {
> + uint32_t simd_per_cu;
> + uint32_t max_waves_per_simd;
> + uint32_t wave_front_size;
> + uint32_t max_scratch_slots_per_cu;
> + uint32_t lds_size;
> +
> + /* total active CU number */
> + uint32_t number;
> + uint32_t ao_cu_mask;
> + uint32_t ao_cu_bitmap[4][4];
> + uint32_t bitmap[4][4];
> +};
> +
> +struct amdgpu_gfx_funcs {
> + /* get the gpu clock counter */
> + uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
> + void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
> + u32 sh_num, u32 instance);
> + void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
> + uint32_t wave, uint32_t *dst, int *no_fields);
> + void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
> + uint32_t wave, uint32_t thread, uint32_t start,
> + uint32_t size, uint32_t *dst);
> + void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
> + uint32_t wave, uint32_t start, uint32_t size,
> + uint32_t *dst);
> + void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
> + u32 queue);
> +};
> +
> +struct amdgpu_ngg_buf {
> + struct amdgpu_bo *bo;
> + uint64_t gpu_addr;
> + uint32_t size;
> + uint32_t bo_size;
> +};
> +
> +enum {
> + NGG_PRIM = 0,
> + NGG_POS,
> + NGG_CNTL,
> + NGG_PARAM,
> + NGG_BUF_MAX
> +};
> +
> +struct amdgpu_ngg {
> + struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
> + uint32_t gds_reserve_addr;
> + uint32_t gds_reserve_size;
> + bool init;
> +};
> +
> +struct sq_work {
> + struct work_struct work;
> + unsigned ih_data;
> +};
> +
> +struct amdgpu_gfx {
> + struct mutex gpu_clock_mutex;
> + struct amdgpu_gfx_config config;
> + struct amdgpu_rlc rlc;
> + struct amdgpu_mec mec;
> + struct amdgpu_kiq kiq;
> + struct amdgpu_scratch scratch;
> + const struct firmware *me_fw; /* ME firmware */
> + uint32_t me_fw_version;
> + const struct firmware *pfp_fw; /* PFP firmware */
> + uint32_t pfp_fw_version;
> + const struct firmware *ce_fw; /* CE firmware */
> + uint32_t ce_fw_version;
> + const struct firmware *rlc_fw; /* RLC firmware */
> + uint32_t rlc_fw_version;
> + const struct firmware *mec_fw; /* MEC firmware */
> + uint32_t mec_fw_version;
> + const struct firmware *mec2_fw; /* MEC2 firmware */
> + uint32_t mec2_fw_version;
> + uint32_t me_feature_version;
> + uint32_t ce_feature_version;
> + uint32_t pfp_feature_version;
> + uint32_t rlc_feature_version;
> + uint32_t rlc_srlc_fw_version;
> + uint32_t rlc_srlc_feature_version;
> + uint32_t rlc_srlg_fw_version;
> + uint32_t rlc_srlg_feature_version;
> + uint32_t rlc_srls_fw_version;
> + uint32_t rlc_srls_feature_version;
> + uint32_t mec_feature_version;
> + uint32_t mec2_feature_version;
> + struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
> + unsigned num_gfx_rings;
> + struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
> + unsigned num_compute_rings;
> + struct amdgpu_irq_src eop_irq;
> + struct amdgpu_irq_src priv_reg_irq;
> + struct amdgpu_irq_src priv_inst_irq;
> + struct amdgpu_irq_src cp_ecc_error_irq;
> + struct amdgpu_irq_src sq_irq;
> + struct sq_work sq_work;
> +
> + /* gfx status */
> + uint32_t gfx_current_status;
> + /* ce ram size*/
> + unsigned ce_ram_size;
> + struct amdgpu_cu_info cu_info;
> + const struct amdgpu_gfx_funcs *funcs;
> +
> + /* reset mask */
> + uint32_t grbm_soft_reset;
> + uint32_t srbm_soft_reset;
> + /* s3/s4 mask */
> + bool in_suspend;
> + /* NGG */
> + struct amdgpu_ngg ngg;
> +
> + /* pipe reservation */
> + struct mutex pipe_reserve_mutex;
> + DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
> +};
> +
> +#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
> +#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
> +#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
>
> /**
> * amdgpu_gfx_create_bitmask - create a bitmask
> @@ -60,34 +322,33 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
> return (u32)((1ULL << bit_width) - 1);
> }
>
> -static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev,
> - int mec, int pipe, int queue)
> -{
> - int bit = 0;
> +int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
> +void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
>
> - bit += mec * adev->gfx.mec.num_pipe_per_mec
> - * adev->gfx.mec.num_queue_per_pipe;
> - bit += pipe * adev->gfx.mec.num_queue_per_pipe;
> - bit += queue;
> +void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
> + unsigned max_sh);
>
> - return bit;
> -}
> +int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
> + struct amdgpu_ring *ring,
> + struct amdgpu_irq_src *irq);
>
> -static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
> - int *mec, int *pipe, int *queue)
> -{
> - *queue = bit % adev->gfx.mec.num_queue_per_pipe;
> - *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
> - % adev->gfx.mec.num_pipe_per_mec;
> - *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
> - / adev->gfx.mec.num_pipe_per_mec;
> +void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
> + struct amdgpu_irq_src *irq);
>
> -}
> -static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
> - int mec, int pipe, int queue)
> -{
> - return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
> - adev->gfx.mec.queue_bitmap);
> -}
> +void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
> +int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
> + unsigned hpd_size);
> +
> +int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
> + unsigned mqd_size);
> +void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
> +
> +void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
> +int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
> + int pipe, int queue);
> +void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
> + int *mec, int *pipe, int *queue);
> +bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
> + int pipe, int queue);
>
> #endif
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