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From: Andi Kleen <ak@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH] SPTE masking
Date: Fri, 10 Aug 2018 10:23:41 -0700	[thread overview]
Message-ID: <20180810172341.GH4238@tassilo.jf.intel.com> (raw)
In-Reply-To: <5ed402af-86dc-cc18-16e3-fe8f50178ccd@redhat.com>

On Fri, Aug 10, 2018 at 09:55:49AM +0200, speck for Paolo Bonzini wrote:
> On 09/08/2018 19:43, speck for Andi Kleen wrote:
> >> But that would only apply to processors with
> >> MAXPHYADDR=52.
> > We don't expect those to be vulnerable to L1TF.
> > 
> > So patches are not needed I think.
> 
> Looks like they are still needed on processors with cache-maxphyaddr =
> l1tf-maxphyaddr.

Not sure I follow your definitions. What is l1tf-maxphyaddr?

Normally we have the maxphyaddr reported by CPUID, and then we
have a larger maxphyaddr which could exist because VMs are lying
(upto 46bits)

-Andi

  parent reply	other threads:[~2018-08-10 17:23 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-08 23:21 [MODERATED] [PATCH] SPTE masking Jim Mattson
2018-08-09  2:57 ` [MODERATED] " Andi Kleen
2018-08-09  9:24   ` Paolo Bonzini
2018-08-09 17:43     ` Andi Kleen
2018-08-10  7:55       ` Paolo Bonzini
2018-08-10 15:59         ` Jim Mattson
2018-08-10 17:23         ` Andi Kleen [this message]
2018-08-10 17:32           ` Linus Torvalds
2018-08-10 17:45             ` Andi Kleen
2018-08-10 18:37               ` Paolo Bonzini
2018-08-10 19:17                 ` Andi Kleen
2018-08-12 10:57                   ` Paolo Bonzini
2018-08-09  9:25 ` Paolo Bonzini
2018-08-09  9:33   ` Andrew Cooper
2018-08-09 10:01     ` Paolo Bonzini
2018-08-09 10:47       ` Andrew Cooper
2018-08-09 11:13         ` Paolo Bonzini
2018-08-09 11:46           ` Andrew Cooper
2018-08-09 11:54             ` Paolo Bonzini
2018-08-09 14:01               ` Andrew Cooper
2018-08-09 15:00                 ` Paolo Bonzini
2018-08-09 20:14       ` Jim Mattson

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