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From: Paolo Bonzini <pbonzini@redhat.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH] SPTE masking
Date: Thu, 9 Aug 2018 11:24:47 +0200	[thread overview]
Message-ID: <f793388f-0cae-4007-f4f7-0a2ce32d4376@redhat.com> (raw)
In-Reply-To: <20180809025756.GD4238@tassilo.jf.intel.com>

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On 09/08/2018 04:57, speck for Andi Kleen wrote:
>> [PATCH] kvm: x86: Set highest physical address bit in non-present/reserved SPTEs
>>
>> Always set the upper-most supported physical address bit to 1 for SPTEs
>> that are marked as non-present or reserved, to make them unusable for
>> L1TF attacks from the guest. Currently, this just applies to MMIO SPTEs.
> L1TF only works for cached memory. 
> 
> Are you concerned about cacheable MMIO?

No, he's concerned that KVM stores information in SPTEs that point to
guest MMIO (i.e. emulated devices), and that information is
guest-controlled.  But that would only apply to processors with
MAXPHYADDR=52.

Paolo


  reply	other threads:[~2018-08-09  9:24 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-08 23:21 [MODERATED] [PATCH] SPTE masking Jim Mattson
2018-08-09  2:57 ` [MODERATED] " Andi Kleen
2018-08-09  9:24   ` Paolo Bonzini [this message]
2018-08-09 17:43     ` Andi Kleen
2018-08-10  7:55       ` Paolo Bonzini
2018-08-10 15:59         ` Jim Mattson
2018-08-10 17:23         ` Andi Kleen
2018-08-10 17:32           ` Linus Torvalds
2018-08-10 17:45             ` Andi Kleen
2018-08-10 18:37               ` Paolo Bonzini
2018-08-10 19:17                 ` Andi Kleen
2018-08-12 10:57                   ` Paolo Bonzini
2018-08-09  9:25 ` Paolo Bonzini
2018-08-09  9:33   ` Andrew Cooper
2018-08-09 10:01     ` Paolo Bonzini
2018-08-09 10:47       ` Andrew Cooper
2018-08-09 11:13         ` Paolo Bonzini
2018-08-09 11:46           ` Andrew Cooper
2018-08-09 11:54             ` Paolo Bonzini
2018-08-09 14:01               ` Andrew Cooper
2018-08-09 15:00                 ` Paolo Bonzini
2018-08-09 20:14       ` Jim Mattson

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