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From: Andi Kleen <ak@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH] SPTE masking
Date: Wed, 8 Aug 2018 19:57:56 -0700	[thread overview]
Message-ID: <20180809025756.GD4238@tassilo.jf.intel.com> (raw)
In-Reply-To: <CALMp9eTY2wjoc3yZUC3PyKDVPiiGU6t2fHLUwUxGDh5C5_x+wQ@mail.gmail.com>

On Wed, Aug 08, 2018 at 04:21:14PM -0700, speck for Jim Mattson wrote:
> [PATCH] kvm: x86: Set highest physical address bit in non-present/reserved SPTEs
> 
> Always set the upper-most supported physical address bit to 1 for SPTEs
> that are marked as non-present or reserved, to make them unusable for
> L1TF attacks from the guest. Currently, this just applies to MMIO SPTEs.

L1TF only works for cached memory. 

Are you concerned about cacheable MMIO?

I didn't think it could happen.

-Andi

  reply	other threads:[~2018-08-09  2:58 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-08 23:21 [MODERATED] [PATCH] SPTE masking Jim Mattson
2018-08-09  2:57 ` Andi Kleen [this message]
2018-08-09  9:24   ` [MODERATED] " Paolo Bonzini
2018-08-09 17:43     ` Andi Kleen
2018-08-10  7:55       ` Paolo Bonzini
2018-08-10 15:59         ` Jim Mattson
2018-08-10 17:23         ` Andi Kleen
2018-08-10 17:32           ` Linus Torvalds
2018-08-10 17:45             ` Andi Kleen
2018-08-10 18:37               ` Paolo Bonzini
2018-08-10 19:17                 ` Andi Kleen
2018-08-12 10:57                   ` Paolo Bonzini
2018-08-09  9:25 ` Paolo Bonzini
2018-08-09  9:33   ` Andrew Cooper
2018-08-09 10:01     ` Paolo Bonzini
2018-08-09 10:47       ` Andrew Cooper
2018-08-09 11:13         ` Paolo Bonzini
2018-08-09 11:46           ` Andrew Cooper
2018-08-09 11:54             ` Paolo Bonzini
2018-08-09 14:01               ` Andrew Cooper
2018-08-09 15:00                 ` Paolo Bonzini
2018-08-09 20:14       ` Jim Mattson

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