* [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
Hi all,
This patch series updates the ARM NSP DTS and BCM958625HR in order to
support the SFP connected to port 5 on these reference boards.
I will be submitting the functional changes to drivers/net/dsa/b53 once
net-next opens back up, but this is largely independent from getting
these 3 patches out.
Thank you
Changes in v3:
- changes i2c controller node name from i2c to i2c (Ray)
- updated binding patch to have bulleted reg-names and interrupt-names
(Rob)
Changes in v2:
- added missing managed = "in-band-status" property
- reworded the commit message to explain the limitation of i2c-proc
is of 63 bytes per transfer, not 256 bytes
Florian Fainelli (3):
ARM: dts: NSP: Enable SFP on bcm958625hr
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
ARM: dts: NSP: Wire up switch interrupts
.../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
arch/arm/boot/dts/bcm-nsp.dtsi | 31 +++++++++++++++-
arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++
3 files changed, 92 insertions(+), 1 deletion(-)
--
2.17.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
Hi all,
This patch series updates the ARM NSP DTS and BCM958625HR in order to
support the SFP connected to port 5 on these reference boards.
I will be submitting the functional changes to drivers/net/dsa/b53 once
net-next opens back up, but this is largely independent from getting
these 3 patches out.
Thank you
Changes in v3:
- changes i2c controller node name from i2c to i2c (Ray)
- updated binding patch to have bulleted reg-names and interrupt-names
(Rob)
Changes in v2:
- added missing managed = "in-band-status" property
- reworded the commit message to explain the limitation of i2c-proc
is of 63 bytes per transfer, not 256 bytes
Florian Fainelli (3):
ARM: dts: NSP: Enable SFP on bcm958625hr
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
ARM: dts: NSP: Wire up switch interrupts
.../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
arch/arm/boot/dts/bcm-nsp.dtsi | 31 +++++++++++++++-
arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++
3 files changed, 92 insertions(+), 1 deletion(-)
--
2.17.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series updates the ARM NSP DTS and BCM958625HR in order to
support the SFP connected to port 5 on these reference boards.
I will be submitting the functional changes to drivers/net/dsa/b53 once
net-next opens back up, but this is largely independent from getting
these 3 patches out.
Thank you
Changes in v3:
- changes i2c controller node name from i2c to i2c (Ray)
- updated binding patch to have bulleted reg-names and interrupt-names
(Rob)
Changes in v2:
- added missing managed = "in-band-status" property
- reworded the commit message to explain the limitation of i2c-proc
is of 63 bytes per transfer, not 256 bytes
Florian Fainelli (3):
ARM: dts: NSP: Enable SFP on bcm958625hr
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
ARM: dts: NSP: Wire up switch interrupts
.../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
arch/arm/boot/dts/bcm-nsp.dtsi | 31 +++++++++++++++-
arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++
3 files changed, 92 insertions(+), 1 deletion(-)
--
2.17.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 1/3] ARM: dts: NSP: Enable SFP on bcm958625hr
2018-08-31 19:20 ` Florian Fainelli
(?)
@ 2018-08-31 19:20 ` Florian Fainelli
-1 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
Enable the SFP connected to port 5 of the switch and wire up all GPIOs
to the SFP cage. Because of a hardware limitation of the i2c controller
on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
work, we use the i2c-gpio interface instead, which does not have that
limitation. This allows us to read the SFP module EEPROM, which would
not be possible otherwise since it exceeds that size during a single
read transfer.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index ea3fc194f8f3..a53a2f629d74 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -58,6 +58,24 @@
open-source;
priority = <200>;
};
+
+ /* Hardware I2C block cannot do more than 63 bytes per transfer,
+ * which would prevent reading from a SFP's EEPROM (256 byte).
+ */
+ i2c1: i2c {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
+ los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
+ };
};
&amac0 {
@@ -210,6 +228,14 @@
reg = <4>;
};
+ port@5 {
+ label = "sfp";
+ phy-mode = "sgmii";
+ reg = <5>;
+ sfp = <&sfp>;
+ managed = "in-band-status";
+ };
+
port@8 {
ethernet = <&amac2>;
label = "cpu";
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 1/3] ARM: dts: NSP: Enable SFP on bcm958625hr
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
Enable the SFP connected to port 5 of the switch and wire up all GPIOs
to the SFP cage. Because of a hardware limitation of the i2c controller
on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
work, we use the i2c-gpio interface instead, which does not have that
limitation. This allows us to read the SFP module EEPROM, which would
not be possible otherwise since it exceeds that size during a single
read transfer.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index ea3fc194f8f3..a53a2f629d74 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -58,6 +58,24 @@
open-source;
priority = <200>;
};
+
+ /* Hardware I2C block cannot do more than 63 bytes per transfer,
+ * which would prevent reading from a SFP's EEPROM (256 byte).
+ */
+ i2c1: i2c {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
+ los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
+ };
};
&amac0 {
@@ -210,6 +228,14 @@
reg = <4>;
};
+ port@5 {
+ label = "sfp";
+ phy-mode = "sgmii";
+ reg = <5>;
+ sfp = <&sfp>;
+ managed = "in-band-status";
+ };
+
port@8 {
ethernet = <&amac2>;
label = "cpu";
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 1/3] ARM: dts: NSP: Enable SFP on bcm958625hr
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Enable the SFP connected to port 5 of the switch and wire up all GPIOs
to the SFP cage. Because of a hardware limitation of the i2c controller
on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
work, we use the i2c-gpio interface instead, which does not have that
limitation. This allows us to read the SFP module EEPROM, which would
not be possible otherwise since it exceeds that size during a single
read transfer.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index ea3fc194f8f3..a53a2f629d74 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -58,6 +58,24 @@
open-source;
priority = <200>;
};
+
+ /* Hardware I2C block cannot do more than 63 bytes per transfer,
+ * which would prevent reading from a SFP's EEPROM (256 byte).
+ */
+ i2c1: i2c {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
+ los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
+ };
};
&amac0 {
@@ -210,6 +228,14 @@
reg = <4>;
};
+ port at 5 {
+ label = "sfp";
+ phy-mode = "sgmii";
+ reg = <5>;
+ sfp = <&sfp>;
+ managed = "in-band-status";
+ };
+
port at 8 {
ethernet = <&amac2>;
label = "cpu";
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
2018-08-31 19:20 ` Florian Fainelli
(?)
@ 2018-08-31 19:20 ` Florian Fainelli
-1 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
Document the Broadcom roboswitch Switch Register Access Block interrupt
lines and additional register base addresses for port mux configuration
and SGMII status/configuration registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
index 1811e1972a7a..5201bc15fdd6 100644
--- a/Documentation/devicetree/bindings/net/dsa/b53.txt
+++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
@@ -46,6 +46,42 @@ Required properties:
"brcm,bcm6328-switch"
"brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
+Required properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg: a total of 3 register base addresses, the first one must be the
+ Switch Register Access block base, the second is the port 5/4 mux
+ configuration register and the third one is the SGMII configuration
+ and status register base address.
+
+ - interrupts: a total of 13 interrupts must be specified, in the following
+ order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
+ then the timestamping interrupt and the sleep timer interrupts for ports
+ 5,7,8.
+
+Optional properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg-names: a total of 3 names matching the 3 base register address, must
+ be in the following order:
+ "srab"
+ "mux_config"
+ "sgmii_config"
+
+ - interrupt-names: a total of 13 names matching the 13 interrupts specified
+ must be in the following order:
+ "link_state_p0"
+ "link_state_p1"
+ "link_state_p2"
+ "link_state_p3"
+ "link_state_p4"
+ "link_state_p5"
+ "link_state_p7"
+ "link_state_p8"
+ "phy"
+ "ts"
+ "imp_sleep_timer_p5"
+ "imp_sleep_timer_p7"
+ "imp_sleep_timer_p8"
+
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
Document the Broadcom roboswitch Switch Register Access Block interrupt
lines and additional register base addresses for port mux configuration
and SGMII status/configuration registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
index 1811e1972a7a..5201bc15fdd6 100644
--- a/Documentation/devicetree/bindings/net/dsa/b53.txt
+++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
@@ -46,6 +46,42 @@ Required properties:
"brcm,bcm6328-switch"
"brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
+Required properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg: a total of 3 register base addresses, the first one must be the
+ Switch Register Access block base, the second is the port 5/4 mux
+ configuration register and the third one is the SGMII configuration
+ and status register base address.
+
+ - interrupts: a total of 13 interrupts must be specified, in the following
+ order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
+ then the timestamping interrupt and the sleep timer interrupts for ports
+ 5,7,8.
+
+Optional properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg-names: a total of 3 names matching the 3 base register address, must
+ be in the following order:
+ "srab"
+ "mux_config"
+ "sgmii_config"
+
+ - interrupt-names: a total of 13 names matching the 13 interrupts specified
+ must be in the following order:
+ "link_state_p0"
+ "link_state_p1"
+ "link_state_p2"
+ "link_state_p3"
+ "link_state_p4"
+ "link_state_p5"
+ "link_state_p7"
+ "link_state_p8"
+ "phy"
+ "ts"
+ "imp_sleep_timer_p5"
+ "imp_sleep_timer_p7"
+ "imp_sleep_timer_p8"
+
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Document the Broadcom roboswitch Switch Register Access Block interrupt
lines and additional register base addresses for port mux configuration
and SGMII status/configuration registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
index 1811e1972a7a..5201bc15fdd6 100644
--- a/Documentation/devicetree/bindings/net/dsa/b53.txt
+++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
@@ -46,6 +46,42 @@ Required properties:
"brcm,bcm6328-switch"
"brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
+Required properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg: a total of 3 register base addresses, the first one must be the
+ Switch Register Access block base, the second is the port 5/4 mux
+ configuration register and the third one is the SGMII configuration
+ and status register base address.
+
+ - interrupts: a total of 13 interrupts must be specified, in the following
+ order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
+ then the timestamping interrupt and the sleep timer interrupts for ports
+ 5,7,8.
+
+Optional properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg-names: a total of 3 names matching the 3 base register address, must
+ be in the following order:
+ "srab"
+ "mux_config"
+ "sgmii_config"
+
+ - interrupt-names: a total of 13 names matching the 13 interrupts specified
+ must be in the following order:
+ "link_state_p0"
+ "link_state_p1"
+ "link_state_p2"
+ "link_state_p3"
+ "link_state_p4"
+ "link_state_p5"
+ "link_state_p7"
+ "link_state_p8"
+ "phy"
+ "ts"
+ "imp_sleep_timer_p5"
+ "imp_sleep_timer_p7"
+ "imp_sleep_timer_p8"
+
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/3] ARM: dts: NSP: Wire up switch interrupts
2018-08-31 19:20 ` Florian Fainelli
(?)
@ 2018-08-31 19:20 ` Florian Fainelli
-1 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
The Switch Register Access Block (SRAB) has one interrupt for link state
change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
and sleep timer interrupts for each management ports (5,7,8). Wire those
up so we can utilize them to speed up link resolution.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 09ba85046322..ec869a80f9ba 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -377,7 +377,36 @@
srab: srab@36000 {
compatible = "brcm,nsp-srab";
- reg = <0x36000 0x1000>;
+ reg = <0x36000 0x1000>,
+ <0x3f308 0x8>,
+ <0x3f410 0xc>;
+ reg-names = "srab", "mux_config", "sgmii";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "link_state_p0",
+ "link_state_p1",
+ "link_state_p2",
+ "link_state_p3",
+ "link_state_p4",
+ "link_state_p5",
+ "link_state_p7",
+ "link_state_p8",
+ "phy",
+ "ts",
+ "imp_sleep_timer_p5",
+ "imp_sleep_timer_p7",
+ "imp_sleep_timer_p8";
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/3] ARM: dts: NSP: Wire up switch interrupts
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Rob Herring, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
The Switch Register Access Block (SRAB) has one interrupt for link state
change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
and sleep timer interrupts for each management ports (5,7,8). Wire those
up so we can utilize them to speed up link resolution.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 09ba85046322..ec869a80f9ba 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -377,7 +377,36 @@
srab: srab@36000 {
compatible = "brcm,nsp-srab";
- reg = <0x36000 0x1000>;
+ reg = <0x36000 0x1000>,
+ <0x3f308 0x8>,
+ <0x3f410 0xc>;
+ reg-names = "srab", "mux_config", "sgmii";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "link_state_p0",
+ "link_state_p1",
+ "link_state_p2",
+ "link_state_p3",
+ "link_state_p4",
+ "link_state_p5",
+ "link_state_p7",
+ "link_state_p8",
+ "phy",
+ "ts",
+ "imp_sleep_timer_p5",
+ "imp_sleep_timer_p7",
+ "imp_sleep_timer_p8";
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/3] ARM: dts: NSP: Wire up switch interrupts
@ 2018-08-31 19:20 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-08-31 19:20 UTC (permalink / raw)
To: linux-arm-kernel
The Switch Register Access Block (SRAB) has one interrupt for link state
change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
and sleep timer interrupts for each management ports (5,7,8). Wire those
up so we can utilize them to speed up link resolution.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 09ba85046322..ec869a80f9ba 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -377,7 +377,36 @@
srab: srab at 36000 {
compatible = "brcm,nsp-srab";
- reg = <0x36000 0x1000>;
+ reg = <0x36000 0x1000>,
+ <0x3f308 0x8>,
+ <0x3f410 0xc>;
+ reg-names = "srab", "mux_config", "sgmii";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "link_state_p0",
+ "link_state_p1",
+ "link_state_p2",
+ "link_state_p3",
+ "link_state_p4",
+ "link_state_p5",
+ "link_state_p7",
+ "link_state_p8",
+ "phy",
+ "ts",
+ "imp_sleep_timer_p5",
+ "imp_sleep_timer_p7",
+ "imp_sleep_timer_p8";
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/3] ARM: dts: NSP: Enable SFP on bcm958625hr
2018-08-31 19:20 ` Florian Fainelli
(?)
@ 2018-09-04 20:39 ` Ray Jui
-1 siblings, 0 replies; 21+ messages in thread
From: Ray Jui @ 2018-09-04 20:39 UTC (permalink / raw)
To: Florian Fainelli, linux-arm-kernel
Cc: Rob Herring, Mark Rutland, Ray Jui, Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
On 8/31/2018 12:20 PM, Florian Fainelli wrote:
> Enable the SFP connected to port 5 of the switch and wire up all GPIOs
> to the SFP cage. Because of a hardware limitation of the i2c controller
> on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
> work, we use the i2c-gpio interface instead, which does not have that
> limitation. This allows us to read the SFP module EEPROM, which would
> not be possible otherwise since it exceeds that size during a single
> read transfer.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
> index ea3fc194f8f3..a53a2f629d74 100644
> --- a/arch/arm/boot/dts/bcm958625hr.dts
> +++ b/arch/arm/boot/dts/bcm958625hr.dts
> @@ -58,6 +58,24 @@
> open-source;
> priority = <200>;
> };
> +
> + /* Hardware I2C block cannot do more than 63 bytes per transfer,
> + * which would prevent reading from a SFP's EEPROM (256 byte).
> + */
> + i2c1: i2c {
> + compatible = "i2c-gpio";
> + sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + };
> +
> + sfp: sfp {
> + compatible = "sff,sfp";
> + i2c-bus = <&i2c1>;
> + mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
> + los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
> + tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
> + tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
> + };
> };
>
> &amac0 {
> @@ -210,6 +228,14 @@
> reg = <4>;
> };
>
> + port@5 {
> + label = "sfp";
> + phy-mode = "sgmii";
> + reg = <5>;
> + sfp = <&sfp>;
> + managed = "in-band-status";
> + };
> +
> port@8 {
> ethernet = <&amac2>;
> label = "cpu";
>
Looks good to me. Thanks!
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/3] ARM: dts: NSP: Enable SFP on bcm958625hr
@ 2018-09-04 20:39 ` Ray Jui
0 siblings, 0 replies; 21+ messages in thread
From: Ray Jui @ 2018-09-04 20:39 UTC (permalink / raw)
To: Florian Fainelli, linux-arm-kernel
Cc: Rob Herring, Mark Rutland, Ray Jui, Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
On 8/31/2018 12:20 PM, Florian Fainelli wrote:
> Enable the SFP connected to port 5 of the switch and wire up all GPIOs
> to the SFP cage. Because of a hardware limitation of the i2c controller
> on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
> work, we use the i2c-gpio interface instead, which does not have that
> limitation. This allows us to read the SFP module EEPROM, which would
> not be possible otherwise since it exceeds that size during a single
> read transfer.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
> index ea3fc194f8f3..a53a2f629d74 100644
> --- a/arch/arm/boot/dts/bcm958625hr.dts
> +++ b/arch/arm/boot/dts/bcm958625hr.dts
> @@ -58,6 +58,24 @@
> open-source;
> priority = <200>;
> };
> +
> + /* Hardware I2C block cannot do more than 63 bytes per transfer,
> + * which would prevent reading from a SFP's EEPROM (256 byte).
> + */
> + i2c1: i2c {
> + compatible = "i2c-gpio";
> + sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + };
> +
> + sfp: sfp {
> + compatible = "sff,sfp";
> + i2c-bus = <&i2c1>;
> + mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
> + los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
> + tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
> + tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
> + };
> };
>
> &amac0 {
> @@ -210,6 +228,14 @@
> reg = <4>;
> };
>
> + port@5 {
> + label = "sfp";
> + phy-mode = "sgmii";
> + reg = <5>;
> + sfp = <&sfp>;
> + managed = "in-band-status";
> + };
> +
> port@8 {
> ethernet = <&amac2>;
> label = "cpu";
>
Looks good to me. Thanks!
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 1/3] ARM: dts: NSP: Enable SFP on bcm958625hr
@ 2018-09-04 20:39 ` Ray Jui
0 siblings, 0 replies; 21+ messages in thread
From: Ray Jui @ 2018-09-04 20:39 UTC (permalink / raw)
To: linux-arm-kernel
On 8/31/2018 12:20 PM, Florian Fainelli wrote:
> Enable the SFP connected to port 5 of the switch and wire up all GPIOs
> to the SFP cage. Because of a hardware limitation of the i2c controller
> on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
> work, we use the i2c-gpio interface instead, which does not have that
> limitation. This allows us to read the SFP module EEPROM, which would
> not be possible otherwise since it exceeds that size during a single
> read transfer.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/boot/dts/bcm958625hr.dts | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
> index ea3fc194f8f3..a53a2f629d74 100644
> --- a/arch/arm/boot/dts/bcm958625hr.dts
> +++ b/arch/arm/boot/dts/bcm958625hr.dts
> @@ -58,6 +58,24 @@
> open-source;
> priority = <200>;
> };
> +
> + /* Hardware I2C block cannot do more than 63 bytes per transfer,
> + * which would prevent reading from a SFP's EEPROM (256 byte).
> + */
> + i2c1: i2c {
> + compatible = "i2c-gpio";
> + sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + };
> +
> + sfp: sfp {
> + compatible = "sff,sfp";
> + i2c-bus = <&i2c1>;
> + mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
> + los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
> + tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
> + tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
> + };
> };
>
> &amac0 {
> @@ -210,6 +228,14 @@
> reg = <4>;
> };
>
> + port at 5 {
> + label = "sfp";
> + phy-mode = "sgmii";
> + reg = <5>;
> + sfp = <&sfp>;
> + managed = "in-band-status";
> + };
> +
> port at 8 {
> ethernet = <&amac2>;
> label = "cpu";
>
Looks good to me. Thanks!
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
2018-08-31 19:20 ` Florian Fainelli
(?)
@ 2018-09-10 19:57 ` Rob Herring
-1 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2018-09-10 19:57 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-arm-kernel, Florian Fainelli, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
On Fri, 31 Aug 2018 12:20:38 -0700, Florian Fainelli wrote:
> Document the Broadcom roboswitch Switch Register Access Block interrupt
> lines and additional register base addresses for port mux configuration
> and SGMII status/configuration registers.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
@ 2018-09-10 19:57 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2018-09-10 19:57 UTC (permalink / raw)
Cc: linux-arm-kernel, Florian Fainelli, Mark Rutland, Ray Jui,
Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
On Fri, 31 Aug 2018 12:20:38 -0700, Florian Fainelli wrote:
> Document the Broadcom roboswitch Switch Register Access Block interrupt
> lines and additional register base addresses for port mux configuration
> and SGMII status/configuration registers.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
@ 2018-09-10 19:57 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2018-09-10 19:57 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 31 Aug 2018 12:20:38 -0700, Florian Fainelli wrote:
> Document the Broadcom roboswitch Switch Register Access Block interrupt
> lines and additional register base addresses for port mux configuration
> and SGMII status/configuration registers.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../devicetree/bindings/net/dsa/b53.txt | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP
2018-08-31 19:20 ` Florian Fainelli
(?)
@ 2018-09-13 18:10 ` Florian Fainelli
-1 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-09-13 18:10 UTC (permalink / raw)
To: Florian Fainelli, linux-arm-kernel
Cc: Rob Herring, Mark Rutland, Ray Jui, Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
On 08/31/18 12:20, Florian Fainelli wrote:
> Hi all,
>
> This patch series updates the ARM NSP DTS and BCM958625HR in order to
> support the SFP connected to port 5 on these reference boards.
>
> I will be submitting the functional changes to drivers/net/dsa/b53 once
> net-next opens back up, but this is largely independent from getting
> these 3 patches out.
Series applied to devicetree/next.
--
Florian
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP
@ 2018-09-13 18:10 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-09-13 18:10 UTC (permalink / raw)
To: Florian Fainelli, linux-arm-kernel
Cc: Rob Herring, Mark Rutland, Ray Jui, Scott Branden, Jon Mason,
maintainer:BROADCOM IPROC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, andrew, rmk+kernel
On 08/31/18 12:20, Florian Fainelli wrote:
> Hi all,
>
> This patch series updates the ARM NSP DTS and BCM958625HR in order to
> support the SFP connected to port 5 on these reference boards.
>
> I will be submitting the functional changes to drivers/net/dsa/b53 once
> net-next opens back up, but this is largely independent from getting
> these 3 patches out.
Series applied to devicetree/next.
--
Florian
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP
@ 2018-09-13 18:10 ` Florian Fainelli
0 siblings, 0 replies; 21+ messages in thread
From: Florian Fainelli @ 2018-09-13 18:10 UTC (permalink / raw)
To: linux-arm-kernel
On 08/31/18 12:20, Florian Fainelli wrote:
> Hi all,
>
> This patch series updates the ARM NSP DTS and BCM958625HR in order to
> support the SFP connected to port 5 on these reference boards.
>
> I will be submitting the functional changes to drivers/net/dsa/b53 once
> net-next opens back up, but this is largely independent from getting
> these 3 patches out.
Series applied to devicetree/next.
--
Florian
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2018-09-13 18:10 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-31 19:20 [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-08-31 19:20 ` [PATCH v3 1/3] ARM: dts: NSP: Enable SFP on bcm958625hr Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-09-04 20:39 ` Ray Jui
2018-09-04 20:39 ` Ray Jui
2018-09-04 20:39 ` Ray Jui
2018-08-31 19:20 ` [PATCH v3 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-09-10 19:57 ` Rob Herring
2018-09-10 19:57 ` Rob Herring
2018-09-10 19:57 ` Rob Herring
2018-08-31 19:20 ` [PATCH v3 3/3] ARM: dts: NSP: Wire up switch interrupts Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-08-31 19:20 ` Florian Fainelli
2018-09-13 18:10 ` [PATCH v3 0/3] ARM: NSP updates to support switch interrupts/SFP Florian Fainelli
2018-09-13 18:10 ` Florian Fainelli
2018-09-13 18:10 ` Florian Fainelli
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