From: Christoph Hellwig <hch@infradead.org>
To: Atish Patra <atish.patra@wdc.com>
Cc: palmer@sifive.com, linux-riscv@lists.infradead.org,
hch@infradead.org, anup@brainfault.org, mark.rutland@arm.com,
Damien.LeMoal@wdc.com, jason@lakedaemon.net,
ard.biesheuvel@linaro.org, marc.zyngier@arm.com,
gregkh@linuxfoundation.org, dmitriy@oss-tech.org,
linux-kernel@vger.kernel.org, jeremy.linton@arm.com,
catalin.marinas@arm.com, tglx@linutronix.de
Subject: Re: [PATCH v3 04/12] RISC-V: Disable preemption before enabling interrupts
Date: Mon, 10 Sep 2018 04:24:43 -0700 [thread overview]
Message-ID: <20180910112443.GD12979@infradead.org> (raw)
In-Reply-To: <1536221135-182613-5-git-send-email-atish.patra@wdc.com>
On Thu, Sep 06, 2018 at 01:05:27AM -0700, Atish Patra wrote:
> Currently, irq is enabled before preemption disabling happens.
> If the scheduler fired right here and cpu is scheduled then it
> may blow up.
>
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
> [Atish: Commit text and code comment formatting update]
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
Looks good,
Reviewed-by: Christoph Hellwig <hch@lst.de>
WARNING: multiple messages have this Message-ID (diff)
From: hch@infradead.org (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH v3 04/12] RISC-V: Disable preemption before enabling interrupts
Date: Mon, 10 Sep 2018 04:24:43 -0700 [thread overview]
Message-ID: <20180910112443.GD12979@infradead.org> (raw)
In-Reply-To: <1536221135-182613-5-git-send-email-atish.patra@wdc.com>
On Thu, Sep 06, 2018 at 01:05:27AM -0700, Atish Patra wrote:
> Currently, irq is enabled before preemption disabling happens.
> If the scheduler fired right here and cpu is scheduled then it
> may blow up.
>
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
> [Atish: Commit text and code comment formatting update]
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
Looks good,
Reviewed-by: Christoph Hellwig <hch@lst.de>
next prev parent reply other threads:[~2018-09-10 11:24 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-06 8:05 [PATCH v3 00/12] SMP cleanup and new features Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-06 8:05 ` [PATCH v3 01/12] RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} Atish Patra
2018-09-06 8:05 ` [PATCH v3 01/12] RISC-V: Don't set cacheinfo.{physical_line_partition, attributes} Atish Patra
2018-09-06 8:05 ` [PATCH v3 02/12] RISC-V: Filter ISA and MMU values in cpuinfo Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:24 ` Christoph Hellwig
2018-09-10 11:24 ` Christoph Hellwig
2018-09-11 1:35 ` Atish Patra
2018-09-11 1:35 ` Atish Patra
2018-09-06 8:05 ` [PATCH v3 03/12] RISC-V: Comment on the TLB flush in smp_callin() Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:24 ` Christoph Hellwig
2018-09-10 11:24 ` Christoph Hellwig
2018-09-06 8:05 ` [PATCH v3 04/12] RISC-V: Disable preemption before enabling interrupts Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:24 ` Christoph Hellwig [this message]
2018-09-10 11:24 ` Christoph Hellwig
2018-09-06 8:05 ` [PATCH v3 05/12] RISC-V: Provide a cleaner raw_smp_processor_id() Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:25 ` Christoph Hellwig
2018-09-10 11:25 ` Christoph Hellwig
2018-09-06 8:05 ` [PATCH v3 06/12] RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:25 ` Christoph Hellwig
2018-09-10 11:25 ` Christoph Hellwig
2018-09-11 1:36 ` Atish Patra
2018-09-11 1:36 ` Atish Patra
2018-09-11 6:17 ` Christoph Hellwig
2018-09-11 6:17 ` Christoph Hellwig
2018-09-06 8:05 ` [PATCH v3 07/12] RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:26 ` Christoph Hellwig
2018-09-10 11:26 ` Christoph Hellwig
2018-09-06 8:05 ` [PATCH v3 08/12] RISC-V: Use mmgrab() Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-06 8:05 ` [PATCH v3 09/12] RISC-V: User WRITE_ONCE instead of direct access Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:27 ` Christoph Hellwig
2018-09-10 11:27 ` Christoph Hellwig
2018-09-06 8:05 ` [PATCH v3 10/12] RISC-V: Add logical CPU indexing for RISC-V Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:27 ` Christoph Hellwig
2018-09-10 11:27 ` Christoph Hellwig
2018-09-06 8:05 ` [PATCH v3 11/12] RISC-V: Use Linux logical cpu number instead of hartid Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-10 11:29 ` Christoph Hellwig
2018-09-10 11:29 ` Christoph Hellwig
2018-09-11 1:35 ` Atish Patra
2018-09-11 1:35 ` Atish Patra
2018-09-06 8:05 ` [PATCH v3 12/12] RISC-V: Support cpu hotplug Atish Patra
2018-09-06 8:05 ` Atish Patra
2018-09-06 10:20 ` Mark Rutland
2018-09-06 10:20 ` Mark Rutland
2018-09-06 18:25 ` Atish Patra
2018-09-06 18:25 ` Atish Patra
2018-09-11 18:36 ` Atish Patra
2018-09-11 18:36 ` Atish Patra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180910112443.GD12979@infradead.org \
--to=hch@infradead.org \
--cc=Damien.LeMoal@wdc.com \
--cc=anup@brainfault.org \
--cc=ard.biesheuvel@linaro.org \
--cc=atish.patra@wdc.com \
--cc=catalin.marinas@arm.com \
--cc=dmitriy@oss-tech.org \
--cc=gregkh@linuxfoundation.org \
--cc=jason@lakedaemon.net \
--cc=jeremy.linton@arm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=palmer@sifive.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.