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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>,
	Anusha Srivatsa <anusha.srivatsa@intel.com>
Subject: [PATCH v4 01/25] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
Date: Tue, 11 Sep 2018 17:55:43 -0700	[thread overview]
Message-ID: <20180912005607.29522-2-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20180912005607.29522-1-manasi.d.navare@intel.com>

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.

Credits to Manasi for noticing bSpec change.

Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c80e56959e21..6de15f781090 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10638,6 +10638,7 @@ enum skl_power_gate {
 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
 
-- 
2.18.0

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  reply	other threads:[~2018-09-12  0:55 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-12  0:55 [PATCH v4 00/25] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-09-12  0:55 ` Manasi Navare [this message]
2018-09-12  0:55 ` [PATCH v4 02/25] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-09-12 13:42   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 03/25] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-09-12  0:55 ` [PATCH v4 04/25] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-09-12 14:32   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 05/25] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-09-14  5:31   ` Singh, Gaurav K
2018-09-14  5:57   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 06/25] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-09-14  6:45   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 07/25] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-09-12  0:55 ` [PATCH v4 08/25] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-09-12  0:55 ` [PATCH v4 09/25] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-09-12  0:55 ` [PATCH v4 10/25] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-09-12  0:55 ` [PATCH v4 11/25] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-09-12  0:55 ` [PATCH v4 12/25] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-09-12  0:55 ` [PATCH v4 13/25] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-09-12  0:55 ` [PATCH v4 14/25] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-09-12  0:55 ` [PATCH v4 15/25] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-09-12  0:55 ` [PATCH v4 16/25] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-09-12  0:55 ` [PATCH v4 17/25] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-09-12  0:56 ` [PATCH v4 18/25] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-09-12  0:56 ` [PATCH v4 19/25] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-09-12 19:09   ` [Intel-gfx] " Rodrigo Vivi
2018-09-14 10:55   ` Imre Deak
2018-09-18 19:04     ` Manasi Navare
2018-09-18 19:12       ` Ville Syrjälä
2018-09-18 19:31         ` Manasi Navare
2018-09-18 19:46           ` Ville Syrjälä
2018-09-18 21:10             ` Manasi Navare
2018-09-19 10:57               ` Ville Syrjälä
2018-09-21  8:34                 ` Manasi Navare
2018-09-21 13:46                   ` Ville Syrjälä
2018-10-01  9:35                     ` Imre Deak
2018-10-01 18:32                       ` [Intel-gfx] " Runyan, Arthur J
2018-10-02 11:45                         ` Imre Deak
2018-10-02 18:20                           ` Manasi Navare
2018-10-01  9:45       ` Imre Deak
2018-09-12  0:56 ` [PATCH v4 20/25] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-09-12  0:56 ` [PATCH v4 21/25] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-09-12  0:56 ` [PATCH v4 22/25] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-09-12  0:56 ` [PATCH v4 23/25] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-09-12  0:56 ` [PATCH v4 24/25] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-09-12  0:56 ` [PATCH v4 25/25] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-09-12  1:24 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev4) Patchwork
2018-09-12  1:33 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-09-12  1:41 ` ✗ Fi.CI.BAT: failure " Patchwork

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