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From: Patchwork <patchwork@emeril.freedesktop.org>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP (rev4)
Date: Wed, 12 Sep 2018 01:41:39 -0000	[thread overview]
Message-ID: <20180912014139.24566.20664@emeril.freedesktop.org> (raw)
In-Reply-To: <20180912005607.29522-1-manasi.d.navare@intel.com>

== Series Details ==

Series: Display Stream Compression enabling on eDP/DP (rev4)
URL   : https://patchwork.freedesktop.org/series/47514/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4806 -> Patchwork_10145 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10145 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10145, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47514/revisions/4/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10145:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_module_reload@basic-reload:
      fi-icl-u:           NOTRUN -> DMESG-WARN +21

    
    ==== Warnings ====

    igt@gem_exec_suspend@basic-s3:
      fi-icl-u:           INCOMPLETE (fdo#107901) -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_10145 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#107341)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_psr@primary_page_flip:
      fi-kbl-7560u:       PASS -> FAIL (fdo#107336)

    
    ==== Possible fixes ====

    igt@amdgpu/amd_basic@userptr:
      fi-kbl-8809g:       INCOMPLETE (fdo#107402) -> PASS

    igt@gem_exec_suspend@basic-s3:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     FAIL (fdo#103191, fdo#107362) -> PASS

    igt@prime_vgem@basic-fence-flip:
      fi-ilk-650:         FAIL (fdo#104008) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107901 https://bugs.freedesktop.org/show_bug.cgi?id=107901


== Participating hosts (49 -> 44) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4806 -> Patchwork_10145

  CI_DRM_4806: feeccde66999c5e87be3550f2159e5d7eeb61c67 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10145: d52012c3f51f135735abe1050b133bd2dc88daef @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d52012c3f51f drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
7adbcfab9358 drm/i915/dp: Configure Display stream splitter registers during DSC enable
667d667fcc32 drm/i915/icl: Add Display Stream Splitter control registers
ebfeb6c84440 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
d81afaa3f3af drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
f31be5cedd0e drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
36a228201d7c drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
2e8d374ecf60 drm/i915/dp: Enable/Disable DSC in DP Sink
364395179414 drm/i915/dsc: Compute Rate Control parameters for DSC
2dc4510a94cf drm/i915/dsc: Define & Compute VESA DSC params
6071851e78f6 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
6505ec03ee07 drm/i915/dp: Do not enable PSR2 if DSC is enabled
a269e9cbb0cb drm/i915/dp: Compute DSC pipe config in atomic check
c373898f4090 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
b37f405578b5 drm/dsc: Add helpers for DSC picture parameter set infoframes
2fa50580e540 drm/dsc: Define Rate Control values that do not change over configurations
3f646b2cd07d drm/dsc: Define VESA Display Stream Compression Capabilities
80275c56167e drm/dsc: Define Display Stream Compression PPS infoframe
91e0ef49ef5f drm/dp: Define payload size for DP SDP PPS packet
3229480fcf42 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
b05fa7e9e1c0 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
3d7e87c20a5e drm/dp: DRM DP helper/macros to get DP sink DSC parameters
23db8f3fa417 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
f1feaec457cc drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
c28404862aa9 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10145/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      parent reply	other threads:[~2018-09-12  1:41 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-12  0:55 [PATCH v4 00/25] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-09-12  0:55 ` [PATCH v4 01/25] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-09-12  0:55 ` [PATCH v4 02/25] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-09-12 13:42   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 03/25] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-09-12  0:55 ` [PATCH v4 04/25] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-09-12 14:32   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 05/25] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-09-14  5:31   ` Singh, Gaurav K
2018-09-14  5:57   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 06/25] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-09-14  6:45   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 07/25] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-09-12  0:55 ` [PATCH v4 08/25] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-09-12  0:55 ` [PATCH v4 09/25] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-09-12  0:55 ` [PATCH v4 10/25] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-09-12  0:55 ` [PATCH v4 11/25] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-09-12  0:55 ` [PATCH v4 12/25] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-09-12  0:55 ` [PATCH v4 13/25] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-09-12  0:55 ` [PATCH v4 14/25] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-09-12  0:55 ` [PATCH v4 15/25] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-09-12  0:55 ` [PATCH v4 16/25] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-09-12  0:55 ` [PATCH v4 17/25] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-09-12  0:56 ` [PATCH v4 18/25] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-09-12  0:56 ` [PATCH v4 19/25] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-09-12 19:09   ` [Intel-gfx] " Rodrigo Vivi
2018-09-14 10:55   ` Imre Deak
2018-09-18 19:04     ` Manasi Navare
2018-09-18 19:12       ` Ville Syrjälä
2018-09-18 19:31         ` Manasi Navare
2018-09-18 19:46           ` Ville Syrjälä
2018-09-18 21:10             ` Manasi Navare
2018-09-19 10:57               ` Ville Syrjälä
2018-09-21  8:34                 ` Manasi Navare
2018-09-21 13:46                   ` Ville Syrjälä
2018-10-01  9:35                     ` Imre Deak
2018-10-01 18:32                       ` [Intel-gfx] " Runyan, Arthur J
2018-10-02 11:45                         ` Imre Deak
2018-10-02 18:20                           ` Manasi Navare
2018-10-01  9:45       ` Imre Deak
2018-09-12  0:56 ` [PATCH v4 20/25] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-09-12  0:56 ` [PATCH v4 21/25] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-09-12  0:56 ` [PATCH v4 22/25] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-09-12  0:56 ` [PATCH v4 23/25] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-09-12  0:56 ` [PATCH v4 24/25] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-09-12  0:56 ` [PATCH v4 25/25] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-09-12  1:24 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev4) Patchwork
2018-09-12  1:33 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-09-12  1:41 ` Patchwork [this message]

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