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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH v4 19/25] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Date: Tue, 11 Sep 2018 17:56:01 -0700	[thread overview]
Message-ID: <20180912005607.29522-20-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20180912005607.29522-1-manasi.d.navare@intel.com>

On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_display.h    |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++------
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 3fe52788b4cf..bef71d27cdfe 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -256,6 +256,7 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
 	POWER_DOMAIN_INIT,
+	POWER_DOMAIN_VDSC_EDP_MIPI,
 
 	POWER_DOMAIN_NUM,
 };
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 480dadb1047b..146e2d6cf954 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -146,6 +146,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "MODESET";
 	case POWER_DOMAIN_GT_IRQ:
 		return "GT_IRQ";
+	case POWER_DOMAIN_VDSC_EDP_MIPI:
+		return "VDSC_EDP_MIPI";
 	default:
 		MISSING_CASE(domain);
 		return "?";
@@ -1966,18 +1968,16 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
 	/*
-	 * - transcoder WD
-	 * - KVMR (HW control)
+ 	 * - eDP/MIPI DSI VDSC
 	 */
 #define ICL_PW_2_POWER_DOMAINS (			\
-	ICL_PW_3_POWER_DOMAINS |			\
-	BIT_ULL(POWER_DOMAIN_INIT))
+	BIT_ULL(POWER_DOMAIN_VDSC_EDP_MIPI))
 	/*
-	 * - eDP/DSI VDSC
+	 * - transcoder WD
 	 * - KVMR (HW control)
 	 */
 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
-	ICL_PW_2_POWER_DOMAINS |			\
+	ICL_PW_3_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
-- 
2.18.0

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  parent reply	other threads:[~2018-09-12  0:56 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-12  0:55 [PATCH v4 00/25] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-09-12  0:55 ` [PATCH v4 01/25] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-09-12  0:55 ` [PATCH v4 02/25] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-09-12 13:42   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 03/25] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-09-12  0:55 ` [PATCH v4 04/25] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-09-12 14:32   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 05/25] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-09-14  5:31   ` Singh, Gaurav K
2018-09-14  5:57   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 06/25] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-09-14  6:45   ` Singh, Gaurav K
2018-09-12  0:55 ` [PATCH v4 07/25] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-09-12  0:55 ` [PATCH v4 08/25] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-09-12  0:55 ` [PATCH v4 09/25] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-09-12  0:55 ` [PATCH v4 10/25] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-09-12  0:55 ` [PATCH v4 11/25] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-09-12  0:55 ` [PATCH v4 12/25] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-09-12  0:55 ` [PATCH v4 13/25] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-09-12  0:55 ` [PATCH v4 14/25] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-09-12  0:55 ` [PATCH v4 15/25] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-09-12  0:55 ` [PATCH v4 16/25] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-09-12  0:55 ` [PATCH v4 17/25] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-09-12  0:56 ` [PATCH v4 18/25] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-09-12  0:56 ` Manasi Navare [this message]
2018-09-12 19:09   ` [Intel-gfx] [PATCH v4 19/25] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Rodrigo Vivi
2018-09-14 10:55   ` Imre Deak
2018-09-18 19:04     ` Manasi Navare
2018-09-18 19:12       ` Ville Syrjälä
2018-09-18 19:31         ` Manasi Navare
2018-09-18 19:46           ` Ville Syrjälä
2018-09-18 21:10             ` Manasi Navare
2018-09-19 10:57               ` Ville Syrjälä
2018-09-21  8:34                 ` Manasi Navare
2018-09-21 13:46                   ` Ville Syrjälä
2018-10-01  9:35                     ` Imre Deak
2018-10-01 18:32                       ` [Intel-gfx] " Runyan, Arthur J
2018-10-02 11:45                         ` Imre Deak
2018-10-02 18:20                           ` Manasi Navare
2018-10-01  9:45       ` Imre Deak
2018-09-12  0:56 ` [PATCH v4 20/25] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-09-12  0:56 ` [PATCH v4 21/25] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-09-12  0:56 ` [PATCH v4 22/25] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-09-12  0:56 ` [PATCH v4 23/25] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-09-12  0:56 ` [PATCH v4 24/25] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-09-12  0:56 ` [PATCH v4 25/25] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-09-12  1:24 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev4) Patchwork
2018-09-12  1:33 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-09-12  1:41 ` ✗ Fi.CI.BAT: failure " Patchwork

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