From: Miquel Raynal <miquel.raynal@bootlin.com> To: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>, Jason Cooper <jason@lakedaemon.net>, devicetree@vger.kernel.org, Antoine Tenart <antoine.tenart@bootlin.com>, Catalin Marinas <catalin.marinas@arm.com>, Gregory Clement <gregory.clement@bootlin.com>, Haim Boot <hayim@marvell.com>, Will Deacon <will.deacon@arm.com>, Maxime Chevallier <maxime.chevallier@bootlin.com>, Nadav Haklai <nadavh@marvell.com>, Rob Herring <robh+dt@kernel.org>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Thomas Gleixner <tglx@linutronix.de>, Hanna Hawa <hannah@marvell.com>, linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Subject: [PATCH v6 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Date: Mon, 1 Oct 2018 16:13:55 +0200 [thread overview] Message-ID: <20181001141358.31508-12-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20181001141358.31508-1-miquel.raynal@bootlin.com> Describe the System Error Interrupt (SEI) controller. It aggregates two types of interrupts, wired and MSIs from respectively the AP and the CPs, into a single SPI interrupt. Suggested-by: Haim Boot <hayim@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../interrupt-controller/marvell,sei.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt new file mode 100644 index 000000000000..0beafed502f5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt @@ -0,0 +1,36 @@ +Marvell SEI (System Error Interrupt) Controller +----------------------------------------------- + +Marvell SEI (System Error Interrupt) controller is an interrupt +aggregator. It receives interrupts from several sources and aggregates +them to a single interrupt line (an SPI) on the parent interrupt +controller. + +This interrupt controller can handle up to 64 SEIs, a set comes from the +AP and is wired while a second set comes from the CPs by the mean of +MSIs. + +Required properties: + +- compatible: should be one of: + * "marvell,ap806-sei" +- reg: SEI registers location and length. +- interrupts: identifies the parent IRQ that will be triggered. +- #interrupt-cells: number of cells to define an SEI wired interrupt + coming from the AP, should be 1. The cell is the IRQ + number. +- interrupt-controller: identifies the node as an interrupt controller + for AP interrupts. +- msi-controller: identifies the node as an MSI controller for the CPs + interrupts. + +Example: + + sei: interrupt-controller@3f0200 { + compatible = "marvell,ap806-sei"; + reg = <0x3f0200 0x40>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-controller; + msi-controller; + }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: miquel.raynal@bootlin.com (Miquel Raynal) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Date: Mon, 1 Oct 2018 16:13:55 +0200 [thread overview] Message-ID: <20181001141358.31508-12-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20181001141358.31508-1-miquel.raynal@bootlin.com> Describe the System Error Interrupt (SEI) controller. It aggregates two types of interrupts, wired and MSIs from respectively the AP and the CPs, into a single SPI interrupt. Suggested-by: Haim Boot <hayim@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../interrupt-controller/marvell,sei.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt new file mode 100644 index 000000000000..0beafed502f5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt @@ -0,0 +1,36 @@ +Marvell SEI (System Error Interrupt) Controller +----------------------------------------------- + +Marvell SEI (System Error Interrupt) controller is an interrupt +aggregator. It receives interrupts from several sources and aggregates +them to a single interrupt line (an SPI) on the parent interrupt +controller. + +This interrupt controller can handle up to 64 SEIs, a set comes from the +AP and is wired while a second set comes from the CPs by the mean of +MSIs. + +Required properties: + +- compatible: should be one of: + * "marvell,ap806-sei" +- reg: SEI registers location and length. +- interrupts: identifies the parent IRQ that will be triggered. +- #interrupt-cells: number of cells to define an SEI wired interrupt + coming from the AP, should be 1. The cell is the IRQ + number. +- interrupt-controller: identifies the node as an interrupt controller + for AP interrupts. +- msi-controller: identifies the node as an MSI controller for the CPs + interrupts. + +Example: + + sei: interrupt-controller at 3f0200 { + compatible = "marvell,ap806-sei"; + reg = <0x3f0200 0x40>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-controller; + msi-controller; + }; -- 2.17.1
next prev parent reply other threads:[~2018-10-01 14:13 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-01 14:13 [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 01/14] genirq/msi: Allow creation of a tree-based irqdomain for platform-msi Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 02/14] dt-bindings/interrupt-controller: fix Marvell ICU length in the example Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 03/14] irqchip/irq-mvebu-icu: fix wrong private data retrieval Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 04/14] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 05/14] irqchip/irq-mvebu-icu: disociate ICU and NSR Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 06/14] irqchip/irq-mvebu-icu: support ICU subnodes Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 16:49 ` Marc Zyngier 2018-10-01 16:49 ` Marc Zyngier 2018-10-02 8:13 ` Miquel Raynal 2018-10-02 8:13 ` Miquel Raynal 2018-10-02 8:54 ` [PATCH v7 " Miquel Raynal 2018-10-02 8:54 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 07/14] irqchip/irq-mvebu-sei: add new driver for Marvell SEI Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 08/14] arm64: marvell: enable SEI driver Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 17:07 ` Marc Zyngier 2018-10-01 17:07 ` Marc Zyngier 2018-10-02 8:18 ` Miquel Raynal 2018-10-02 8:18 ` Miquel Raynal 2018-10-02 8:59 ` [PATCH v7 " Miquel Raynal 2018-10-02 8:59 ` Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 10/14] dt-bindings/interrupt-controller: update Marvell ICU bindings Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal [this message] 2018-10-01 14:13 ` [PATCH v6 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Miquel Raynal 2018-10-01 14:13 ` [PATCH v6 12/14] arm64: dts: marvell: add AP806 SEI subnode Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-02 14:39 ` Gregory CLEMENT 2018-10-02 14:39 ` Gregory CLEMENT 2018-10-01 14:13 ` [PATCH v6 13/14] arm64: dts: marvell: use new bindings for CP110 interrupts Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-02 14:41 ` Gregory CLEMENT 2018-10-02 14:41 ` Gregory CLEMENT 2018-10-01 14:13 ` [PATCH v6 14/14] arm64: dts: marvell: add CP110 ICU SEI subnode Miquel Raynal 2018-10-01 14:13 ` Miquel Raynal 2018-10-02 10:57 ` [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs Marc Zyngier 2018-10-02 10:57 ` Marc Zyngier 2018-10-02 14:30 ` Gregory CLEMENT 2018-10-02 14:30 ` Gregory CLEMENT
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