From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>,
Jason Cooper <jason@lakedaemon.net>,
devicetree@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Hanna Hawa <hannah@marvell.com>, Haim Boot <hayim@marvell.com>,
Will Deacon <will.deacon@arm.com>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Nadav Haklai <nadavh@marvell.com>,
Antoine Tenart <antoine.tenart@bootlin.com>,
Rob Herring <robh+dt@kernel.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v6 12/14] arm64: dts: marvell: add AP806 SEI subnode
Date: Tue, 02 Oct 2018 16:39:23 +0200 [thread overview]
Message-ID: <871s98o1k4.fsf@bootlin.com> (raw)
In-Reply-To: <20181001141358.31508-13-miquel.raynal@bootlin.com> (Miquel Raynal's message of "Mon, 1 Oct 2018 16:13:56 +0200")
Hi Miquel,
On lun., oct. 01 2018, Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Add the System Error Interrupt node, representing an IRQ chip which is
> part of the GIC. The SEI node aggregates interrupts from the AP through
> wired interrupts, and from the CPs through MSIs.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> index 176e38d54872..92215342b453 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> @@ -124,6 +124,15 @@
> interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + sei: interrupt-controller@3f0200 {
> + compatible = "marvell,ap806-sei";
> + reg = <0x3f0200 0x40>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + msi-controller;
> + };
> +
> xor@400000 {
> compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> reg = <0x400000 0x1000>,
> --
> 2.17.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
WARNING: multiple messages have this Message-ID (diff)
From: gregory.clement@bootlin.com (Gregory CLEMENT)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 12/14] arm64: dts: marvell: add AP806 SEI subnode
Date: Tue, 02 Oct 2018 16:39:23 +0200 [thread overview]
Message-ID: <871s98o1k4.fsf@bootlin.com> (raw)
In-Reply-To: <20181001141358.31508-13-miquel.raynal@bootlin.com> (Miquel Raynal's message of "Mon, 1 Oct 2018 16:13:56 +0200")
Hi Miquel,
On lun., oct. 01 2018, Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Add the System Error Interrupt node, representing an IRQ chip which is
> part of the GIC. The SEI node aggregates interrupts from the AP through
> wired interrupts, and from the CPs through MSIs.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> index 176e38d54872..92215342b453 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> @@ -124,6 +124,15 @@
> interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + sei: interrupt-controller at 3f0200 {
> + compatible = "marvell,ap806-sei";
> + reg = <0x3f0200 0x40>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + msi-controller;
> + };
> +
> xor at 400000 {
> compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
> reg = <0x400000 0x1000>,
> --
> 2.17.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
next prev parent reply other threads:[~2018-10-02 14:39 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-01 14:13 [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 01/14] genirq/msi: Allow creation of a tree-based irqdomain for platform-msi Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 02/14] dt-bindings/interrupt-controller: fix Marvell ICU length in the example Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 03/14] irqchip/irq-mvebu-icu: fix wrong private data retrieval Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 04/14] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 05/14] irqchip/irq-mvebu-icu: disociate ICU and NSR Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 06/14] irqchip/irq-mvebu-icu: support ICU subnodes Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 16:49 ` Marc Zyngier
2018-10-01 16:49 ` Marc Zyngier
2018-10-02 8:13 ` Miquel Raynal
2018-10-02 8:13 ` Miquel Raynal
2018-10-02 8:54 ` [PATCH v7 " Miquel Raynal
2018-10-02 8:54 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 07/14] irqchip/irq-mvebu-sei: add new driver for Marvell SEI Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 08/14] arm64: marvell: enable SEI driver Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 09/14] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 17:07 ` Marc Zyngier
2018-10-01 17:07 ` Marc Zyngier
2018-10-02 8:18 ` Miquel Raynal
2018-10-02 8:18 ` Miquel Raynal
2018-10-02 8:59 ` [PATCH v7 " Miquel Raynal
2018-10-02 8:59 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 10/14] dt-bindings/interrupt-controller: update Marvell ICU bindings Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-01 14:13 ` [PATCH v6 12/14] arm64: dts: marvell: add AP806 SEI subnode Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-02 14:39 ` Gregory CLEMENT [this message]
2018-10-02 14:39 ` Gregory CLEMENT
2018-10-01 14:13 ` [PATCH v6 13/14] arm64: dts: marvell: use new bindings for CP110 interrupts Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-02 14:41 ` Gregory CLEMENT
2018-10-02 14:41 ` Gregory CLEMENT
2018-10-01 14:13 ` [PATCH v6 14/14] arm64: dts: marvell: add CP110 ICU SEI subnode Miquel Raynal
2018-10-01 14:13 ` Miquel Raynal
2018-10-02 10:57 ` [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs Marc Zyngier
2018-10-02 10:57 ` Marc Zyngier
2018-10-02 14:30 ` Gregory CLEMENT
2018-10-02 14:30 ` Gregory CLEMENT
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=871s98o1k4.fsf@bootlin.com \
--to=gregory.clement@bootlin.com \
--cc=andrew@lunn.ch \
--cc=antoine.tenart@bootlin.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=hannah@marvell.com \
--cc=hayim@marvell.com \
--cc=jason@lakedaemon.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=maxime.chevallier@bootlin.com \
--cc=miquel.raynal@bootlin.com \
--cc=nadavh@marvell.com \
--cc=robh+dt@kernel.org \
--cc=sebastian.hesselbarth@gmail.com \
--cc=tglx@linutronix.de \
--cc=thomas.petazzoni@bootlin.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.