* [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles @ 2018-09-24 16:54 Lucas De Marchi 2018-09-24 17:25 ` ✗ Fi.CI.BAT: failure for " Patchwork ` (4 more replies) 0 siblings, 5 replies; 13+ messages in thread From: Lucas De Marchi @ 2018-09-24 16:54 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi Display WA #1178 is meant to fix Aux channel voltage swing too low with some type C dongles. Although it is for type C, of ICL it only applies to combo phy and not to eDP. This means we need to apply the WA only on Aux B. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e7e6ca7f9665..1e92112d23de 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8928,6 +8928,10 @@ enum skl_power_gate { #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398) +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) + /* HDCP Key Registers */ #define HDCP_KEY_CONF _MMIO(0x66c00) #define HDCP_AKSV_SEND_TRIGGER BIT(31) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 0fdabce647ab..a97d2f762b77 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); hsw_wait_for_power_well_enable(dev_priv, power_well); + + /* Display WA #1178: icl */ + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) { + val = I915_READ(ICL_AUX_ANAOVRD1_B); + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; + I915_WRITE(ICL_AUX_ANAOVRD1_B, val); + } } static void -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-09-24 16:54 [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles Lucas De Marchi @ 2018-09-24 17:25 ` Patchwork 2018-10-03 23:30 ` [PATCH] " Rodrigo Vivi ` (3 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2018-09-24 17:25 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles URL : https://patchwork.freedesktop.org/series/50102/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4868 -> Patchwork_10263 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10263 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10263, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/50102/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10263: === IGT changes === ==== Possible regressions ==== igt@core_prop_blob@basic: fi-kbl-7560u: PASS -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10263 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_selftest@live_hangcheck: fi-skl-guc: PASS -> DMESG-FAIL (fdo#106685) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) igt@kms_psr@primary_page_flip: fi-kbl-r: PASS -> FAIL (fdo#107336) ==== Possible fixes ==== igt@gem_exec_suspend@basic-s3: fi-bdw-samus: INCOMPLETE (fdo#107773) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106685 https://bugs.freedesktop.org/show_bug.cgi?id=106685 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 == Participating hosts (46 -> 41) == Additional (1): fi-hsw-4770r Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4868 -> Patchwork_10263 CI_DRM_4868: dd42062d73b630f0ef0e8891bcc6438c14dae9dc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10263: f1c0d6306647d46d6aaf9b5d3247b19a5f9927e2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f1c0d6306647 drm/i915/icl: apply Display WA #1178 to fix type C dongles == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10263/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-09-24 16:54 [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles Lucas De Marchi 2018-09-24 17:25 ` ✗ Fi.CI.BAT: failure for " Patchwork @ 2018-10-03 23:30 ` Rodrigo Vivi 2018-10-03 23:43 ` Lucas De Marchi 2018-10-04 0:06 ` ✓ Fi.CI.BAT: success for " Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 13+ messages in thread From: Rodrigo Vivi @ 2018-10-03 23:30 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Paulo Zanoni On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote: > Display WA #1178 is meant to fix Aux channel voltage swing too low with > some type C dongles. Although it is for type C, of ICL it only applies > to combo phy and not to eDP. This means we need to apply the WA only on > Aux B. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e7e6ca7f9665..1e92112d23de 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8928,6 +8928,10 @@ enum skl_power_gate { > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) > > +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398) > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) > + > /* HDCP Key Registers */ > #define HDCP_KEY_CONF _MMIO(0x66c00) > #define HDCP_AKSV_SEND_TRIGGER BIT(31) > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 0fdabce647ab..a97d2f762b77 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > hsw_wait_for_power_well_enable(dev_priv, power_well); > + > + /* Display WA #1178: icl */ > + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) { Spec tells: CNL: This programming does not apply to Aux A. ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1 with extra note of This programming only applies for external ports on the combo PHY, not on type C PHY, and not for eDP. So I believe we need to add Aux A here and add a check for !is_edp > + val = I915_READ(ICL_AUX_ANAOVRD1_B); > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > + I915_WRITE(ICL_AUX_ANAOVRD1_B, val); > + } > } > > static void > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-10-03 23:30 ` [PATCH] " Rodrigo Vivi @ 2018-10-03 23:43 ` Lucas De Marchi 2018-10-04 0:23 ` Rodrigo Vivi 2018-10-04 10:42 ` Ville Syrjälä 0 siblings, 2 replies; 13+ messages in thread From: Lucas De Marchi @ 2018-10-03 23:43 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni On Wed, Oct 03, 2018 at 04:30:36PM -0700, Rodrigo Vivi wrote: > On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote: > > Display WA #1178 is meant to fix Aux channel voltage swing too low with > > some type C dongles. Although it is for type C, of ICL it only applies > > to combo phy and not to eDP. This means we need to apply the WA only on > > Aux B. > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Imre Deak <imre.deak@intel.com> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++ > > 2 files changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index e7e6ca7f9665..1e92112d23de 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -8928,6 +8928,10 @@ enum skl_power_gate { > > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) > > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) > > > > +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398) > > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) > > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) > > + > > /* HDCP Key Registers */ > > #define HDCP_KEY_CONF _MMIO(0x66c00) > > #define HDCP_AKSV_SEND_TRIGGER BIT(31) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > > index 0fdabce647ab..a97d2f762b77 100644 > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > > > hsw_wait_for_power_well_enable(dev_priv, power_well); > > + > > + /* Display WA #1178: icl */ > > + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) { > > Spec tells: > CNL: This programming does not apply to Aux A. > ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1 > with extra note of This programming only applies for external ports on the combo PHY, > not on type C PHY, and not for eDP. > > So I believe we need to add Aux A here and add a check for !is_edp ha! But spec 20584 for Icelake says Combo Port A can only be used for eDP or DSI. Or am I missing anything here? Lucas De Marchi > > > + val = I915_READ(ICL_AUX_ANAOVRD1_B); > > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > > + I915_WRITE(ICL_AUX_ANAOVRD1_B, val); > > + } > > } > > > > static void > > -- > > 2.17.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-10-03 23:43 ` Lucas De Marchi @ 2018-10-04 0:23 ` Rodrigo Vivi 2018-10-04 10:45 ` Ville Syrjälä 2018-10-04 10:42 ` Ville Syrjälä 1 sibling, 1 reply; 13+ messages in thread From: Rodrigo Vivi @ 2018-10-04 0:23 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni On Wed, Oct 03, 2018 at 04:43:53PM -0700, Lucas De Marchi wrote: > On Wed, Oct 03, 2018 at 04:30:36PM -0700, Rodrigo Vivi wrote: > > On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote: > > > Display WA #1178 is meant to fix Aux channel voltage swing too low with > > > some type C dongles. Although it is for type C, of ICL it only applies > > > to combo phy and not to eDP. This means we need to apply the WA only on > > > Aux B. > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Cc: Imre Deak <imre.deak@intel.com> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++ > > > 2 files changed, 11 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index e7e6ca7f9665..1e92112d23de 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -8928,6 +8928,10 @@ enum skl_power_gate { > > > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) > > > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) > > > > > > +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398) > > > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) > > > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) > > > + > > > /* HDCP Key Registers */ > > > #define HDCP_KEY_CONF _MMIO(0x66c00) > > > #define HDCP_AKSV_SEND_TRIGGER BIT(31) > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > index 0fdabce647ab..a97d2f762b77 100644 > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > > > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > > > > > hsw_wait_for_power_well_enable(dev_priv, power_well); > > > + > > > + /* Display WA #1178: icl */ > > > + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) { > > > > Spec tells: > > CNL: This programming does not apply to Aux A. > > ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1 > > with extra note of This programming only applies for external ports on the combo PHY, > > not on type C PHY, and not for eDP. > > > > So I believe we need to add Aux A here and add a check for !is_edp > > ha! But spec 20584 for Icelake says Combo Port A can only be used for eDP or DSI. > Or am I missing anything here? Hmm... maybe some weird platforms could configuration could use Aux A with Port B through VBT?! I've seen in the past port E with aux B and Port E with aux C. But I really thing it is unlikely indeed... So, feel free to go with: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Lucas De Marchi > > > > > > + val = I915_READ(ICL_AUX_ANAOVRD1_B); > > > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > > > + I915_WRITE(ICL_AUX_ANAOVRD1_B, val); > > > + } > > > } > > > > > > static void > > > -- > > > 2.17.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-10-04 0:23 ` Rodrigo Vivi @ 2018-10-04 10:45 ` Ville Syrjälä 0 siblings, 0 replies; 13+ messages in thread From: Ville Syrjälä @ 2018-10-04 10:45 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni On Wed, Oct 03, 2018 at 05:23:54PM -0700, Rodrigo Vivi wrote: > On Wed, Oct 03, 2018 at 04:43:53PM -0700, Lucas De Marchi wrote: > > On Wed, Oct 03, 2018 at 04:30:36PM -0700, Rodrigo Vivi wrote: > > > On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote: > > > > Display WA #1178 is meant to fix Aux channel voltage swing too low with > > > > some type C dongles. Although it is for type C, of ICL it only applies > > > > to combo phy and not to eDP. This means we need to apply the WA only on > > > > Aux B. > > > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++ > > > > 2 files changed, 11 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > > index e7e6ca7f9665..1e92112d23de 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -8928,6 +8928,10 @@ enum skl_power_gate { > > > > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) > > > > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) > > > > > > > > +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398) > > > > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) > > > > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) > > > > + > > > > /* HDCP Key Registers */ > > > > #define HDCP_KEY_CONF _MMIO(0x66c00) > > > > #define HDCP_AKSV_SEND_TRIGGER BIT(31) > > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > > index 0fdabce647ab..a97d2f762b77 100644 > > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > > @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > > > > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > > > > > > > hsw_wait_for_power_well_enable(dev_priv, power_well); > > > > + > > > > + /* Display WA #1178: icl */ > > > > + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) { > > > > > > Spec tells: > > > CNL: This programming does not apply to Aux A. > > > ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1 > > > with extra note of This programming only applies for external ports on the combo PHY, > > > not on type C PHY, and not for eDP. > > > > > > So I believe we need to add Aux A here and add a check for !is_edp > > > > ha! But spec 20584 for Icelake says Combo Port A can only be used for eDP or DSI. > > Or am I missing anything here? > > Hmm... maybe some weird platforms could configuration could use > Aux A with Port B through VBT?! > > I've seen in the past port E with aux B and Port E with aux C. IIRC mostly I've seen port E with aux A. But now we have aux E so maybe that's not so likely anymore. > > But I really thing it is unlikely indeed... > > So, feel free to go with: > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > > Lucas De Marchi > > > > > > > > > + val = I915_READ(ICL_AUX_ANAOVRD1_B); > > > > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > > > > + I915_WRITE(ICL_AUX_ANAOVRD1_B, val); > > > > + } > > > > } > > > > > > > > static void > > > > -- > > > > 2.17.1 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-10-03 23:43 ` Lucas De Marchi 2018-10-04 0:23 ` Rodrigo Vivi @ 2018-10-04 10:42 ` Ville Syrjälä 2018-10-12 21:57 ` [PATCH v2] " Lucas De Marchi 1 sibling, 1 reply; 13+ messages in thread From: Ville Syrjälä @ 2018-10-04 10:42 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni, Rodrigo Vivi On Wed, Oct 03, 2018 at 04:43:53PM -0700, Lucas De Marchi wrote: > On Wed, Oct 03, 2018 at 04:30:36PM -0700, Rodrigo Vivi wrote: > > On Mon, Sep 24, 2018 at 09:54:35AM -0700, Lucas De Marchi wrote: > > > Display WA #1178 is meant to fix Aux channel voltage swing too low with > > > some type C dongles. Although it is for type C, of ICL it only applies > > > to combo phy and not to eDP. This means we need to apply the WA only on > > > Aux B. > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Cc: Imre Deak <imre.deak@intel.com> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++ > > > 2 files changed, 11 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index e7e6ca7f9665..1e92112d23de 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -8928,6 +8928,10 @@ enum skl_power_gate { > > > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) > > > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) > > > > > > +#define ICL_AUX_ANAOVRD1_B _MMIO(0x6C398) > > > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) > > > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) > > > + > > > /* HDCP Key Registers */ > > > #define HDCP_KEY_CONF _MMIO(0x66c00) > > > #define HDCP_AKSV_SEND_TRIGGER BIT(31) > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > index 0fdabce647ab..a97d2f762b77 100644 > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > > @@ -436,6 +436,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > > > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > > > > > hsw_wait_for_power_well_enable(dev_priv, power_well); > > > + > > > + /* Display WA #1178: icl */ > > > + if (IS_ICELAKE(dev_priv) && pw_idx == ICL_PW_CTL_IDX_AUX_B) { > > > > Spec tells: > > CNL: This programming does not apply to Aux A. > > ILC: Aux A: Set 0x162398 bit 0 and bit 7 = 1 > > with extra note of This programming only applies for external ports on the combo PHY, > > not on type C PHY, and not for eDP. > > > > So I believe we need to add Aux A here and add a check for !is_edp > > ha! But spec 20584 for Icelake says Combo Port A can only be used for eDP or DSI. > Or am I missing anything here? Hmm. I wonder if that's correct. Earlier platforms did allow normal DP (apart from audio/mst/dp++/etc.) on port A (despute the transcoder being called EDP). I'm not sure what the critical difference between DP and eDP would be really. Maybe file an issue in the spec to clarify? > > Lucas De Marchi > > > > > > + val = I915_READ(ICL_AUX_ANAOVRD1_B); > > > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > > > + I915_WRITE(ICL_AUX_ANAOVRD1_B, val); > > > + } > > > } > > > > > > static void > > > -- > > > 2.17.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-10-04 10:42 ` Ville Syrjälä @ 2018-10-12 21:57 ` Lucas De Marchi 2018-10-12 22:28 ` Rodrigo Vivi 2018-10-16 10:12 ` Imre Deak 0 siblings, 2 replies; 13+ messages in thread From: Lucas De Marchi @ 2018-10-12 21:57 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi Display WA #1178 is meant to fix Aux channel voltage swing too low with some type C dongles. It applies to external ports on combo phy. On Icelake this is port A and B when those are not eDP. v2: follow the spec to the letter: include Aux A and just check if it's not eDP instead of checking only for Aux B. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 20785417953d..e74c3f082ee9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8934,6 +8934,15 @@ enum skl_power_gate { #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) +#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) +#define _ICL_AUX_ANAOVRD1_A 0x162398 +#define _ICL_AUX_ANAOVRD1_B 0x6C398 +#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ + _ICL_AUX_ANAOVRD1_A, \ + _ICL_AUX_ANAOVRD1_B)) +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) + /* HDCP Key Registers */ #define HDCP_KEY_CONF _MMIO(0x66c00) #define HDCP_AKSV_SEND_TRIGGER BIT(31) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3cf8533e0834..31a49bdcf193 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -436,6 +436,15 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); hsw_wait_for_power_well_enable(dev_priv, power_well); + + /* Display WA #1178: icl */ + if (IS_ICELAKE(dev_priv) && + pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && + !intel_bios_is_port_edp(dev_priv, port)) { + val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; + I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); + } } static void -- 2.19.1.1.g8c3cf03f71 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-10-12 21:57 ` [PATCH v2] " Lucas De Marchi @ 2018-10-12 22:28 ` Rodrigo Vivi 2018-10-16 10:12 ` Imre Deak 1 sibling, 0 replies; 13+ messages in thread From: Rodrigo Vivi @ 2018-10-12 22:28 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Paulo Zanoni On Fri, Oct 12, 2018 at 02:57:58PM -0700, Lucas De Marchi wrote: > Display WA #1178 is meant to fix Aux channel voltage swing too low with > some type C dongles. It applies to external ports on combo phy. On > Icelake this is port A and B when those are not eDP. > > v2: follow the spec to the letter: include Aux A and just check if it's > not eDP instead of checking only for Aux B. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++ > drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 20785417953d..e74c3f082ee9 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8934,6 +8934,15 @@ enum skl_power_gate { > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) > > +#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) > +#define _ICL_AUX_ANAOVRD1_A 0x162398 > +#define _ICL_AUX_ANAOVRD1_B 0x6C398 > +#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ > + _ICL_AUX_ANAOVRD1_A, \ > + _ICL_AUX_ANAOVRD1_B)) > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) > + > /* HDCP Key Registers */ > #define HDCP_KEY_CONF _MMIO(0x66c00) > #define HDCP_AKSV_SEND_TRIGGER BIT(31) > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 3cf8533e0834..31a49bdcf193 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -436,6 +436,15 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > hsw_wait_for_power_well_enable(dev_priv, power_well); > + > + /* Display WA #1178: icl */ > + if (IS_ICELAKE(dev_priv) && > + pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && > + !intel_bios_is_port_edp(dev_priv, port)) { > + val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > + I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); > + } > } > > static void > -- > 2.19.1.1.g8c3cf03f71 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-10-12 21:57 ` [PATCH v2] " Lucas De Marchi 2018-10-12 22:28 ` Rodrigo Vivi @ 2018-10-16 10:12 ` Imre Deak 1 sibling, 0 replies; 13+ messages in thread From: Imre Deak @ 2018-10-16 10:12 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Paulo Zanoni, Rodrigo Vivi On Fri, Oct 12, 2018 at 02:57:58PM -0700, Lucas De Marchi wrote: > Display WA #1178 is meant to fix Aux channel voltage swing too low with > some type C dongles. It applies to external ports on combo phy. On > Icelake this is port A and B when those are not eDP. > > v2: follow the spec to the letter: include Aux A and just check if it's > not eDP instead of checking only for Aux B. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++ > drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 20785417953d..e74c3f082ee9 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8934,6 +8934,15 @@ enum skl_power_gate { > #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) > #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) > > +#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) > +#define _ICL_AUX_ANAOVRD1_A 0x162398 > +#define _ICL_AUX_ANAOVRD1_B 0x6C398 > +#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ > + _ICL_AUX_ANAOVRD1_A, \ > + _ICL_AUX_ANAOVRD1_B)) > +#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) > +#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) > + > /* HDCP Key Registers */ > #define HDCP_KEY_CONF _MMIO(0x66c00) > #define HDCP_AKSV_SEND_TRIGGER BIT(31) > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 3cf8533e0834..31a49bdcf193 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -436,6 +436,15 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > hsw_wait_for_power_well_enable(dev_priv, power_well); > + > + /* Display WA #1178: icl */ > + if (IS_ICELAKE(dev_priv) && > + pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && > + !intel_bios_is_port_edp(dev_priv, port)) { > + val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); > + val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > + I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); > + } Looks ok: Reviewed-by: Imre Deak <imre.deak@intel.com> I think using port instead of pw_idx to select the register (here and for the CNL counterpart) would be clearer, but that would be for a follow-up in any case. > } > > static void > -- > 2.19.1.1.g8c3cf03f71 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-09-24 16:54 [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles Lucas De Marchi 2018-09-24 17:25 ` ✗ Fi.CI.BAT: failure for " Patchwork 2018-10-03 23:30 ` [PATCH] " Rodrigo Vivi @ 2018-10-04 0:06 ` Patchwork 2018-10-04 10:26 ` ✓ Fi.CI.IGT: " Patchwork 2018-10-12 22:48 ` ✓ Fi.CI.BAT: success for drm/i915/icl: apply Display WA #1178 to fix type C dongles (rev2) Patchwork 4 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2018-10-04 0:06 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles URL : https://patchwork.freedesktop.org/series/50102/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4925 -> Patchwork_10352 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50102/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10352 that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) ==== Possible fixes ==== igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (48 -> 42) == Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 == Build changes == * Linux: CI_DRM_4925 -> Patchwork_10352 CI_DRM_4925: b652f33e63e1aafb7fc1cb2a9648a14d66f0d35f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10352: 4531b0c35129f74192eb31d5fa4671274cc69bc8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4531b0c35129 drm/i915/icl: apply Display WA #1178 to fix type C dongles == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10352/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: apply Display WA #1178 to fix type C dongles 2018-09-24 16:54 [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles Lucas De Marchi ` (2 preceding siblings ...) 2018-10-04 0:06 ` ✓ Fi.CI.BAT: success for " Patchwork @ 2018-10-04 10:26 ` Patchwork 2018-10-12 22:48 ` ✓ Fi.CI.BAT: success for drm/i915/icl: apply Display WA #1178 to fix type C dongles (rev2) Patchwork 4 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2018-10-04 10:26 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles URL : https://patchwork.freedesktop.org/series/50102/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4925_full -> Patchwork_10352_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10352_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_suspend@shrink: shard-kbl: PASS -> INCOMPLETE (fdo#106886, fdo#103665) igt@gem_exec_big: shard-hsw: PASS -> TIMEOUT (fdo#107937) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_fbcon_fbt@psr-suspend: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_plane@pixel-format-pipe-a-planes: shard-skl: NOTRUN -> DMESG-WARN (fdo#106885) igt@kms_plane@plane-position-covered-pipe-b-planes: shard-apl: PASS -> FAIL (fdo#103166) {igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max}: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_sysfs_edid_timing: shard-skl: NOTRUN -> FAIL (fdo#100047) igt@pm_rpm@pm-tiling: shard-skl: NOTRUN -> INCOMPLETE (fdo#107807) ==== Possible fixes ==== igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: FAIL (fdo#103355) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: shard-apl: FAIL (fdo#103167) -> PASS {igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max}: shard-apl: FAIL (fdo#108145) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS igt@kms_universal_plane@universal-plane-pipe-a-functional: shard-apl: FAIL (fdo#103166) -> PASS igt@perf@blocking: shard-hsw: FAIL (fdo#102252) -> PASS {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#107937 https://bugs.freedesktop.org/show_bug.cgi?id=107937 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 5) == Missing (1): shard-glk == Build changes == * Linux: CI_DRM_4925 -> Patchwork_10352 CI_DRM_4925: b652f33e63e1aafb7fc1cb2a9648a14d66f0d35f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10352: 4531b0c35129f74192eb31d5fa4671274cc69bc8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10352/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: apply Display WA #1178 to fix type C dongles (rev2) 2018-09-24 16:54 [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles Lucas De Marchi ` (3 preceding siblings ...) 2018-10-04 10:26 ` ✓ Fi.CI.IGT: " Patchwork @ 2018-10-12 22:48 ` Patchwork 4 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2018-10-12 22:48 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: apply Display WA #1178 to fix type C dongles (rev2) URL : https://patchwork.freedesktop.org/series/50102/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4978 -> Patchwork_10451 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50102/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10451 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_module_reload@basic-reload: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725, fdo#106248) igt@gem_exec_suspend@basic-s3: fi-cfl-8109u: PASS -> INCOMPLETE (fdo#108126, fdo#107187) fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-icl-u2: SKIP -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) ==== Possible fixes ==== igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS +1 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107187 https://bugs.freedesktop.org/show_bug.cgi?id=107187 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126 == Participating hosts (44 -> 40) == Additional (1): fi-icl-u Missing (5): fi-hsw-4770r fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-apl-guc == Build changes == * Linux: CI_DRM_4978 -> Patchwork_10451 CI_DRM_4978: ca98b2681a49a1417f8157af2d94a4f2d0bd0e47 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4674: 93871c6fb3c25e5d350c9faf36ded917174214de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10451: aa9471c9676e40b6c2b1a456e85f0f08c149455c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aa9471c9676e drm/i915/icl: apply Display WA #1178 to fix type C dongles == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10451/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-10-16 10:12 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-09-24 16:54 [PATCH] drm/i915/icl: apply Display WA #1178 to fix type C dongles Lucas De Marchi 2018-09-24 17:25 ` ✗ Fi.CI.BAT: failure for " Patchwork 2018-10-03 23:30 ` [PATCH] " Rodrigo Vivi 2018-10-03 23:43 ` Lucas De Marchi 2018-10-04 0:23 ` Rodrigo Vivi 2018-10-04 10:45 ` Ville Syrjälä 2018-10-04 10:42 ` Ville Syrjälä 2018-10-12 21:57 ` [PATCH v2] " Lucas De Marchi 2018-10-12 22:28 ` Rodrigo Vivi 2018-10-16 10:12 ` Imre Deak 2018-10-04 0:06 ` ✓ Fi.CI.BAT: success for " Patchwork 2018-10-04 10:26 ` ✓ Fi.CI.IGT: " Patchwork 2018-10-12 22:48 ` ✓ Fi.CI.BAT: success for drm/i915/icl: apply Display WA #1178 to fix type C dongles (rev2) Patchwork
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