* [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.
@ 2018-10-05 4:02 Jyoti Yadav
2018-10-05 4:39 ` ✓ Fi.CI.BAT: success for drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4) Patchwork
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jyoti Yadav @ 2018-10-05 4:02 UTC (permalink / raw)
To: intel-gfx; +Cc: chris.p.wilson, rodrigo.vivi
DC5 and DC6 counter register tells about residency of DC5 and DC6.
These registers are same for SKL and ICL.
v2 : Remove csr_version check.
Added generic check regarding DC counters for Gen9 onwards. (Rodrigo)
v3 : Simplified gen checks. (Chris)
v4 : Simplified "if" ladder for multiple gens.
Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++-----
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a5265c2..738f8c7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2897,15 +2897,14 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (IS_KABYLAKE(dev_priv) ||
- (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
+ if (IS_BROXTON(dev_priv)) {
+ seq_printf(m, "DC3 -> DC5 count: %d\n",
+ I915_READ(BXT_CSR_DC3_DC5_COUNT));
+ } else if (IS_GEN(dev_priv, 9, 11)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(SKL_CSR_DC3_DC5_COUNT));
seq_printf(m, "DC5 -> DC6 count: %d\n",
I915_READ(SKL_CSR_DC5_DC6_COUNT));
- } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
- seq_printf(m, "DC3 -> DC5 count: %d\n",
- I915_READ(BXT_CSR_DC3_DC5_COUNT));
}
out:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88..573d5f3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6985,6 +6985,7 @@ enum {
/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
#define CSR_MMIO_START_RANGE 0x80000
#define CSR_MMIO_END_RANGE 0x8FFFF
+/* DC3_DC5 count and DC5_DC6 count registers are same for SKL and ICL */
#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4)
2018-10-05 4:02 [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Jyoti Yadav
@ 2018-10-05 4:39 ` Patchwork
2018-10-05 9:57 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-05 17:29 ` [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Rodrigo Vivi
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-10-05 4:39 UTC (permalink / raw)
To: Jyoti Yadav; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4)
URL : https://patchwork.freedesktop.org/series/49800/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4933 -> Patchwork_10372 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/49800/revisions/4/mbox/
== Known issues ==
Here are the changes found in Patchwork_10372 that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
== Participating hosts (44 -> 41) ==
Additional (2): fi-glk-j4005 fi-snb-2520m
Missing (5): fi-ctg-p8600 fi-bsw-cyan fi-ilk-m540 fi-byt-squawks fi-icl-u2
== Build changes ==
* Linux: CI_DRM_4933 -> Patchwork_10372
CI_DRM_4933: 6b7a44d1597791524f46d7ea17620db54dffdc8c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10372: 2be92258bd1a96c47c25c8f21a5c010735f28305 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2be92258bd1a drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10372/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4)
2018-10-05 4:02 [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Jyoti Yadav
2018-10-05 4:39 ` ✓ Fi.CI.BAT: success for drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4) Patchwork
@ 2018-10-05 9:57 ` Patchwork
2018-10-05 17:29 ` [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Rodrigo Vivi
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-10-05 9:57 UTC (permalink / raw)
To: Jyoti Yadav; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4)
URL : https://patchwork.freedesktop.org/series/49800/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4933_full -> Patchwork_10372_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10372_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_userptr_blits@readonly-unsync:
shard-skl: PASS -> INCOMPLETE (fdo#108074)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-hang-newfb-render-a:
shard-apl: PASS -> DMESG-WARN (fdo#107956)
igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
shard-glk: PASS -> FAIL (fdo#108145)
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: PASS -> FAIL (fdo#103232) +1
igt@kms_cursor_crc@cursor-256x256-onscreen:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
shard-hsw: PASS -> FAIL (fdo#105767)
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538)
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_plane@pixel-format-pipe-a-planes:
shard-skl: NOTRUN -> DMESG-WARN (fdo#106885)
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +1
igt@kms_plane@plane-position-covered-pipe-b-planes:
shard-glk: PASS -> FAIL (fdo#103166) +1
{igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb}:
shard-apl: PASS -> FAIL (fdo#108145)
{igt@kms_plane_alpha_blend@pipe-b-coverage-7efc}:
shard-skl: NOTRUN -> FAIL (fdo#108146)
{igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb}:
shard-skl: NOTRUN -> FAIL (fdo#108145) +3
igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
shard-apl: PASS -> FAIL (fdo#103166) +1
igt@kms_rotation_crc@exhaust-fences:
shard-skl: NOTRUN -> DMESG-WARN (fdo#105748)
igt@kms_sysfs_edid_timing:
shard-skl: NOTRUN -> FAIL (fdo#100047)
==== Possible fixes ====
igt@drv_suspend@fence-restore-untiled:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS
igt@gem_cpu_reloc@full:
shard-skl: INCOMPLETE (fdo#108073) -> PASS
igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-b:
shard-apl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +1
igt@kms_busy@extended-pageflip-hang-newfb-render-b:
shard-glk: DMESG-WARN (fdo#107956) -> PASS
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-glk: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-64x21-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS +3
igt@pm_rpm@pm-tiling:
shard-skl: INCOMPLETE (fdo#107807) -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105748 https://bugs.freedesktop.org/show_bug.cgi?id=105748
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108073 https://bugs.freedesktop.org/show_bug.cgi?id=108073
fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4933 -> Patchwork_10372
CI_DRM_4933: 6b7a44d1597791524f46d7ea17620db54dffdc8c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10372: 2be92258bd1a96c47c25c8f21a5c010735f28305 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10372/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.
2018-10-05 4:02 [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Jyoti Yadav
2018-10-05 4:39 ` ✓ Fi.CI.BAT: success for drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4) Patchwork
2018-10-05 9:57 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-10-05 17:29 ` Rodrigo Vivi
2 siblings, 0 replies; 4+ messages in thread
From: Rodrigo Vivi @ 2018-10-05 17:29 UTC (permalink / raw)
To: Jyoti Yadav; +Cc: intel-gfx, chris.p.wilson
On Fri, Oct 05, 2018 at 12:02:26AM -0400, Jyoti Yadav wrote:
> DC5 and DC6 counter register tells about residency of DC5 and DC6.
> These registers are same for SKL and ICL.
>
> v2 : Remove csr_version check.
> Added generic check regarding DC counters for Gen9 onwards. (Rodrigo)
> v3 : Simplified gen checks. (Chris)
> v4 : Simplified "if" ladder for multiple gens.
>
> Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++-----
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a5265c2..738f8c7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2897,15 +2897,14 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> CSR_VERSION_MINOR(csr->version));
>
> - if (IS_KABYLAKE(dev_priv) ||
> - (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
> + if (IS_BROXTON(dev_priv)) {
> + seq_printf(m, "DC3 -> DC5 count: %d\n",
> + I915_READ(BXT_CSR_DC3_DC5_COUNT));
> + } else if (IS_GEN(dev_priv, 9, 11)) {
> seq_printf(m, "DC3 -> DC5 count: %d\n",
> I915_READ(SKL_CSR_DC3_DC5_COUNT));
> seq_printf(m, "DC5 -> DC6 count: %d\n",
> I915_READ(SKL_CSR_DC5_DC6_COUNT));
> - } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
> - seq_printf(m, "DC3 -> DC5 count: %d\n",
> - I915_READ(BXT_CSR_DC3_DC5_COUNT));
> }
>
> out:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8534f88..573d5f3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6985,6 +6985,7 @@ enum {
> /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
> #define CSR_MMIO_START_RANGE 0x80000
> #define CSR_MMIO_END_RANGE 0x8FFFF
> +/* DC3_DC5 count and DC5_DC6 count registers are same for SKL and ICL */
This comment is incorrect... it is same for skl, kbl, cfl, cnl, whl, aml,
and icl.
But it is also useless because the code is clear already.
And not needed, because "SKL_" prefix shows already
started on SKL, but can be used for SKL+ or not...
Also it has a risk of getting outdated and forgotten.
So, with this removed:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Sorry for not spotting this earlier.
> #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
> #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
> #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-10-05 17:29 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-05 4:02 [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Jyoti Yadav
2018-10-05 4:39 ` ✓ Fi.CI.BAT: success for drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev4) Patchwork
2018-10-05 9:57 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-05 17:29 ` [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Rodrigo Vivi
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