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* [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device
@ 2018-10-18 11:19 Linus Walleij
  2018-10-22  6:50 ` Linus Walleij
  2018-10-23  5:03 ` A H
  0 siblings, 2 replies; 3+ messages in thread
From: Linus Walleij @ 2018-10-18 11:19 UTC (permalink / raw)
  To: Thierry Reding, dri-devel

The DSI devices have a maximum operating frequency specified
in their data sheet per the MIPI specification, and DSI hosts
that can scale their frequency need this information to set
their clock dividers right.

As current panel drivers often lack this information, specify
that setting it to zero will make the DSI host use some
reasonable default.

Cc: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- s/*_rate_hz/*_rate/g
- s/operation/mode/g
- Clarify that zero is only allowed for legacy drivers
---
 include/drm/drm_mipi_dsi.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 4fef19064b0f..da3499de2dc2 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -168,6 +168,12 @@ struct mipi_dsi_device_info {
  * @format: pixel format for video mode
  * @lanes: number of active data lanes
  * @mode_flags: DSI operation mode related flags
+ * @hs_rate: Maximum lane frequency for high speed mode, this should
+ * be set to the real limits of the hardware, zero is only accepted for
+ * legacy drivers
+ * @lp_rate: Maximum lane frequency for low power mode, this should
+ * be set to the real limits of the hardware, zero is only accepted for
+ * legacy drivers
  */
 struct mipi_dsi_device {
 	struct mipi_dsi_host *host;
@@ -178,6 +184,8 @@ struct mipi_dsi_device {
 	unsigned int lanes;
 	enum mipi_dsi_pixel_format format;
 	unsigned long mode_flags;
+	unsigned long hs_rate;
+	unsigned long lp_rate;
 };
 
 #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
-- 
2.17.2

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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device
  2018-10-18 11:19 [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device Linus Walleij
@ 2018-10-22  6:50 ` Linus Walleij
  2018-10-23  5:03 ` A H
  1 sibling, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2018-10-22  6:50 UTC (permalink / raw)
  To: thierry.reding, open list:DRM PANEL DRIVERS, Andrzej Hajda

On Thu, Oct 18, 2018 at 1:19 PM Linus Walleij <linus.walleij@linaro.org> wrote:

> The DSI devices have a maximum operating frequency specified
> in their data sheet per the MIPI specification, and DSI hosts
> that can scale their frequency need this information to set
> their clock dividers right.
>
> As current panel drivers often lack this information, specify
> that setting it to zero will make the DSI host use some
> reasonable default.
>
> Cc: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - s/*_rate_hz/*_rate/g
> - s/operation/mode/g
> - Clarify that zero is only allowed for legacy drivers

Andrzej are you fine with this version (Acked-by) so I can apply it?

Yours,
Linus Walleij
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device
  2018-10-18 11:19 [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device Linus Walleij
  2018-10-22  6:50 ` Linus Walleij
@ 2018-10-23  5:03 ` A H
  1 sibling, 0 replies; 3+ messages in thread
From: A H @ 2018-10-23  5:03 UTC (permalink / raw)
  To: Linus Walleij; +Cc: Thierry Reding, dri-devel


[-- Attachment #1.1: Type: text/plain, Size: 2737 bytes --]

czw., 18 paź 2018, 12:21 użytkownik Linus Walleij <linus.walleij@linaro.org>
napisał:

> The DSI devices have a maximum operating frequency specified
> in their data sheet per the MIPI specification, and DSI hosts
> that can scale their frequency need this information to set
> their clock dividers right.
>
> As current panel drivers often lack this information, specify
> that setting it to zero will make the DSI host use some
> reasonable default.
>
> Cc: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - s/*_rate_hz/*_rate/g
> - s/operation/mode/g
> - Clarify that zero is only allowed for legacy drivers
> ---
>  include/drm/drm_mipi_dsi.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
> index 4fef19064b0f..da3499de2dc2 100644
> --- a/include/drm/drm_mipi_dsi.h
> +++ b/include/drm/drm_mipi_dsi.h
> @@ -168,6 +168,12 @@ struct mipi_dsi_device_info {
>   * @format: pixel format for video mode
>   * @lanes: number of active data lanes
>   * @mode_flags: DSI operation mode related flags
> + * @hs_rate: Maximum lane frequency for high speed mode, this should
> + * be set to the real limits of the hardware, zero is only accepted for
> + * legacy drivers
> + * @lp_rate: Maximum lane frequency for low power mode, this should
> + * be set to the real limits of the hardware, zero is only accepted for
> + * legacy drivers
>

The convention here is no-capital-letters, moreover it would be good to put
units in the description.

Regarding zero value, as I looked into some random panel data sheets they
do not always have specified rates, so maybe calculation of hs_rate from
specified video mode wouldn't be so bad, but in such case it should be
described here, up to you, can be adjusted in the future when we will have
more input.

So with minor changes from previous sentence:
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>

I have no access to my corp mail atm, so if there is policy to send tags
from the same email, I can do it on Friday.

Regards
Andrzej

  */
>  struct mipi_dsi_device {
>         struct mipi_dsi_host *host;
> @@ -178,6 +184,8 @@ struct mipi_dsi_device {
>         unsigned int lanes;
>         enum mipi_dsi_pixel_format format;
>         unsigned long mode_flags;
> +       unsigned long hs_rate;
> +       unsigned long lp_rate;
>  };
>
>  #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
> --
> 2.17.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2018-10-23  5:03 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2018-10-18 11:19 [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device Linus Walleij
2018-10-22  6:50 ` Linus Walleij
2018-10-23  5:03 ` A H

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