* [PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller
@ 2018-11-20 14:52 Maxime Ripard
2018-11-27 5:59 ` Jagan Teki
0 siblings, 1 reply; 5+ messages in thread
From: Maxime Ripard @ 2018-11-20 14:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Myl?ne Josserand <mylene.josserand@bootlin.com>
The H3 and H5 features the same CSI controller that was initially found on
the A31.
Add a DT node for it.
Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Changes from v3:
- Removed the CSI MCLK pin from the default pin group
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 4b1530ebe427..39cd445f796a 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -393,6 +393,13 @@
interrupt-controller;
#interrupt-cells = <3>;
+ csi_pins: csi {
+ pins = "PE1", "PE2", "PE3", "PE4", "PE5",
+ "PE6", "PE7", "PE8", "PE9", "PE10",
+ "PE11";
+ function = "csi";
+ };
+
emac_rgmii_pins: emac0 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD7", "PD8", "PD9", "PD10",
@@ -744,6 +751,21 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ csi: camera at 1cb0000 {
+ compatible = "allwinner,sun8i-h3-csi",
+ "allwinner,sun6i-a31-csi";
+ reg = <0x01cb0000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi_pins>;
+ status = "disabled";
+ };
+
hdmi: hdmi at 1ee0000 {
compatible = "allwinner,sun8i-h3-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
--
2.19.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller
2018-11-20 14:52 [PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller Maxime Ripard
@ 2018-11-27 5:59 ` Jagan Teki
2018-11-27 7:53 ` Maxime Ripard
0 siblings, 1 reply; 5+ messages in thread
From: Jagan Teki @ 2018-11-27 5:59 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Nov 20, 2018 at 9:53 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> From: Myl?ne Josserand <mylene.josserand@bootlin.com>
>
> The H3 and H5 features the same CSI controller that was initially found on
> the A31.
>
> Add a DT node for it.
>
> Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> ---
>
> Changes from v3:
> - Removed the CSI MCLK pin from the default pin group
If I'm not wrong, PE1 is CSI_MCLK and PE0 is CSI_PCLK so we have PE0
and PE1 removed.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller
2018-11-27 5:59 ` Jagan Teki
@ 2018-11-27 7:53 ` Maxime Ripard
2018-11-27 8:06 ` Jagan Teki
0 siblings, 1 reply; 5+ messages in thread
From: Maxime Ripard @ 2018-11-27 7:53 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Nov 27, 2018 at 11:29:13AM +0530, Jagan Teki wrote:
> On Tue, Nov 20, 2018 at 9:53 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > From: Myl?ne Josserand <mylene.josserand@bootlin.com>
> >
> > The H3 and H5 features the same CSI controller that was initially found on
> > the A31.
> >
> > Add a DT node for it.
> >
> > Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> >
> > ---
> >
> > Changes from v3:
> > - Removed the CSI MCLK pin from the default pin group
>
> If I'm not wrong, PE1 is CSI_MCLK and PE0 is CSI_PCLK so we have PE0
> and PE1 removed.
i'm not sure what you mean, PCLK is still in that patch.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller
2018-11-27 7:53 ` Maxime Ripard
@ 2018-11-27 8:06 ` Jagan Teki
2018-11-27 15:55 ` Maxime Ripard
0 siblings, 1 reply; 5+ messages in thread
From: Jagan Teki @ 2018-11-27 8:06 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Nov 27, 2018 at 1:24 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Tue, Nov 27, 2018 at 11:29:13AM +0530, Jagan Teki wrote:
> > On Tue, Nov 20, 2018 at 9:53 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > From: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > >
> > > The H3 and H5 features the same CSI controller that was initially found on
> > > the A31.
> > >
> > > Add a DT node for it.
> > >
> > > Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > >
> > > ---
> > >
> > > Changes from v3:
> > > - Removed the CSI MCLK pin from the default pin group
> >
> > If I'm not wrong, PE1 is CSI_MCLK and PE0 is CSI_PCLK so we have PE0
> > and PE1 removed.
>
> i'm not sure what you mean, PCLK is still in that patch.
PE0 -> CSI_PCLK
PE1 -> CSI_MCLK
So, removing CSI MCLK in "Changes from v3" means, removing PE1 right?
but csi_pins removed PE0 which is CSI_PCLK, we need to remove PE1 from
csi_pins and keep PE0. isn't it?
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller
2018-11-27 8:06 ` Jagan Teki
@ 2018-11-27 15:55 ` Maxime Ripard
0 siblings, 0 replies; 5+ messages in thread
From: Maxime Ripard @ 2018-11-27 15:55 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Nov 27, 2018 at 01:36:38PM +0530, Jagan Teki wrote:
> On Tue, Nov 27, 2018 at 1:24 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Nov 27, 2018 at 11:29:13AM +0530, Jagan Teki wrote:
> > > On Tue, Nov 20, 2018 at 9:53 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > > >
> > > > From: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > > >
> > > > The H3 and H5 features the same CSI controller that was initially found on
> > > > the A31.
> > > >
> > > > Add a DT node for it.
> > > >
> > > > Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > > >
> > > > ---
> > > >
> > > > Changes from v3:
> > > > - Removed the CSI MCLK pin from the default pin group
> > >
> > > If I'm not wrong, PE1 is CSI_MCLK and PE0 is CSI_PCLK so we have PE0
> > > and PE1 removed.
> >
> > i'm not sure what you mean, PCLK is still in that patch.
>
> PE0 -> CSI_PCLK
> PE1 -> CSI_MCLK
>
> So, removing CSI MCLK in "Changes from v3" means, removing PE1 right?
> but csi_pins removed PE0 which is CSI_PCLK, we need to remove PE1 from
> csi_pins and keep PE0. isn't it?
Ah, right. I've fixed it up while applying.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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2018-11-20 14:52 [PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller Maxime Ripard
2018-11-27 5:59 ` Jagan Teki
2018-11-27 7:53 ` Maxime Ripard
2018-11-27 8:06 ` Jagan Teki
2018-11-27 15:55 ` Maxime Ripard
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