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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 4/5] drm/i915: Add PSR2 selective update status registers and bits definitions
Date: Tue,  4 Dec 2018 15:00:31 -0800	[thread overview]
Message-ID: <20181204230032.6352-4-jose.souza@intel.com> (raw)
In-Reply-To: <20181204230032.6352-1-jose.souza@intel.com>

This register contains how many blocks was sent in the past selective
updates.
Those registers are not kept set all the times but pulling it after flip
can show that the expected values are set for the current frame and the
previous ones too.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d60509ca7..7d634f34ca7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4248,6 +4248,12 @@ enum {
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
 #define EDP_PSR2_STATUS_STATE_SHIFT    28
 
+#define EDP_PSR2_SU_STATUS					_MMIO(0x6f914)
+#define EDP_PSR2_SU_STATUS2					_MMIO(0x6F918)
+#define EDP_PSR2_SU_STATUS3					_MMIO(0x6F91C)
+#define  EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_SHIFT(i)	((i) * 10)
+#define  EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_MASK(i)	(0x3FF << ((i) * 10))
+
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
-- 
2.19.2

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  parent reply	other threads:[~2018-12-04 23:00 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-04 23:00 [PATCH 1/5] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks José Roberto de Souza
2018-12-04 23:00 ` [PATCH 2/5] drm/i915: Refactor PSR status debugfs José Roberto de Souza
2018-12-11  6:51   ` Dhinakaran Pandiyan
2018-12-11 12:44     ` Souza, Jose
2018-12-11 18:32       ` Dhinakaran Pandiyan
2018-12-11 18:54         ` Souza, Jose
2019-01-02 17:09           ` Souza, Jose
2019-01-02 19:02             ` Dhinakaran Pandiyan
2018-12-04 23:00 ` [PATCH 3/5] drm/i915/psr: Do not print last attempted entry or exit in PSR debugfs while in PSR2 José Roberto de Souza
2018-12-11  7:03   ` Dhinakaran Pandiyan
2018-12-11 14:01     ` Souza, Jose
2018-12-04 23:00 ` José Roberto de Souza [this message]
2018-12-11  7:51   ` [PATCH 4/5] drm/i915: Add PSR2 selective update status registers and bits definitions Dhinakaran Pandiyan
2018-12-11 14:20     ` Souza, Jose
2018-12-04 23:00 ` [PATCH 5/5] drm/i915/debugfs: Print PSR selective update status register values José Roberto de Souza
2018-12-11 22:20   ` Dhinakaran Pandiyan
2018-12-13 18:06     ` Souza, Jose
2018-12-04 23:10 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks Patchwork
2018-12-04 23:27 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-05 11:38 ` ✓ Fi.CI.IGT: " Patchwork
2018-12-11  3:52 ` [PATCH 1/5] " Dhinakaran Pandiyan
2018-12-11 12:29   ` Souza, Jose

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