From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-devel] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() Date: Wed, 26 Dec 2018 09:20:03 -0800 [thread overview] Message-ID: <20181226172005.26990-13-palmer@sifive.com> (raw) In-Reply-To: <20181226172005.26990-1-palmer@sifive.com> From: Anup Patel <anup@brainfault.org> Currently, start and end address of a PMP region are not decoded correctly by pmp_decode_napot(). Let's say we have a 128KB PMP region with base address as 0x80000000. Now, the PMPADDRx CSR value for this region will be 0x20003fff. The current pmp_decode_napot() implementation will decode PMPADDRx CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff. This patch fixes the base value decoding in pmp_decode_napot() when PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff). Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 03abd8fe5eb7..15a5366616bd 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -138,7 +138,7 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) return; } else { target_ulong t1 = ctz64(~a); - target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 3; + target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2; target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1; *sa = base; *ea = base + range; -- 2.18.1
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() Date: Wed, 26 Dec 2018 09:20:03 -0800 [thread overview] Message-ID: <20181226172005.26990-13-palmer@sifive.com> (raw) In-Reply-To: <20181226172005.26990-1-palmer@sifive.com> From: Anup Patel <anup@brainfault.org> Currently, start and end address of a PMP region are not decoded correctly by pmp_decode_napot(). Let's say we have a 128KB PMP region with base address as 0x80000000. Now, the PMPADDRx CSR value for this region will be 0x20003fff. The current pmp_decode_napot() implementation will decode PMPADDRx CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff. This patch fixes the base value decoding in pmp_decode_napot() when PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff). Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 03abd8fe5eb7..15a5366616bd 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -138,7 +138,7 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) return; } else { target_ulong t1 = ctz64(~a); - target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 3; + target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2; target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1; *sa = base; *ea = base + range; -- 2.18.1
next prev parent reply other threads:[~2018-12-26 17:20 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-26 17:19 [Qemu-devel] [PULL] RISC-V Changes for 3.2, Part 1 Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 04/14] riscv: Enable VGA and PCIE_VGA Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-devel] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes Palmer Dabbelt 2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-devel] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-devel] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-devel] [PULL 11/14] sifive_uart: Implement interrupt pending register Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:20 ` Palmer Dabbelt [this message] 2018-12-26 17:20 ` [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-devel] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-riscv] " Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-devel] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported Palmer Dabbelt 2018-12-26 17:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-03 16:46 ` [Qemu-devel] [PULL] RISC-V Changes for 3.2, Part 1 Peter Maydell 2019-01-03 16:46 ` [Qemu-riscv] " Peter Maydell 2019-01-08 19:37 ` [Qemu-devel] Wiki Account Creation [Was Re: [PULL] RISC-V Changes for 3.2, Part 1] Palmer Dabbelt 2019-01-08 19:37 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-08 20:35 ` [Qemu-devel] " Max Filippov 2019-01-08 20:35 ` [Qemu-riscv] " Max Filippov 2019-01-09 19:37 ` Palmer Dabbelt 2019-01-09 19:37 ` [Qemu-riscv] " Palmer Dabbelt -- strict thread matches above, loose matches on Subject: below -- 2018-12-21 16:02 [Qemu-devel] [PR RFC] RISC-V Changes for 3.2, Part 1 Palmer Dabbelt 2018-12-21 16:03 ` [Qemu-devel] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() Palmer Dabbelt
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