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From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Mao Zhongyi <maozhongyi@cmss.chinamobile.com>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize
Date: Wed, 26 Dec 2018 09:20:04 -0800	[thread overview]
Message-ID: <20181226172005.26990-14-palmer@sifive.com> (raw)
In-Reply-To: <20181226172005.26990-1-palmer@sifive.com>

From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a025a0a3baac..5e8a2cb2ba61 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -330,8 +330,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     CPUClass *cc = CPU_CLASS(c);
     DeviceClass *dc = DEVICE_CLASS(c);
 
-    mcc->parent_realize = dc->realize;
-    dc->realize = riscv_cpu_realize;
+    device_class_set_parent_realize(dc, riscv_cpu_realize,
+                                    &mcc->parent_realize);
 
     mcc->parent_reset = cc->reset;
     cc->reset = riscv_cpu_reset;
-- 
2.18.1

WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org,       qemu-devel@nongnu.org,
	Mao Zhongyi <maozhongyi@cmss.chinamobile.com>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize
Date: Wed, 26 Dec 2018 09:20:04 -0800	[thread overview]
Message-ID: <20181226172005.26990-14-palmer@sifive.com> (raw)
In-Reply-To: <20181226172005.26990-1-palmer@sifive.com>

From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a025a0a3baac..5e8a2cb2ba61 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -330,8 +330,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     CPUClass *cc = CPU_CLASS(c);
     DeviceClass *dc = DEVICE_CLASS(c);
 
-    mcc->parent_realize = dc->realize;
-    dc->realize = riscv_cpu_realize;
+    device_class_set_parent_realize(dc, riscv_cpu_realize,
+                                    &mcc->parent_realize);
 
     mcc->parent_reset = cc->reset;
     cc->reset = riscv_cpu_reset;
-- 
2.18.1



  parent reply	other threads:[~2018-12-26 17:21 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-26 17:19 [Qemu-devel] [PULL] RISC-V Changes for 3.2, Part 1 Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 04/14] riscv: Enable VGA and PCIE_VGA Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:19 ` [Qemu-devel] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes Palmer Dabbelt
2018-12-26 17:19   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads Palmer Dabbelt
2018-12-26 17:20   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u Palmer Dabbelt
2018-12-26 17:20   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 11/14] sifive_uart: Implement interrupt pending register Palmer Dabbelt
2018-12-26 17:20   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() Palmer Dabbelt
2018-12-26 17:20   ` [Qemu-riscv] " Palmer Dabbelt
2018-12-26 17:20 ` Palmer Dabbelt [this message]
2018-12-26 17:20   ` [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize Palmer Dabbelt
2018-12-26 17:20 ` [Qemu-devel] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported Palmer Dabbelt
2018-12-26 17:20   ` [Qemu-riscv] " Palmer Dabbelt
2019-01-03 16:46 ` [Qemu-devel] [PULL] RISC-V Changes for 3.2, Part 1 Peter Maydell
2019-01-03 16:46   ` [Qemu-riscv] " Peter Maydell
2019-01-08 19:37   ` [Qemu-devel] Wiki Account Creation [Was Re: [PULL] RISC-V Changes for 3.2, Part 1] Palmer Dabbelt
2019-01-08 19:37     ` [Qemu-riscv] " Palmer Dabbelt
2019-01-08 20:35     ` [Qemu-devel] " Max Filippov
2019-01-08 20:35       ` [Qemu-riscv] " Max Filippov
2019-01-09 19:37       ` Palmer Dabbelt
2019-01-09 19:37         ` [Qemu-riscv] " Palmer Dabbelt
  -- strict thread matches above, loose matches on Subject: below --
2018-12-21 16:02 [Qemu-devel] [PR RFC] RISC-V Changes for 3.2, Part 1 Palmer Dabbelt
2018-12-21 16:03 ` [Qemu-devel] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize Palmer Dabbelt

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