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From: Matt Roper <matthew.d.roper@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 03/13] drm/i915: Precompute gamma_mode
Date: Fri, 11 Jan 2019 16:41:49 -0800	[thread overview]
Message-ID: <20190112004149.GV4563@mdroper-desk.amr.corp.intel.com> (raw)
In-Reply-To: <20190111170823.4441-4-ville.syrjala@linux.intel.com>

On Fri, Jan 11, 2019 at 07:08:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We shouldn't be computing gamma mode during the commit phase.
> Move it to the check phase.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks like this also drops the posting reads, but I don't see anything
in the bspec that indicates those were necessary in the first place.

> ---
>  drivers/gpu/drm/i915/intel_color.c | 44 +++++++++++++++++-------------
>  1 file changed, 25 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 37fd9ddf762e..b10e66ce3970 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -375,8 +375,7 @@ static void haswell_load_luts(struct intel_crtc_state *crtc_state)
>  		reenable_ips = true;
>  	}
>  
> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> -	I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
> +	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>  
>  	i9xx_load_luts(crtc_state);
>  
> @@ -476,9 +475,7 @@ static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
>  	bdw_load_gamma_lut(crtc_state,
>  			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
>  
> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> -	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
> -	POSTING_READ(GAMMA_MODE(pipe));
> +	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  
>  	/*
>  	 * Reset the index, otherwise it prevents the legacy palette to be
> @@ -532,9 +529,7 @@ static void glk_load_luts(struct intel_crtc_state *crtc_state)
>  
>  	bdw_load_gamma_lut(crtc_state, 0);
>  
> -	crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> -	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
> -	POSTING_READ(GAMMA_MODE(pipe));
> +	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  }
>  
>  /* Loads the palette/gamma unit for the CRTC on CherryView. */
> @@ -608,29 +603,40 @@ void intel_color_load_luts(struct intel_crtc_state *crtc_state)
>  int intel_color_check(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
>  	size_t gamma_length, degamma_length;
>  
>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  
>  	/*
> -	 * We allow both degamma & gamma luts at the right size or
> -	 * NULL.
> +	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> +	 * size (256 entries).
>  	 */

Minor nit:  now that the order of tests is swapped, you probably want
to move the "also" from this comment down to the one below.

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> -	if ((!crtc_state->base.degamma_lut ||
> -	     drm_color_lut_size(crtc_state->base.degamma_lut) == degamma_length) &&
> -	    (!crtc_state->base.gamma_lut ||
> -	     drm_color_lut_size(crtc_state->base.gamma_lut) == gamma_length))
> +	if (crtc_state_is_legacy_gamma(crtc_state)) {
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>  		return 0;
> +	}
>  
>  	/*
> -	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> -	 * size (256 entries).
> +	 * We allow both degamma & gamma luts at the right size or
> +	 * NULL.
>  	 */
> -	if (crtc_state_is_legacy_gamma(crtc_state))
> -		return 0;
> +	if (degamma_lut && drm_color_lut_size(degamma_lut) != degamma_length)
> +		return -EINVAL;
> +
> +	if (gamma_lut && drm_color_lut_size(gamma_lut) != gamma_length)
> +		return -EINVAL;
> +
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> +	else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> +	else
> +		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>  
> -	return -EINVAL;
> +	return 0;
>  }
>  
>  void intel_color_init(struct intel_crtc *crtc)
> -- 
> 2.19.2
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-01-12  0:41 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-16 16:08   ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-14 17:11     ` Ville Syrjälä
2019-01-14 19:11       ` Ville Syrjälä
2019-01-16 17:11         ` Shankar, Uma
2019-01-17 16:34           ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 03/13] drm/i915: Precompute gamma_mode Ville Syrjala
2019-01-12  0:41   ` Matt Roper [this message]
2019-01-16 17:18     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
2019-01-12  0:42   ` Matt Roper
2019-01-16 17:21     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
2019-01-12  0:57   ` Matt Roper
2019-01-16 17:26     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
2019-01-15  0:56   ` Matt Roper
2019-01-16 18:22     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
2019-01-16 17:38   ` Matt Roper
2019-01-16 18:02     ` Ville Syrjälä
2019-01-17 15:00     ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
2019-01-16 18:31   ` Matt Roper
2019-01-16 18:58     ` Ville Syrjälä
2019-01-16 19:51       ` Ville Syrjälä
2019-01-29 15:59         ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
2019-01-16 19:36   ` Matt Roper
2019-01-17  5:14     ` Shankar, Uma
2019-01-17 14:57       ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 10/13] drm/i915: Track pipe csc enable " Ville Syrjala
2019-01-16 19:43   ` Matt Roper
2019-01-17  5:17     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
2019-01-17  5:32   ` Shankar, Uma
2019-01-17 18:40   ` Matt Roper
2019-01-17 18:48     ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 12/13] drm/i915: Turn off pipe CSC " Ville Syrjala
2019-01-17  5:37   ` Shankar, Uma
2019-01-17 18:54   ` Matt Roper
2019-01-11 17:08 ` [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
2019-01-17  5:58   ` Shankar, Uma
2019-01-17 19:13   ` Matt Roper
2019-01-17 19:27     ` Ville Syrjälä
2019-01-11 17:25 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8 Patchwork
2019-01-11 17:44 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-11 22:03 ` ✓ Fi.CI.IGT: " Patchwork

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