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From: "Shankar, Uma" <uma.shankar@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.
Date: Thu, 17 Jan 2019 05:32:38 +0000	[thread overview]
Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F81ED47D3@BGSMSX104.gar.corp.intel.com> (raw)
In-Reply-To: <20190111170823.4441-12-ville.syrjala@linux.intel.com>



>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, January 11, 2019 10:38 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed.

Full stop can be dropped.

>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>The pipe internal precision is higher than what we currently program to the
>degamma/gamma LUTs. We can get a higher quality image by bypassing the LUTs
>when they're not needed. Let's do that.
>
>Each plane has its own control bit for this, so we have to update all active planes.
>The way we've done this we don't actually have to run through the whole
>.check_plane() thing. And we actually do the .color_check() after .check_plane()
>so we couldn't even do that without shuffling the code around.
>
>Additionally on pre-skl we have to update the primary plane regardless of
>whether it's active or not on account of the primayr plane gamma enable bit also

Typo in primary.

Overall looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>affecting the pipe bottom color.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 55 ++++++++++++++++++++++++++++--
> 1 file changed, 53 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index 8d7ea902a34b..a8b7428a64bf 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -633,27 +633,78 @@ void intel_color_commit(const struct intel_crtc_state
>*crtc_state)
> 	dev_priv->display.color_commit(crtc_state);
> }
>
>+static bool need_plane_update(struct intel_plane *plane,
>+			      const struct intel_crtc_state *crtc_state) {
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+
>+	/*
>+	 * On pre-SKL the pipe gamma enable and pipe csc enable for
>+	 * the pipe bottom color are configured via the primary plane.
>+	 * We have to reconfigure that even if the plane is inactive.
>+	 */
>+	return crtc_state->active_planes & BIT(plane->id) ||
>+		(INTEL_GEN(dev_priv) < 9 &&
>+		 plane->id == PLANE_PRIMARY);
>+}
>+
>+static int
>+intel_color_add_affected_planes(struct intel_crtc_state
>+*new_crtc_state) {
>+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+	struct intel_atomic_state *state =
>+		to_intel_atomic_state(new_crtc_state->base.state);
>+	const struct intel_crtc_state *old_crtc_state =
>+		intel_atomic_get_old_crtc_state(state, crtc);
>+	struct intel_plane *plane;
>+
>+	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable)
>+		return 0;
>+
>+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
>+		struct intel_plane_state *plane_state;
>+
>+		if (!need_plane_update(plane, new_crtc_state))
>+			continue;
>+
>+		plane_state = intel_atomic_get_plane_state(state, plane);
>+		if (IS_ERR(plane_state))
>+			return PTR_ERR(plane_state);
>+
>+		new_crtc_state->update_planes |= BIT(plane->id);
>+	}
>+
>+	return 0;
>+}
>+
> int intel_color_check(struct intel_crtc_state *crtc_state)  {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> 	const struct drm_property_blob *gamma_lut = crtc_state-
>>base.gamma_lut;
> 	const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
> 	size_t gamma_length, degamma_length;
>+	int ret;
>
> 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> 	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>
>-	crtc_state->gamma_enable = true;
>+	crtc_state->gamma_enable = gamma_lut || degamma_lut;
>
> 	if (INTEL_GEN(dev_priv) >= 9 ||
> 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> 		crtc_state->csc_enable = true;
>
>+	ret = intel_color_add_affected_planes(crtc_state);
>+	if (ret)
>+		return ret;
>+
> 	/*
> 	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> 	 * size (256 entries).
> 	 */
>-	if (crtc_state_is_legacy_gamma(crtc_state)) {
>+	if (!crtc_state->gamma_enable ||
>+	    crtc_state_is_legacy_gamma(crtc_state)) {
> 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> 		return 0;
> 	}
>--
>2.19.2

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  reply	other threads:[~2019-01-17  5:32 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-11 17:08 [PATCH 00/13] Enable/disable gamma/csc dynamically and fix C8 Ville Syrjala
2019-01-11 17:08 ` [PATCH 01/13] drm/i915: Clean up intel_plane_atomic_check_with_state() Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-16 16:08   ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 02/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-14 17:11     ` Ville Syrjälä
2019-01-14 19:11       ` Ville Syrjälä
2019-01-16 17:11         ` Shankar, Uma
2019-01-17 16:34           ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 03/13] drm/i915: Precompute gamma_mode Ville Syrjala
2019-01-12  0:41   ` Matt Roper
2019-01-16 17:18     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 04/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
2019-01-12  0:42   ` Matt Roper
2019-01-16 17:21     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
2019-01-12  0:57   ` Matt Roper
2019-01-16 17:26     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 06/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
2019-01-15  0:56   ` Matt Roper
2019-01-16 18:22     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 07/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
2019-01-16 17:38   ` Matt Roper
2019-01-16 18:02     ` Ville Syrjälä
2019-01-17 15:00     ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 08/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
2019-01-16 18:31   ` Matt Roper
2019-01-16 18:58     ` Ville Syrjälä
2019-01-16 19:51       ` Ville Syrjälä
2019-01-29 15:59         ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 09/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
2019-01-16 19:36   ` Matt Roper
2019-01-17  5:14     ` Shankar, Uma
2019-01-17 14:57       ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 10/13] drm/i915: Track pipe csc enable " Ville Syrjala
2019-01-16 19:43   ` Matt Roper
2019-01-17  5:17     ` Shankar, Uma
2019-01-11 17:08 ` [PATCH 11/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
2019-01-17  5:32   ` Shankar, Uma [this message]
2019-01-17 18:40   ` Matt Roper
2019-01-17 18:48     ` Ville Syrjälä
2019-01-11 17:08 ` [PATCH 12/13] drm/i915: Turn off pipe CSC " Ville Syrjala
2019-01-17  5:37   ` Shankar, Uma
2019-01-17 18:54   ` Matt Roper
2019-01-11 17:08 ` [PATCH 13/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
2019-01-17  5:58   ` Shankar, Uma
2019-01-17 19:13   ` Matt Roper
2019-01-17 19:27     ` Ville Syrjälä
2019-01-11 17:25 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8 Patchwork
2019-01-11 17:44 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-11 22:03 ` ✓ Fi.CI.IGT: " Patchwork

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