* [PATCH v3 0/2] cadence-quadspi: Add Octal mode support @ 2019-01-16 10:30 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: Boris Brezillon, Tudor.Ambarus Cc: Marek Vasut, Rob Herring, linux-mtd, devicetree, linux-kernel, Vignesh R This series adds support for OSPI version of Cadence QSPI controller IP. Based on top of [1][2] that add Octal mode support in spi-nor core: [1] https://patchwork.ozlabs.org/patch/1025081/ [2] https://patchwork.ozlabs.org/patch/1025082/ Changes: v3: Rebase on top of v7 of Yogesh's series[1] v2: spi-nor core patches dropped, are now part of Yogesh's series [1] Declare Octal mode capability based on compatible. Vignesh R (2): dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller .../bindings/mtd/cadence-quadspi.txt | 1 + drivers/mtd/spi-nor/cadence-quadspi.c | 54 ++++++++++++++----- 2 files changed, 43 insertions(+), 12 deletions(-) -- 2.20.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 0/2] cadence-quadspi: Add Octal mode support @ 2019-01-16 10:30 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: linux-mtd This series adds support for OSPI version of Cadence QSPI controller IP. Based on top of [1][2] that add Octal mode support in spi-nor core: [1] https://patchwork.ozlabs.org/patch/1025081/ [2] https://patchwork.ozlabs.org/patch/1025082/ Changes: v3: Rebase on top of v7 of Yogesh's series[1] v2: spi-nor core patches dropped, are now part of Yogesh's series [1] Declare Octal mode capability based on compatible. Vignesh R (2): dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller .../bindings/mtd/cadence-quadspi.txt | 1 + drivers/mtd/spi-nor/cadence-quadspi.c | 54 ++++++++++++++----- 2 files changed, 43 insertions(+), 12 deletions(-) -- 2.20.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 0/2] cadence-quadspi: Add Octal mode support @ 2019-01-16 10:30 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: Boris Brezillon, Tudor.Ambarus Cc: Marek Vasut, Rob Herring, linux-mtd, devicetree, linux-kernel, Vignesh R This series adds support for OSPI version of Cadence QSPI controller IP. Based on top of [1][2] that add Octal mode support in spi-nor core: [1] https://patchwork.ozlabs.org/patch/1025081/ [2] https://patchwork.ozlabs.org/patch/1025082/ Changes: v3: Rebase on top of v7 of Yogesh's series[1] v2: spi-nor core patches dropped, are now part of Yogesh's series [1] Declare Octal mode capability based on compatible. Vignesh R (2): dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller .../bindings/mtd/cadence-quadspi.txt | 1 + drivers/mtd/spi-nor/cadence-quadspi.c | 54 ++++++++++++++----- 2 files changed, 43 insertions(+), 12 deletions(-) -- 2.20.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 1/2] dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC 2019-01-16 10:30 ` Vignesh R (?) @ 2019-01-16 10:30 ` Vignesh R -1 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: Boris Brezillon, Tudor.Ambarus Cc: Marek Vasut, Rob Herring, linux-mtd, devicetree, linux-kernel, Vignesh R AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence QSPI controller but supports Octal IO(x8 data lines) and Double Data Rate(DDR) mode. Add new compatible to support OSPI controller on TI's AM654 SoCs. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> --- v3: No changes Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index bb2075df9b38..4345c3a6f530 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -4,6 +4,7 @@ Required properties: - compatible : should be one of the following: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the -- 2.20.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 1/2] dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC @ 2019-01-16 10:30 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: linux-mtd AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence QSPI controller but supports Octal IO(x8 data lines) and Double Data Rate(DDR) mode. Add new compatible to support OSPI controller on TI's AM654 SoCs. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> --- v3: No changes Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index bb2075df9b38..4345c3a6f530 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -4,6 +4,7 @@ Required properties: - compatible : should be one of the following: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the -- 2.20.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 1/2] dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC @ 2019-01-16 10:30 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: Boris Brezillon, Tudor.Ambarus Cc: Marek Vasut, Rob Herring, linux-mtd, devicetree, linux-kernel, Vignesh R AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence QSPI controller but supports Octal IO(x8 data lines) and Double Data Rate(DDR) mode. Add new compatible to support OSPI controller on TI's AM654 SoCs. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> --- v3: No changes Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index bb2075df9b38..4345c3a6f530 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -4,6 +4,7 @@ Required properties: - compatible : should be one of the following: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the -- 2.20.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller 2019-01-16 10:30 ` Vignesh R (?) @ 2019-01-16 10:30 ` Vignesh R -1 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: Boris Brezillon, Tudor.Ambarus Cc: Marek Vasut, Rob Herring, linux-mtd, devicetree, linux-kernel, Vignesh R Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Signed-off-by: Vignesh R <vigneshr@ti.com> --- v3: No changes v2: Declare Octal mode capability based on compatible. drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 04cedd3a2bf6..31ed50f78972 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -93,6 +93,11 @@ struct cqspi_st { struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; }; +struct cqspi_driver_platdata { + u32 hwcaps_mask; + u8 quirks; +}; + /* Operation timeout value */ #define CQSPI_TIMEOUT_MS 500 #define CQSPI_READ_TIMEOUT_MS 10 @@ -101,6 +106,7 @@ struct cqspi_st { #define CQSPI_INST_TYPE_SINGLE 0 #define CQSPI_INST_TYPE_DUAL 1 #define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) case SNOR_PROTO_1_1_4: f_pdata->data_width = CQSPI_INST_TYPE_QUAD; break; + case SNOR_PROTO_1_1_8: + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; + break; default: return -EINVAL; } @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) { - const struct spi_nor_hwcaps hwcaps = { - .mask = SNOR_HWCAPS_READ | - SNOR_HWCAPS_READ_FAST | - SNOR_HWCAPS_READ_1_1_2 | - SNOR_HWCAPS_READ_1_1_4 | - SNOR_HWCAPS_PP, - }; struct platform_device *pdev = cqspi->pdev; struct device *dev = &pdev->dev; + struct cqspi_driver_platdata *ddata; + struct spi_nor_hwcaps hwcaps; struct cqspi_flash_pdata *f_pdata; struct spi_nor *nor; struct mtd_info *mtd; unsigned int cs; int i, ret; + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); + hwcaps.mask = ddata->hwcaps_mask; + /* Get flash device data */ for_each_available_child_of_node(dev->of_node, np) { ret = of_property_read_u32(np, "reg", &cs); @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; - unsigned long data; + struct cqspi_driver_platdata *ddata; int ret; int irq; @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) } cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); - data = (unsigned long)of_device_get_match_data(dev); - if (data & CQSPI_NEEDS_WR_DELAY) + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, cqspi->master_ref_clk_hz); @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { #define CQSPI_DEV_PM_OPS NULL #endif +#define cqspi_base_hwcaps_mask \ + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ + SNOR_HWCAPS_PP) + +static const struct cqspi_driver_platdata cdns_qspi = { + .hwcaps_mask = cqspi_base_hwcaps_mask, +}; + +static const struct cqspi_driver_platdata k2g_qspi = { + .hwcaps_mask = cqspi_base_hwcaps_mask, + .quirks = CQSPI_NEEDS_WR_DELAY, +}; + +static const struct cqspi_driver_platdata am654_ospi = { + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, + .quirks = CQSPI_NEEDS_WR_DELAY, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", - .data = (void *)0, + .data = (void *)&cdns_qspi, }, { .compatible = "ti,k2g-qspi", - .data = (void *)CQSPI_NEEDS_WR_DELAY, + .data = (void *)&k2g_qspi, + }, + { + .compatible = "ti,am654-ospi", + .data = (void *)&am654_ospi, }, { /* end of table */ } }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-16 10:30 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: linux-mtd Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Signed-off-by: Vignesh R <vigneshr@ti.com> --- v3: No changes v2: Declare Octal mode capability based on compatible. drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 04cedd3a2bf6..31ed50f78972 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -93,6 +93,11 @@ struct cqspi_st { struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; }; +struct cqspi_driver_platdata { + u32 hwcaps_mask; + u8 quirks; +}; + /* Operation timeout value */ #define CQSPI_TIMEOUT_MS 500 #define CQSPI_READ_TIMEOUT_MS 10 @@ -101,6 +106,7 @@ struct cqspi_st { #define CQSPI_INST_TYPE_SINGLE 0 #define CQSPI_INST_TYPE_DUAL 1 #define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) case SNOR_PROTO_1_1_4: f_pdata->data_width = CQSPI_INST_TYPE_QUAD; break; + case SNOR_PROTO_1_1_8: + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; + break; default: return -EINVAL; } @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) { - const struct spi_nor_hwcaps hwcaps = { - .mask = SNOR_HWCAPS_READ | - SNOR_HWCAPS_READ_FAST | - SNOR_HWCAPS_READ_1_1_2 | - SNOR_HWCAPS_READ_1_1_4 | - SNOR_HWCAPS_PP, - }; struct platform_device *pdev = cqspi->pdev; struct device *dev = &pdev->dev; + struct cqspi_driver_platdata *ddata; + struct spi_nor_hwcaps hwcaps; struct cqspi_flash_pdata *f_pdata; struct spi_nor *nor; struct mtd_info *mtd; unsigned int cs; int i, ret; + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); + hwcaps.mask = ddata->hwcaps_mask; + /* Get flash device data */ for_each_available_child_of_node(dev->of_node, np) { ret = of_property_read_u32(np, "reg", &cs); @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; - unsigned long data; + struct cqspi_driver_platdata *ddata; int ret; int irq; @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) } cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); - data = (unsigned long)of_device_get_match_data(dev); - if (data & CQSPI_NEEDS_WR_DELAY) + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, cqspi->master_ref_clk_hz); @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { #define CQSPI_DEV_PM_OPS NULL #endif +#define cqspi_base_hwcaps_mask \ + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ + SNOR_HWCAPS_PP) + +static const struct cqspi_driver_platdata cdns_qspi = { + .hwcaps_mask = cqspi_base_hwcaps_mask, +}; + +static const struct cqspi_driver_platdata k2g_qspi = { + .hwcaps_mask = cqspi_base_hwcaps_mask, + .quirks = CQSPI_NEEDS_WR_DELAY, +}; + +static const struct cqspi_driver_platdata am654_ospi = { + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, + .quirks = CQSPI_NEEDS_WR_DELAY, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", - .data = (void *)0, + .data = (void *)&cdns_qspi, }, { .compatible = "ti,k2g-qspi", - .data = (void *)CQSPI_NEEDS_WR_DELAY, + .data = (void *)&k2g_qspi, + }, + { + .compatible = "ti,am654-ospi", + .data = (void *)&am654_ospi, }, { /* end of table */ } }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-16 10:30 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-16 10:30 UTC (permalink / raw) To: Boris Brezillon, Tudor.Ambarus Cc: Marek Vasut, Rob Herring, linux-mtd, devicetree, linux-kernel, Vignesh R Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Signed-off-by: Vignesh R <vigneshr@ti.com> --- v3: No changes v2: Declare Octal mode capability based on compatible. drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 04cedd3a2bf6..31ed50f78972 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -93,6 +93,11 @@ struct cqspi_st { struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; }; +struct cqspi_driver_platdata { + u32 hwcaps_mask; + u8 quirks; +}; + /* Operation timeout value */ #define CQSPI_TIMEOUT_MS 500 #define CQSPI_READ_TIMEOUT_MS 10 @@ -101,6 +106,7 @@ struct cqspi_st { #define CQSPI_INST_TYPE_SINGLE 0 #define CQSPI_INST_TYPE_DUAL 1 #define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) case SNOR_PROTO_1_1_4: f_pdata->data_width = CQSPI_INST_TYPE_QUAD; break; + case SNOR_PROTO_1_1_8: + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; + break; default: return -EINVAL; } @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) { - const struct spi_nor_hwcaps hwcaps = { - .mask = SNOR_HWCAPS_READ | - SNOR_HWCAPS_READ_FAST | - SNOR_HWCAPS_READ_1_1_2 | - SNOR_HWCAPS_READ_1_1_4 | - SNOR_HWCAPS_PP, - }; struct platform_device *pdev = cqspi->pdev; struct device *dev = &pdev->dev; + struct cqspi_driver_platdata *ddata; + struct spi_nor_hwcaps hwcaps; struct cqspi_flash_pdata *f_pdata; struct spi_nor *nor; struct mtd_info *mtd; unsigned int cs; int i, ret; + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); + hwcaps.mask = ddata->hwcaps_mask; + /* Get flash device data */ for_each_available_child_of_node(dev->of_node, np) { ret = of_property_read_u32(np, "reg", &cs); @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; - unsigned long data; + struct cqspi_driver_platdata *ddata; int ret; int irq; @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) } cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); - data = (unsigned long)of_device_get_match_data(dev); - if (data & CQSPI_NEEDS_WR_DELAY) + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, cqspi->master_ref_clk_hz); @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { #define CQSPI_DEV_PM_OPS NULL #endif +#define cqspi_base_hwcaps_mask \ + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ + SNOR_HWCAPS_PP) + +static const struct cqspi_driver_platdata cdns_qspi = { + .hwcaps_mask = cqspi_base_hwcaps_mask, +}; + +static const struct cqspi_driver_platdata k2g_qspi = { + .hwcaps_mask = cqspi_base_hwcaps_mask, + .quirks = CQSPI_NEEDS_WR_DELAY, +}; + +static const struct cqspi_driver_platdata am654_ospi = { + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, + .quirks = CQSPI_NEEDS_WR_DELAY, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", - .data = (void *)0, + .data = (void *)&cdns_qspi, }, { .compatible = "ti,k2g-qspi", - .data = (void *)CQSPI_NEEDS_WR_DELAY, + .data = (void *)&k2g_qspi, + }, + { + .compatible = "ti,am654-ospi", + .data = (void *)&am654_ospi, }, { /* end of table */ } }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller 2019-01-16 10:30 ` Vignesh R (?) @ 2019-01-20 14:56 ` Tudor.Ambarus -1 siblings, 0 replies; 19+ messages in thread From: Tudor.Ambarus @ 2019-01-20 14:56 UTC (permalink / raw) To: vigneshr, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, devicetree, linux-kernel Hi, Vignesh, On 01/16/2019 12:30 PM, Vignesh R wrote: > Cadence OSPI controller IP supports Octal IO (x8 IO lines), > It also has an integrated PHY. IP register layout is very > similar to existing QSPI IP except for additional bits to support Octal > and Octal DDR mode. Therefore, extend current driver to support Octal > mode. > > Signed-off-by: Vignesh R <vigneshr@ti.com> > --- > v3: No changes > > v2: > Declare Octal mode capability based on compatible. > > drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ > 1 file changed, 42 insertions(+), 12 deletions(-) > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index 04cedd3a2bf6..31ed50f78972 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -93,6 +93,11 @@ struct cqspi_st { > struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; > }; > > +struct cqspi_driver_platdata { > + u32 hwcaps_mask; > + u8 quirks; > +}; > + > /* Operation timeout value */ > #define CQSPI_TIMEOUT_MS 500 > #define CQSPI_READ_TIMEOUT_MS 10 > @@ -101,6 +106,7 @@ struct cqspi_st { > #define CQSPI_INST_TYPE_SINGLE 0 > #define CQSPI_INST_TYPE_DUAL 1 > #define CQSPI_INST_TYPE_QUAD 2 > +#define CQSPI_INST_TYPE_OCTAL 3 > > #define CQSPI_DUMMY_CLKS_PER_BYTE 8 > #define CQSPI_DUMMY_BYTES_MAX 4 > @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) > case SNOR_PROTO_1_1_4: > f_pdata->data_width = CQSPI_INST_TYPE_QUAD; > break; > + case SNOR_PROTO_1_1_8: > + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; > + break; > default: > return -EINVAL; > } > @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) > > static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) > { > - const struct spi_nor_hwcaps hwcaps = { > - .mask = SNOR_HWCAPS_READ | > - SNOR_HWCAPS_READ_FAST | > - SNOR_HWCAPS_READ_1_1_2 | > - SNOR_HWCAPS_READ_1_1_4 | > - SNOR_HWCAPS_PP, > - }; > struct platform_device *pdev = cqspi->pdev; > struct device *dev = &pdev->dev; > + struct cqspi_driver_platdata *ddata; const struct cqspi_driver_platdata *ddata; > + struct spi_nor_hwcaps hwcaps; > struct cqspi_flash_pdata *f_pdata; > struct spi_nor *nor; > struct mtd_info *mtd; > unsigned int cs; > int i, ret; > > + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); You forgot to check for NULL. Also, I would expect an implicit type cast, you can drop the explicit cast. > + hwcaps.mask = ddata->hwcaps_mask; > + > /* Get flash device data */ > for_each_available_child_of_node(dev->of_node, np) { > ret = of_property_read_u32(np, "reg", &cs); > @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) > struct cqspi_st *cqspi; > struct resource *res; > struct resource *res_ahb; > - unsigned long data; > + struct cqspi_driver_platdata *ddata; const struct cqspi_driver_platdata *ddata; > int ret; > int irq; > > @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) > } > > cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); > - data = (unsigned long)of_device_get_match_data(dev); > - if (data & CQSPI_NEEDS_WR_DELAY) > + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); I would expect an implicit type cast, you can drop the explicit cast. > + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) > cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, > cqspi->master_ref_clk_hz); > > @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { > #define CQSPI_DEV_PM_OPS NULL > #endif > > +#define cqspi_base_hwcaps_mask \ > + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ > + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ > + SNOR_HWCAPS_PP) > + > +static const struct cqspi_driver_platdata cdns_qspi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask, > +}; > + > +static const struct cqspi_driver_platdata k2g_qspi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask, > + .quirks = CQSPI_NEEDS_WR_DELAY, > +}; > + > +static const struct cqspi_driver_platdata am654_ospi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, > + .quirks = CQSPI_NEEDS_WR_DELAY, > +}; > + > static const struct of_device_id cqspi_dt_ids[] = { > { > .compatible = "cdns,qspi-nor", > - .data = (void *)0, > + .data = (void *)&cdns_qspi, You can drop the (void *) cast. Looks good. Did you test the octal mode with mt35xu512aba? If yes, it would be nice to specify this in the commit message. Cheers, ta > }, > { > .compatible = "ti,k2g-qspi", > - .data = (void *)CQSPI_NEEDS_WR_DELAY, > + .data = (void *)&k2g_qspi, > + }, > + { > + .compatible = "ti,am654-ospi", > + .data = (void *)&am654_ospi, > }, > { /* end of table */ } > }; > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-20 14:56 ` Tudor.Ambarus 0 siblings, 0 replies; 19+ messages in thread From: Tudor.Ambarus @ 2019-01-20 14:56 UTC (permalink / raw) To: vigneshr, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, linux-kernel, devicetree Hi, Vignesh, On 01/16/2019 12:30 PM, Vignesh R wrote: > Cadence OSPI controller IP supports Octal IO (x8 IO lines), > It also has an integrated PHY. IP register layout is very > similar to existing QSPI IP except for additional bits to support Octal > and Octal DDR mode. Therefore, extend current driver to support Octal > mode. > > Signed-off-by: Vignesh R <vigneshr@ti.com> > --- > v3: No changes > > v2: > Declare Octal mode capability based on compatible. > > drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ > 1 file changed, 42 insertions(+), 12 deletions(-) > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index 04cedd3a2bf6..31ed50f78972 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -93,6 +93,11 @@ struct cqspi_st { > struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; > }; > > +struct cqspi_driver_platdata { > + u32 hwcaps_mask; > + u8 quirks; > +}; > + > /* Operation timeout value */ > #define CQSPI_TIMEOUT_MS 500 > #define CQSPI_READ_TIMEOUT_MS 10 > @@ -101,6 +106,7 @@ struct cqspi_st { > #define CQSPI_INST_TYPE_SINGLE 0 > #define CQSPI_INST_TYPE_DUAL 1 > #define CQSPI_INST_TYPE_QUAD 2 > +#define CQSPI_INST_TYPE_OCTAL 3 > > #define CQSPI_DUMMY_CLKS_PER_BYTE 8 > #define CQSPI_DUMMY_BYTES_MAX 4 > @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) > case SNOR_PROTO_1_1_4: > f_pdata->data_width = CQSPI_INST_TYPE_QUAD; > break; > + case SNOR_PROTO_1_1_8: > + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; > + break; > default: > return -EINVAL; > } > @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) > > static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) > { > - const struct spi_nor_hwcaps hwcaps = { > - .mask = SNOR_HWCAPS_READ | > - SNOR_HWCAPS_READ_FAST | > - SNOR_HWCAPS_READ_1_1_2 | > - SNOR_HWCAPS_READ_1_1_4 | > - SNOR_HWCAPS_PP, > - }; > struct platform_device *pdev = cqspi->pdev; > struct device *dev = &pdev->dev; > + struct cqspi_driver_platdata *ddata; const struct cqspi_driver_platdata *ddata; > + struct spi_nor_hwcaps hwcaps; > struct cqspi_flash_pdata *f_pdata; > struct spi_nor *nor; > struct mtd_info *mtd; > unsigned int cs; > int i, ret; > > + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); You forgot to check for NULL. Also, I would expect an implicit type cast, you can drop the explicit cast. > + hwcaps.mask = ddata->hwcaps_mask; > + > /* Get flash device data */ > for_each_available_child_of_node(dev->of_node, np) { > ret = of_property_read_u32(np, "reg", &cs); > @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) > struct cqspi_st *cqspi; > struct resource *res; > struct resource *res_ahb; > - unsigned long data; > + struct cqspi_driver_platdata *ddata; const struct cqspi_driver_platdata *ddata; > int ret; > int irq; > > @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) > } > > cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); > - data = (unsigned long)of_device_get_match_data(dev); > - if (data & CQSPI_NEEDS_WR_DELAY) > + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); I would expect an implicit type cast, you can drop the explicit cast. > + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) > cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, > cqspi->master_ref_clk_hz); > > @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { > #define CQSPI_DEV_PM_OPS NULL > #endif > > +#define cqspi_base_hwcaps_mask \ > + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ > + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ > + SNOR_HWCAPS_PP) > + > +static const struct cqspi_driver_platdata cdns_qspi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask, > +}; > + > +static const struct cqspi_driver_platdata k2g_qspi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask, > + .quirks = CQSPI_NEEDS_WR_DELAY, > +}; > + > +static const struct cqspi_driver_platdata am654_ospi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, > + .quirks = CQSPI_NEEDS_WR_DELAY, > +}; > + > static const struct of_device_id cqspi_dt_ids[] = { > { > .compatible = "cdns,qspi-nor", > - .data = (void *)0, > + .data = (void *)&cdns_qspi, You can drop the (void *) cast. Looks good. Did you test the octal mode with mt35xu512aba? If yes, it would be nice to specify this in the commit message. Cheers, ta > }, > { > .compatible = "ti,k2g-qspi", > - .data = (void *)CQSPI_NEEDS_WR_DELAY, > + .data = (void *)&k2g_qspi, > + }, > + { > + .compatible = "ti,am654-ospi", > + .data = (void *)&am654_ospi, > }, > { /* end of table */ } > }; > ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-20 14:56 ` Tudor.Ambarus 0 siblings, 0 replies; 19+ messages in thread From: Tudor.Ambarus @ 2019-01-20 14:56 UTC (permalink / raw) To: vigneshr, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, devicetree, linux-kernel Hi, Vignesh, On 01/16/2019 12:30 PM, Vignesh R wrote: > Cadence OSPI controller IP supports Octal IO (x8 IO lines), > It also has an integrated PHY. IP register layout is very > similar to existing QSPI IP except for additional bits to support Octal > and Octal DDR mode. Therefore, extend current driver to support Octal > mode. > > Signed-off-by: Vignesh R <vigneshr@ti.com> > --- > v3: No changes > > v2: > Declare Octal mode capability based on compatible. > > drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ > 1 file changed, 42 insertions(+), 12 deletions(-) > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index 04cedd3a2bf6..31ed50f78972 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -93,6 +93,11 @@ struct cqspi_st { > struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; > }; > > +struct cqspi_driver_platdata { > + u32 hwcaps_mask; > + u8 quirks; > +}; > + > /* Operation timeout value */ > #define CQSPI_TIMEOUT_MS 500 > #define CQSPI_READ_TIMEOUT_MS 10 > @@ -101,6 +106,7 @@ struct cqspi_st { > #define CQSPI_INST_TYPE_SINGLE 0 > #define CQSPI_INST_TYPE_DUAL 1 > #define CQSPI_INST_TYPE_QUAD 2 > +#define CQSPI_INST_TYPE_OCTAL 3 > > #define CQSPI_DUMMY_CLKS_PER_BYTE 8 > #define CQSPI_DUMMY_BYTES_MAX 4 > @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) > case SNOR_PROTO_1_1_4: > f_pdata->data_width = CQSPI_INST_TYPE_QUAD; > break; > + case SNOR_PROTO_1_1_8: > + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; > + break; > default: > return -EINVAL; > } > @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) > > static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) > { > - const struct spi_nor_hwcaps hwcaps = { > - .mask = SNOR_HWCAPS_READ | > - SNOR_HWCAPS_READ_FAST | > - SNOR_HWCAPS_READ_1_1_2 | > - SNOR_HWCAPS_READ_1_1_4 | > - SNOR_HWCAPS_PP, > - }; > struct platform_device *pdev = cqspi->pdev; > struct device *dev = &pdev->dev; > + struct cqspi_driver_platdata *ddata; const struct cqspi_driver_platdata *ddata; > + struct spi_nor_hwcaps hwcaps; > struct cqspi_flash_pdata *f_pdata; > struct spi_nor *nor; > struct mtd_info *mtd; > unsigned int cs; > int i, ret; > > + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); You forgot to check for NULL. Also, I would expect an implicit type cast, you can drop the explicit cast. > + hwcaps.mask = ddata->hwcaps_mask; > + > /* Get flash device data */ > for_each_available_child_of_node(dev->of_node, np) { > ret = of_property_read_u32(np, "reg", &cs); > @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) > struct cqspi_st *cqspi; > struct resource *res; > struct resource *res_ahb; > - unsigned long data; > + struct cqspi_driver_platdata *ddata; const struct cqspi_driver_platdata *ddata; > int ret; > int irq; > > @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) > } > > cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); > - data = (unsigned long)of_device_get_match_data(dev); > - if (data & CQSPI_NEEDS_WR_DELAY) > + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); I would expect an implicit type cast, you can drop the explicit cast. > + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) > cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, > cqspi->master_ref_clk_hz); > > @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { > #define CQSPI_DEV_PM_OPS NULL > #endif > > +#define cqspi_base_hwcaps_mask \ > + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ > + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ > + SNOR_HWCAPS_PP) > + > +static const struct cqspi_driver_platdata cdns_qspi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask, > +}; > + > +static const struct cqspi_driver_platdata k2g_qspi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask, > + .quirks = CQSPI_NEEDS_WR_DELAY, > +}; > + > +static const struct cqspi_driver_platdata am654_ospi = { > + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, > + .quirks = CQSPI_NEEDS_WR_DELAY, > +}; > + > static const struct of_device_id cqspi_dt_ids[] = { > { > .compatible = "cdns,qspi-nor", > - .data = (void *)0, > + .data = (void *)&cdns_qspi, You can drop the (void *) cast. Looks good. Did you test the octal mode with mt35xu512aba? If yes, it would be nice to specify this in the commit message. Cheers, ta > }, > { > .compatible = "ti,k2g-qspi", > - .data = (void *)CQSPI_NEEDS_WR_DELAY, > + .data = (void *)&k2g_qspi, > + }, > + { > + .compatible = "ti,am654-ospi", > + .data = (void *)&am654_ospi, > }, > { /* end of table */ } > }; > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller 2019-01-20 14:56 ` Tudor.Ambarus (?) @ 2019-01-20 15:28 ` Tudor.Ambarus -1 siblings, 0 replies; 19+ messages in thread From: Tudor.Ambarus @ 2019-01-20 15:28 UTC (permalink / raw) To: vigneshr, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, devicetree, linux-kernel Vignesh, On 01/20/2019 04:56 PM, Tudor.Ambarus@microchip.com wrote: > Looks good. one more thing: in cqspi_read_setup() I see that the dummy cycles are adjusted if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD). Should you adjust the dummy cycles for octo too? I tried to find a datasheet for the controller, without success though ... ta ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-20 15:28 ` Tudor.Ambarus 0 siblings, 0 replies; 19+ messages in thread From: Tudor.Ambarus @ 2019-01-20 15:28 UTC (permalink / raw) To: vigneshr, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, linux-kernel, devicetree Vignesh, On 01/20/2019 04:56 PM, Tudor.Ambarus@microchip.com wrote: > Looks good. one more thing: in cqspi_read_setup() I see that the dummy cycles are adjusted if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD). Should you adjust the dummy cycles for octo too? I tried to find a datasheet for the controller, without success though ... ta ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-20 15:28 ` Tudor.Ambarus 0 siblings, 0 replies; 19+ messages in thread From: Tudor.Ambarus @ 2019-01-20 15:28 UTC (permalink / raw) To: vigneshr, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, linux-kernel, devicetree Vignesh, On 01/20/2019 04:56 PM, Tudor.Ambarus@microchip.com wrote: > Looks good. one more thing: in cqspi_read_setup() I see that the dummy cycles are adjusted if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD). Should you adjust the dummy cycles for octo too? I tried to find a datasheet for the controller, without success though ... ta ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller 2019-01-20 15:28 ` Tudor.Ambarus @ 2019-01-21 6:00 ` Vignesh R -1 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-21 6:00 UTC (permalink / raw) To: Tudor.Ambarus, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, devicetree, linux-kernel On 20/01/19 8:58 PM, Tudor.Ambarus@microchip.com wrote: > Vignesh, > > On 01/20/2019 04:56 PM, Tudor.Ambarus@microchip.com wrote: >> Looks good. > > one more thing: in cqspi_read_setup() I see that the dummy cycles are adjusted > if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD). > > Should you adjust the dummy cycles for octo too? Driver does not claim support for SNOR_HWCAPS_PP_4_4_4 mode or SNOR_HWCAPS_PP_8_8_8 mode. Therefore inst_width is always be CQSPI_INST_TYPE_SINGLE (cqspi_set_protocol() always sets inst_width and addr_width to CQSPI_INST_TYPE_SINGLE). Code to support 4_4_4 or 8_8_8 mode is incomplete in the driver. Also, using mode bits to satisfy dummy clk cycles does not seem right. My guess is driver is broken, if inst_width is indeed CQSPI_INST_TYPE_QUAD as we end up sending additional 8 dummy clock cycles over what is asked in nor->read_dummy. I will plan to fix these as part of moving driver over to spi-mem. But above code should not impact 1-1-8 mode support. > I tried to find a datasheet for the controller, without success though ... > You can find Octal SPI controller datasheet in AM65x SoC TRM here: http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf Page 9449: 12.3.2 Octal Serial Peripheral Interface (OSPI) -- Regards Vignesh ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-21 6:00 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-21 6:00 UTC (permalink / raw) To: Tudor.Ambarus, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, linux-kernel, devicetree On 20/01/19 8:58 PM, Tudor.Ambarus@microchip.com wrote: > Vignesh, > > On 01/20/2019 04:56 PM, Tudor.Ambarus@microchip.com wrote: >> Looks good. > > one more thing: in cqspi_read_setup() I see that the dummy cycles are adjusted > if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD). > > Should you adjust the dummy cycles for octo too? Driver does not claim support for SNOR_HWCAPS_PP_4_4_4 mode or SNOR_HWCAPS_PP_8_8_8 mode. Therefore inst_width is always be CQSPI_INST_TYPE_SINGLE (cqspi_set_protocol() always sets inst_width and addr_width to CQSPI_INST_TYPE_SINGLE). Code to support 4_4_4 or 8_8_8 mode is incomplete in the driver. Also, using mode bits to satisfy dummy clk cycles does not seem right. My guess is driver is broken, if inst_width is indeed CQSPI_INST_TYPE_QUAD as we end up sending additional 8 dummy clock cycles over what is asked in nor->read_dummy. I will plan to fix these as part of moving driver over to spi-mem. But above code should not impact 1-1-8 mode support. > I tried to find a datasheet for the controller, without success though ... > You can find Octal SPI controller datasheet in AM65x SoC TRM here: http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf Page 9449: 12.3.2 Octal Serial Peripheral Interface (OSPI) -- Regards Vignesh ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller 2019-01-20 14:56 ` Tudor.Ambarus @ 2019-01-21 5:58 ` Vignesh R -1 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-21 5:58 UTC (permalink / raw) To: Tudor.Ambarus, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, devicetree, linux-kernel Hi, Tudor, On 20/01/19 8:26 PM, Tudor.Ambarus@microchip.com wrote: > Hi, Vignesh, > > On 01/16/2019 12:30 PM, Vignesh R wrote: >> Cadence OSPI controller IP supports Octal IO (x8 IO lines), >> It also has an integrated PHY. IP register layout is very >> similar to existing QSPI IP except for additional bits to support Octal >> and Octal DDR mode. Therefore, extend current driver to support Octal >> mode. >> >> Signed-off-by: Vignesh R <vigneshr@ti.com> >> --- >> v3: No changes >> >> v2: >> Declare Octal mode capability based on compatible. >> >> drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ >> 1 file changed, 42 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c >> index 04cedd3a2bf6..31ed50f78972 100644 >> --- a/drivers/mtd/spi-nor/cadence-quadspi.c >> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c >> @@ -93,6 +93,11 @@ struct cqspi_st { >> struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; >> }; >> >> +struct cqspi_driver_platdata { >> + u32 hwcaps_mask; >> + u8 quirks; >> +}; >> + >> /* Operation timeout value */ >> #define CQSPI_TIMEOUT_MS 500 >> #define CQSPI_READ_TIMEOUT_MS 10 >> @@ -101,6 +106,7 @@ struct cqspi_st { >> #define CQSPI_INST_TYPE_SINGLE 0 >> #define CQSPI_INST_TYPE_DUAL 1 >> #define CQSPI_INST_TYPE_QUAD 2 >> +#define CQSPI_INST_TYPE_OCTAL 3 >> >> #define CQSPI_DUMMY_CLKS_PER_BYTE 8 >> #define CQSPI_DUMMY_BYTES_MAX 4 >> @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) >> case SNOR_PROTO_1_1_4: >> f_pdata->data_width = CQSPI_INST_TYPE_QUAD; >> break; >> + case SNOR_PROTO_1_1_8: >> + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; >> + break; >> default: >> return -EINVAL; >> } >> @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) >> >> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) >> { >> - const struct spi_nor_hwcaps hwcaps = { >> - .mask = SNOR_HWCAPS_READ | >> - SNOR_HWCAPS_READ_FAST | >> - SNOR_HWCAPS_READ_1_1_2 | >> - SNOR_HWCAPS_READ_1_1_4 | >> - SNOR_HWCAPS_PP, >> - }; >> struct platform_device *pdev = cqspi->pdev; >> struct device *dev = &pdev->dev; >> + struct cqspi_driver_platdata *ddata; > > const struct cqspi_driver_platdata *ddata; > >> + struct spi_nor_hwcaps hwcaps; >> struct cqspi_flash_pdata *f_pdata; >> struct spi_nor *nor; >> struct mtd_info *mtd; >> unsigned int cs; >> int i, ret; >> >> + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); > > You forgot to check for NULL. Also, I would expect an implicit type cast, you > can drop the explicit cast. > >> + hwcaps.mask = ddata->hwcaps_mask; >> + >> /* Get flash device data */ >> for_each_available_child_of_node(dev->of_node, np) { >> ret = of_property_read_u32(np, "reg", &cs); >> @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) >> struct cqspi_st *cqspi; >> struct resource *res; >> struct resource *res_ahb; >> - unsigned long data; >> + struct cqspi_driver_platdata *ddata; > > const struct cqspi_driver_platdata *ddata; > >> int ret; >> int irq; >> >> @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) >> } >> >> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); >> - data = (unsigned long)of_device_get_match_data(dev); >> - if (data & CQSPI_NEEDS_WR_DELAY) >> + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); > > I would expect an implicit type cast, you can drop the explicit cast. > >> + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) >> cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, >> cqspi->master_ref_clk_hz); >> >> @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { >> #define CQSPI_DEV_PM_OPS NULL >> #endif >> >> +#define cqspi_base_hwcaps_mask \ >> + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ >> + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ >> + SNOR_HWCAPS_PP) >> + >> +static const struct cqspi_driver_platdata cdns_qspi = { >> + .hwcaps_mask = cqspi_base_hwcaps_mask, >> +}; >> + >> +static const struct cqspi_driver_platdata k2g_qspi = { >> + .hwcaps_mask = cqspi_base_hwcaps_mask, >> + .quirks = CQSPI_NEEDS_WR_DELAY, >> +}; >> + >> +static const struct cqspi_driver_platdata am654_ospi = { >> + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, >> + .quirks = CQSPI_NEEDS_WR_DELAY, >> +}; >> + >> static const struct of_device_id cqspi_dt_ids[] = { >> { >> .compatible = "cdns,qspi-nor", >> - .data = (void *)0, >> + .data = (void *)&cdns_qspi, > > You can drop the (void *) cast. > > Looks good. Did you test the octal mode with mt35xu512aba? If yes, it would be > nice to specify this in the commit message. > Yes, octal mode was tested with mt35xu512aba flash. I will address all the comments in v4. Thanks for the review! -- Regards Vignesh ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller @ 2019-01-21 5:58 ` Vignesh R 0 siblings, 0 replies; 19+ messages in thread From: Vignesh R @ 2019-01-21 5:58 UTC (permalink / raw) To: Tudor.Ambarus, bbrezillon Cc: marek.vasut, robh+dt, linux-mtd, linux-kernel, devicetree Hi, Tudor, On 20/01/19 8:26 PM, Tudor.Ambarus@microchip.com wrote: > Hi, Vignesh, > > On 01/16/2019 12:30 PM, Vignesh R wrote: >> Cadence OSPI controller IP supports Octal IO (x8 IO lines), >> It also has an integrated PHY. IP register layout is very >> similar to existing QSPI IP except for additional bits to support Octal >> and Octal DDR mode. Therefore, extend current driver to support Octal >> mode. >> >> Signed-off-by: Vignesh R <vigneshr@ti.com> >> --- >> v3: No changes >> >> v2: >> Declare Octal mode capability based on compatible. >> >> drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++------ >> 1 file changed, 42 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c >> index 04cedd3a2bf6..31ed50f78972 100644 >> --- a/drivers/mtd/spi-nor/cadence-quadspi.c >> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c >> @@ -93,6 +93,11 @@ struct cqspi_st { >> struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; >> }; >> >> +struct cqspi_driver_platdata { >> + u32 hwcaps_mask; >> + u8 quirks; >> +}; >> + >> /* Operation timeout value */ >> #define CQSPI_TIMEOUT_MS 500 >> #define CQSPI_READ_TIMEOUT_MS 10 >> @@ -101,6 +106,7 @@ struct cqspi_st { >> #define CQSPI_INST_TYPE_SINGLE 0 >> #define CQSPI_INST_TYPE_DUAL 1 >> #define CQSPI_INST_TYPE_QUAD 2 >> +#define CQSPI_INST_TYPE_OCTAL 3 >> >> #define CQSPI_DUMMY_CLKS_PER_BYTE 8 >> #define CQSPI_DUMMY_BYTES_MAX 4 >> @@ -911,6 +917,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) >> case SNOR_PROTO_1_1_4: >> f_pdata->data_width = CQSPI_INST_TYPE_QUAD; >> break; >> + case SNOR_PROTO_1_1_8: >> + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; >> + break; >> default: >> return -EINVAL; >> } >> @@ -1213,21 +1222,19 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) >> >> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) >> { >> - const struct spi_nor_hwcaps hwcaps = { >> - .mask = SNOR_HWCAPS_READ | >> - SNOR_HWCAPS_READ_FAST | >> - SNOR_HWCAPS_READ_1_1_2 | >> - SNOR_HWCAPS_READ_1_1_4 | >> - SNOR_HWCAPS_PP, >> - }; >> struct platform_device *pdev = cqspi->pdev; >> struct device *dev = &pdev->dev; >> + struct cqspi_driver_platdata *ddata; > > const struct cqspi_driver_platdata *ddata; > >> + struct spi_nor_hwcaps hwcaps; >> struct cqspi_flash_pdata *f_pdata; >> struct spi_nor *nor; >> struct mtd_info *mtd; >> unsigned int cs; >> int i, ret; >> >> + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); > > You forgot to check for NULL. Also, I would expect an implicit type cast, you > can drop the explicit cast. > >> + hwcaps.mask = ddata->hwcaps_mask; >> + >> /* Get flash device data */ >> for_each_available_child_of_node(dev->of_node, np) { >> ret = of_property_read_u32(np, "reg", &cs); >> @@ -1310,7 +1317,7 @@ static int cqspi_probe(struct platform_device *pdev) >> struct cqspi_st *cqspi; >> struct resource *res; >> struct resource *res_ahb; >> - unsigned long data; >> + struct cqspi_driver_platdata *ddata; > > const struct cqspi_driver_platdata *ddata; > >> int ret; >> int irq; >> >> @@ -1377,8 +1384,8 @@ static int cqspi_probe(struct platform_device *pdev) >> } >> >> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); >> - data = (unsigned long)of_device_get_match_data(dev); >> - if (data & CQSPI_NEEDS_WR_DELAY) >> + ddata = (struct cqspi_driver_platdata *)of_device_get_match_data(dev); > > I would expect an implicit type cast, you can drop the explicit cast. > >> + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) >> cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, >> cqspi->master_ref_clk_hz); >> >> @@ -1460,14 +1467,37 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { >> #define CQSPI_DEV_PM_OPS NULL >> #endif >> >> +#define cqspi_base_hwcaps_mask \ >> + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \ >> + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \ >> + SNOR_HWCAPS_PP) >> + >> +static const struct cqspi_driver_platdata cdns_qspi = { >> + .hwcaps_mask = cqspi_base_hwcaps_mask, >> +}; >> + >> +static const struct cqspi_driver_platdata k2g_qspi = { >> + .hwcaps_mask = cqspi_base_hwcaps_mask, >> + .quirks = CQSPI_NEEDS_WR_DELAY, >> +}; >> + >> +static const struct cqspi_driver_platdata am654_ospi = { >> + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8, >> + .quirks = CQSPI_NEEDS_WR_DELAY, >> +}; >> + >> static const struct of_device_id cqspi_dt_ids[] = { >> { >> .compatible = "cdns,qspi-nor", >> - .data = (void *)0, >> + .data = (void *)&cdns_qspi, > > You can drop the (void *) cast. > > Looks good. Did you test the octal mode with mt35xu512aba? If yes, it would be > nice to specify this in the commit message. > Yes, octal mode was tested with mt35xu512aba flash. I will address all the comments in v4. Thanks for the review! -- Regards Vignesh ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2019-01-21 8:30 UTC | newest] Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-01-16 10:30 [PATCH v3 0/2] cadence-quadspi: Add Octal mode support Vignesh R 2019-01-16 10:30 ` Vignesh R 2019-01-16 10:30 ` Vignesh R 2019-01-16 10:30 ` [PATCH v3 1/2] dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC Vignesh R 2019-01-16 10:30 ` Vignesh R 2019-01-16 10:30 ` Vignesh R 2019-01-16 10:30 ` [PATCH v3 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller Vignesh R 2019-01-16 10:30 ` Vignesh R 2019-01-16 10:30 ` Vignesh R 2019-01-20 14:56 ` Tudor.Ambarus 2019-01-20 14:56 ` Tudor.Ambarus 2019-01-20 14:56 ` Tudor.Ambarus 2019-01-20 15:28 ` Tudor.Ambarus 2019-01-20 15:28 ` Tudor.Ambarus 2019-01-20 15:28 ` Tudor.Ambarus 2019-01-21 6:00 ` Vignesh R 2019-01-21 6:00 ` Vignesh R 2019-01-21 5:58 ` Vignesh R 2019-01-21 5:58 ` Vignesh R
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.