[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Andre Przywara]

This series gathers all remaining patches we need to enable DM_MMC for
Allwinner boards. It relies on the clock gates framework already merged,
and adds the respective gates and resets for each SoC.
It then teaches the sunxi MMC driver to use the clock framework for
those reset and gates clocks. The "mod clock", responsible for setting
the actual interface speed, is still handled in the MMC driver, as the
DM_CLK part of that is not ready yet (and is not trivial).
This allows to turn on DM_MMC, and gets rid of the doomsday warning
message every Allwinner board was blessed with for a while.

This series is available at:
https://github.com/apritzel/u-boot/commits/sunxi-dm-gates

---------------------------

Jagan, can you please have a look whether this is fine? If you are not
sure about patch 7, you can leave this one out for now.
If you are good with it, can you merge it to sunxi/master and send the
PR, so that it still goes into the release?
We can then fix all the remaining issues until the release.

Cheers,
Andre.

Changes in v4:
- Add proper A80 support (special MMC config clock)
- Add V3s support (gates and resets)
- Fix pinmux problem when not booting via SD or eMMC
- smaller fixes per ML discussion
Changes for v3:
- Handle clock via CLK framework.
Changes for v2:
- update the 'reset enablement' logic to do
  required SoC's

Andre Przywara (5):
  sunxi: clk: enable clk and reset for CCU devices
  sunxi: clk: add MMC gates/resets
  sunxi: clk: A80: add MMC clock support
  mmc: sunxi: Add DM clk and reset support
  sunxi: board: do MMC pinmux setup for DM_MMC builds

Jagan Teki (4):
  mmc: sunxi: Add remaining compatible strings
  mmc: sunxi: Add DM_MMC support for H6
  arm: sunxi: Enable DM_MMC
  arm: dts: sunxi: Enumerate MMC2 as MMC1

 arch/arm/Kconfig                      |  1 +
 arch/arm/dts/sunxi-u-boot.dtsi        |  4 +++
 arch/arm/mach-sunxi/Kconfig           |  1 -
 board/sunxi/board.c                   | 15 ++++++++++
 configs/Linksprite_pcDuino3_defconfig |  1 -
 drivers/clk/sunxi/clk_a10.c           |  4 +++
 drivers/clk/sunxi/clk_a10s.c          |  3 ++
 drivers/clk/sunxi/clk_a23.c           |  6 ++++
 drivers/clk/sunxi/clk_a31.c           |  8 +++++
 drivers/clk/sunxi/clk_a64.c           |  6 ++++
 drivers/clk/sunxi/clk_a80.c           | 32 +++++++++++++++++++-
 drivers/clk/sunxi/clk_a83t.c          |  6 ++++
 drivers/clk/sunxi/clk_h3.c            |  6 ++++
 drivers/clk/sunxi/clk_h6.c            |  6 ++++
 drivers/clk/sunxi/clk_r40.c           |  8 +++++
 drivers/clk/sunxi/clk_sunxi.c         | 12 ++++++++
 drivers/clk/sunxi/clk_v3s.c           |  6 ++++
 drivers/mmc/sunxi_mmc.c               | 42 +++++++++++++++++++++++----
 18 files changed, 159 insertions(+), 8 deletions(-)

-- 
2.17.1

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Andre Przywara]

Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.

Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 62ce2994e4..6d4aeb5315 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -8,6 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
+#include <reset.h>
 #include <asm/io.h>
 #include <asm/arch/ccu.h>
 #include <linux/log2.h>
@@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
 int sunxi_clk_probe(struct udevice *dev)
 {
 	struct ccu_priv *priv = dev_get_priv(dev);
+	struct clk_bulk clk_bulk;
+	struct reset_ctl_bulk rst_bulk;
+	int ret;
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
@@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
 	if (!priv->desc)
 		return -EINVAL;
 
+	ret = clk_get_bulk(dev, &clk_bulk);
+	if (!ret)
+		clk_enable_bulk(&clk_bulk);
+
+	ret = reset_get_bulk(dev, &rst_bulk);
+	if (!ret)
+		reset_deassert_bulk(&rst_bulk);
+
 	return 0;
 }
-- 
2.17.1

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> Some Allwinner clock devices have parent clocks and reset gates itself,
> which need to be activated for them to work.
>
> Add some code to just assert all resets and enable all clocks given.
> This should enable the A80 MMC config clock, which requires both to be
> activated. The full CCU devices typically don't require resets, and have
> just fixed clocks as their parents. Since we treat both as optional and
> enabling fixed clocks is a NOP, this works for all cases, without the need
> to differentiate between those clock types.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
> index 62ce2994e4..6d4aeb5315 100644
> --- a/drivers/clk/sunxi/clk_sunxi.c
> +++ b/drivers/clk/sunxi/clk_sunxi.c
> @@ -8,6 +8,7 @@
>  #include <clk-uclass.h>
>  #include <dm.h>
>  #include <errno.h>
> +#include <reset.h>
>  #include <asm/io.h>
>  #include <asm/arch/ccu.h>
>  #include <linux/log2.h>
> @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
>  int sunxi_clk_probe(struct udevice *dev)
>  {
>         struct ccu_priv *priv = dev_get_priv(dev);
> +       struct clk_bulk clk_bulk;
> +       struct reset_ctl_bulk rst_bulk;
> +       int ret;
>
>         priv->base = dev_read_addr_ptr(dev);
>         if (!priv->base)
> @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
>         if (!priv->desc)
>                 return -EINVAL;
>
> +       ret = clk_get_bulk(dev, &clk_bulk);
> +       if (!ret)
> +               clk_enable_bulk(&clk_bulk);
> +
> +       ret = reset_get_bulk(dev, &rst_bulk);
> +       if (!ret)
> +               reset_deassert_bulk(&rst_bulk);
> +

Can't we do this locally to clk_a80 probe?

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Andre Przywara]

On Tue, 29 Jan 2019 23:40:26 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

> On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> <andre.przywara@arm.com> wrote:
> >
> > Some Allwinner clock devices have parent clocks and reset gates
> > itself, which need to be activated for them to work.
> >
> > Add some code to just assert all resets and enable all clocks given.
> > This should enable the A80 MMC config clock, which requires both to
> > be activated. The full CCU devices typically don't require resets,
> > and have just fixed clocks as their parents. Since we treat both as
> > optional and enabling fixed clocks is a NOP, this works for all
> > cases, without the need to differentiate between those clock types.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315 100644
> > --- a/drivers/clk/sunxi/clk_sunxi.c
> > +++ b/drivers/clk/sunxi/clk_sunxi.c
> > @@ -8,6 +8,7 @@
> >  #include <clk-uclass.h>
> >  #include <dm.h>
> >  #include <errno.h>
> > +#include <reset.h>
> >  #include <asm/io.h>
> >  #include <asm/arch/ccu.h>
> >  #include <linux/log2.h>
> > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> >  int sunxi_clk_probe(struct udevice *dev)
> >  {
> >         struct ccu_priv *priv = dev_get_priv(dev);
> > +       struct clk_bulk clk_bulk;
> > +       struct reset_ctl_bulk rst_bulk;
> > +       int ret;
> >
> >         priv->base = dev_read_addr_ptr(dev);
> >         if (!priv->base)
> > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
> >         if (!priv->desc)
> >                 return -EINVAL;
> >
> > +       ret = clk_get_bulk(dev, &clk_bulk);
> > +       if (!ret)
> > +               clk_enable_bulk(&clk_bulk);
> > +
> > +       ret = reset_get_bulk(dev, &rst_bulk);
> > +       if (!ret)
> > +               reset_deassert_bulk(&rst_bulk);
> > +  
> 
> Can't we do this locally to clk_a80 probe?

That's the point: there is no such thing. For all SoCs we use the shared
sunxi_clk_probe() function. Doing this only for the A80 would mean to
split this up, which is duplicating a lot of code for very little
effect. The code here just enables every clock and reset given, which
is generic and should always be the right thing.

Cheers,
Andre.

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Jagan Teki]

On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
<andre.przywara@foss.arm.com> wrote:
>
> On Tue, 29 Jan 2019 23:40:26 +0530
> Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > <andre.przywara@arm.com> wrote:
> > >
> > > Some Allwinner clock devices have parent clocks and reset gates
> > > itself, which need to be activated for them to work.
> > >
> > > Add some code to just assert all resets and enable all clocks given.
> > > This should enable the A80 MMC config clock, which requires both to
> > > be activated. The full CCU devices typically don't require resets,
> > > and have just fixed clocks as their parents. Since we treat both as
> > > optional and enabling fixed clocks is a NOP, this works for all
> > > cases, without the need to differentiate between those clock types.
> > >
> > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > ---
> > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > >  1 file changed, 12 insertions(+)
> > >
> > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315 100644
> > > --- a/drivers/clk/sunxi/clk_sunxi.c
> > > +++ b/drivers/clk/sunxi/clk_sunxi.c
> > > @@ -8,6 +8,7 @@
> > >  #include <clk-uclass.h>
> > >  #include <dm.h>
> > >  #include <errno.h>
> > > +#include <reset.h>
> > >  #include <asm/io.h>
> > >  #include <asm/arch/ccu.h>
> > >  #include <linux/log2.h>
> > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > >  int sunxi_clk_probe(struct udevice *dev)
> > >  {
> > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > +       struct clk_bulk clk_bulk;
> > > +       struct reset_ctl_bulk rst_bulk;
> > > +       int ret;
> > >
> > >         priv->base = dev_read_addr_ptr(dev);
> > >         if (!priv->base)
> > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
> > >         if (!priv->desc)
> > >                 return -EINVAL;
> > >
> > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > +       if (!ret)
> > > +               clk_enable_bulk(&clk_bulk);
> > > +
> > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > +       if (!ret)
> > > +               reset_deassert_bulk(&rst_bulk);
> > > +
> >
> > Can't we do this locally to clk_a80 probe?
>
> That's the point: there is no such thing. For all SoCs we use the shared
> sunxi_clk_probe() function. Doing this only for the A80 would mean to
> split this up, which is duplicating a lot of code for very little
> effect. The code here just enables every clock and reset given, which
> is generic and should always be the right thing.

But enable and dessert of clock and reset is job respective IP driver isn't it?

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Andre Przywara]

On Tue, 29 Jan 2019 23:56:44 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

Hi,

> On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> <andre.przywara@foss.arm.com> wrote:
> >
> > On Tue, 29 Jan 2019 23:40:26 +0530
> > Jagan Teki <jagan@amarulasolutions.com> wrote:
> >  
> > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > <andre.przywara@arm.com> wrote:  
> > > >
> > > > Some Allwinner clock devices have parent clocks and reset gates
> > > > itself, which need to be activated for them to work.
> > > >
> > > > Add some code to just assert all resets and enable all clocks
> > > > given. This should enable the A80 MMC config clock, which
> > > > requires both to be activated. The full CCU devices typically
> > > > don't require resets, and have just fixed clocks as their
> > > > parents. Since we treat both as optional and enabling fixed
> > > > clocks is a NOP, this works for all cases, without the need to
> > > > differentiate between those clock types.
> > > >
> > > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > > ---
> > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > >  1 file changed, 12 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315
> > > > 100644 --- a/drivers/clk/sunxi/clk_sunxi.c
> > > > +++ b/drivers/clk/sunxi/clk_sunxi.c
> > > > @@ -8,6 +8,7 @@
> > > >  #include <clk-uclass.h>
> > > >  #include <dm.h>
> > > >  #include <errno.h>
> > > > +#include <reset.h>
> > > >  #include <asm/io.h>
> > > >  #include <asm/arch/ccu.h>
> > > >  #include <linux/log2.h>
> > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > >  int sunxi_clk_probe(struct udevice *dev)
> > > >  {
> > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > +       struct clk_bulk clk_bulk;
> > > > +       struct reset_ctl_bulk rst_bulk;
> > > > +       int ret;
> > > >
> > > >         priv->base = dev_read_addr_ptr(dev);
> > > >         if (!priv->base)
> > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
> > > >         if (!priv->desc)
> > > >                 return -EINVAL;
> > > >
> > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > +       if (!ret)
> > > > +               clk_enable_bulk(&clk_bulk);
> > > > +
> > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > +       if (!ret)
> > > > +               reset_deassert_bulk(&rst_bulk);
> > > > +  
> > >
> > > Can't we do this locally to clk_a80 probe?  
> >
> > That's the point: there is no such thing. For all SoCs we use the
> > shared sunxi_clk_probe() function. Doing this only for the A80
> > would mean to split this up, which is duplicating a lot of code for
> > very little effect. The code here just enables every clock and
> > reset given, which is generic and should always be the right
> > thing.  
> 
> But enable and dessert of clock and reset is job respective IP driver
> isn't it?

Which IP driver are you thinking about? This is "the IP driver"
for those clock, isn't it?
So you could come up with a completely separate driver for this tiny
A80 MMC config clock, and would find that this is actually almost the
same as the "big" CCU driver (just gates and resets). That's why this
idea of piggy backing on what we already have, just adding the clock
enablement and reset deasserting, which doesn't hurt the "big" driver.

Cheers,
Andre.

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Jagan Teki]

On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Tue, 29 Jan 2019 23:56:44 +0530
> Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Hi,
>
> > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > <andre.przywara@foss.arm.com> wrote:
> > >
> > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >
> > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > <andre.przywara@arm.com> wrote:
> > > > >
> > > > > Some Allwinner clock devices have parent clocks and reset gates
> > > > > itself, which need to be activated for them to work.
> > > > >
> > > > > Add some code to just assert all resets and enable all clocks
> > > > > given. This should enable the A80 MMC config clock, which
> > > > > requires both to be activated. The full CCU devices typically
> > > > > don't require resets, and have just fixed clocks as their
> > > > > parents. Since we treat both as optional and enabling fixed
> > > > > clocks is a NOP, this works for all cases, without the need to
> > > > > differentiate between those clock types.
> > > > >
> > > > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > > > ---
> > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > >  1 file changed, 12 insertions(+)
> > > > >
> > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315
> > > > > 100644 --- a/drivers/clk/sunxi/clk_sunxi.c
> > > > > +++ b/drivers/clk/sunxi/clk_sunxi.c
> > > > > @@ -8,6 +8,7 @@
> > > > >  #include <clk-uclass.h>
> > > > >  #include <dm.h>
> > > > >  #include <errno.h>
> > > > > +#include <reset.h>
> > > > >  #include <asm/io.h>
> > > > >  #include <asm/arch/ccu.h>
> > > > >  #include <linux/log2.h>
> > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > > >  int sunxi_clk_probe(struct udevice *dev)
> > > > >  {
> > > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > > +       struct clk_bulk clk_bulk;
> > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > +       int ret;
> > > > >
> > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > >         if (!priv->base)
> > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
> > > > >         if (!priv->desc)
> > > > >                 return -EINVAL;
> > > > >
> > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > +       if (!ret)
> > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > +
> > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > +       if (!ret)
> > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > +
> > > >
> > > > Can't we do this locally to clk_a80 probe?
> > >
> > > That's the point: there is no such thing. For all SoCs we use the
> > > shared sunxi_clk_probe() function. Doing this only for the A80
> > > would mean to split this up, which is duplicating a lot of code for
> > > very little effect. The code here just enables every clock and
> > > reset given, which is generic and should always be the right
> > > thing.
> >
> > But enable and dessert of clock and reset is job respective IP driver
> > isn't it?
>
> Which IP driver are you thinking about? This is "the IP driver"
> for those clock, isn't it?

IP can be any peripheral like USB, MMC, UART and it those drivers job
to get and enable the clock isn't it?

I assume this code would do the same thing what these peripheral driver do?

> > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > +       if (!ret)
> > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > +
> > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > +       if (!ret)
> > > > > +               reset_deassert_bulk(&rst_bulk);

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Andre Przywara]

On Wed, 30 Jan 2019 16:08:14 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

> On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> <andre.przywara@arm.com> wrote:
> >
> > On Tue, 29 Jan 2019 23:56:44 +0530
> > Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > Hi,
> >  
> > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > <andre.przywara@foss.arm.com> wrote:  
> > > >
> > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > >  
> > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > <andre.przywara@arm.com> wrote:  
> > > > > >
> > > > > > Some Allwinner clock devices have parent clocks and reset
> > > > > > gates itself, which need to be activated for them to work.
> > > > > >
> > > > > > Add some code to just assert all resets and enable all
> > > > > > clocks given. This should enable the A80 MMC config clock,
> > > > > > which requires both to be activated. The full CCU devices
> > > > > > typically don't require resets, and have just fixed clocks
> > > > > > as their parents. Since we treat both as optional and
> > > > > > enabling fixed clocks is a NOP, this works for all cases,
> > > > > > without the need to differentiate between those clock types.
> > > > > >
> > > > > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > > > > ---
> > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > >  1 file changed, 12 insertions(+)
> > > > > >
> > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315
> > > > > > 100644 --- a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > +++ b/drivers/clk/sunxi/clk_sunxi.c
> > > > > > @@ -8,6 +8,7 @@
> > > > > >  #include <clk-uclass.h>
> > > > > >  #include <dm.h>
> > > > > >  #include <errno.h>
> > > > > > +#include <reset.h>
> > > > > >  #include <asm/io.h>
> > > > > >  #include <asm/arch/ccu.h>
> > > > > >  #include <linux/log2.h>
> > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > > > >  int sunxi_clk_probe(struct udevice *dev)
> > > > > >  {
> > > > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > > > +       struct clk_bulk clk_bulk;
> > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > +       int ret;
> > > > > >
> > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > >         if (!priv->base)
> > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
> > > > > >         if (!priv->desc)
> > > > > >                 return -EINVAL;
> > > > > >
> > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > +       if (!ret)
> > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > +
> > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > +       if (!ret)
> > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > +  
> > > > >
> > > > > Can't we do this locally to clk_a80 probe?  
> > > >
> > > > That's the point: there is no such thing. For all SoCs we use
> > > > the shared sunxi_clk_probe() function. Doing this only for the
> > > > A80 would mean to split this up, which is duplicating a lot of
> > > > code for very little effect. The code here just enables every
> > > > clock and reset given, which is generic and should always be
> > > > the right thing.  
> > >
> > > But enable and dessert of clock and reset is job respective IP
> > > driver isn't it?  
> >
> > Which IP driver are you thinking about? This is "the IP driver"
> > for those clock, isn't it?  
> 
> IP can be any peripheral like USB, MMC, UART and it those drivers job
> to get and enable the clock isn't it?

Yes, using the DM_CLK framework. This is what we do: the A80 MMC DT
node refers to the MMC config clock (instead of the generic CCU), and
the MMC driver doesn't care about any requirement this clock has
*itself*.
This is the responsibility of the *A80 MMC config clock driver*, which
we introduce in patch 3/9. So in *this* driver's probe function you
would need to enable the parent clocks, which is exactly what we do.
Just by re-using the existing sunxi_clk_probe() function.

> I assume this code would do the same thing what these peripheral
> driver do?

It does, it's just one layer in between.
-----------------------
A64 MMC driver   A64 CCU driver           fixed clock driver
                 sunxi_clk_probe()
                     clk_enable()    ->   (NULL)
clk_enable()  -> sunxi_clk_enable()
-----------------------
A80 MMC driver   A80 MMC cfg clk driver   A80 CCU driver     fixed clk
                                          sunxi_clk_probe()
                                             clk_enable() -> (NULL)
                 sunxi_clk_probe()
                     clk_enable()    ->   sunxi_clk_enable()
clk_enable()  -> sunxi_clk_enable()
-----------------------

Hope that makes it clearer.

Cheers,
Andre.

> 
> > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > +       if (!ret)
> > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > +
> > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > +       if (!ret)
> > > > > > +               reset_deassert_bulk(&rst_bulk);  

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Jagan Teki]

On Wed, Jan 30, 2019 at 4:26 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Wed, 30 Jan 2019 16:08:14 +0530
> Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> > <andre.przywara@arm.com> wrote:
> > >
> > > On Tue, 29 Jan 2019 23:56:44 +0530
> > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >
> > > Hi,
> > >
> > > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > > <andre.przywara@foss.arm.com> wrote:
> > > > >
> > > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > >
> > > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > > <andre.przywara@arm.com> wrote:
> > > > > > >
> > > > > > > Some Allwinner clock devices have parent clocks and reset
> > > > > > > gates itself, which need to be activated for them to work.
> > > > > > >
> > > > > > > Add some code to just assert all resets and enable all
> > > > > > > clocks given. This should enable the A80 MMC config clock,
> > > > > > > which requires both to be activated. The full CCU devices
> > > > > > > typically don't require resets, and have just fixed clocks
> > > > > > > as their parents. Since we treat both as optional and
> > > > > > > enabling fixed clocks is a NOP, this works for all cases,
> > > > > > > without the need to differentiate between those clock types.
> > > > > > >
> > > > > > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > > > > > ---
> > > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > > >  1 file changed, 12 insertions(+)
> > > > > > >
> > > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315
> > > > > > > 100644 --- a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > +++ b/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > @@ -8,6 +8,7 @@
> > > > > > >  #include <clk-uclass.h>
> > > > > > >  #include <dm.h>
> > > > > > >  #include <errno.h>
> > > > > > > +#include <reset.h>
> > > > > > >  #include <asm/io.h>
> > > > > > >  #include <asm/arch/ccu.h>
> > > > > > >  #include <linux/log2.h>
> > > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > > > > >  int sunxi_clk_probe(struct udevice *dev)
> > > > > > >  {
> > > > > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > > > > +       struct clk_bulk clk_bulk;
> > > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > > +       int ret;
> > > > > > >
> > > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > > >         if (!priv->base)
> > > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev)
> > > > > > >         if (!priv->desc)
> > > > > > >                 return -EINVAL;
> > > > > > >
> > > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > > +       if (!ret)
> > > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > > +
> > > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > > +       if (!ret)
> > > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > > +
> > > > > >
> > > > > > Can't we do this locally to clk_a80 probe?
> > > > >
> > > > > That's the point: there is no such thing. For all SoCs we use
> > > > > the shared sunxi_clk_probe() function. Doing this only for the
> > > > > A80 would mean to split this up, which is duplicating a lot of
> > > > > code for very little effect. The code here just enables every
> > > > > clock and reset given, which is generic and should always be
> > > > > the right thing.
> > > >
> > > > But enable and dessert of clock and reset is job respective IP
> > > > driver isn't it?
> > >
> > > Which IP driver are you thinking about? This is "the IP driver"
> > > for those clock, isn't it?
> >
> > IP can be any peripheral like USB, MMC, UART and it those drivers job
> > to get and enable the clock isn't it?
>
> Yes, using the DM_CLK framework. This is what we do: the A80 MMC DT
> node refers to the MMC config clock (instead of the generic CCU), and
> the MMC driver doesn't care about any requirement this clock has
> *itself*.
> This is the responsibility of the *A80 MMC config clock driver*, which
> we introduce in patch 3/9. So in *this* driver's probe function you
> would need to enable the parent clocks, which is exactly what we do.
> Just by re-using the existing sunxi_clk_probe() function.
>
> > I assume this code would do the same thing what these peripheral
> > driver do?
>
> It does, it's just one layer in between.
> -----------------------
> A64 MMC driver   A64 CCU driver           fixed clock driver
>                  sunxi_clk_probe()
>                      clk_enable()    ->   (NULL)

Ahh.. It didn't effect other clk drivers except A80?

> clk_enable()  -> sunxi_clk_enable()
> -----------------------
> A80 MMC driver   A80 MMC cfg clk driver   A80 CCU driver     fixed clk
>                                           sunxi_clk_probe()
>                                              clk_enable() -> (NULL)
>                  sunxi_clk_probe()
>                      clk_enable()    ->   sunxi_clk_enable()
> clk_enable()  -> sunxi_clk_enable()
> -----------------------

So these bulk enable /deasserts in sunxi_clk_probe will call
respective ops for A80 only and for other the behavior is as before.
it it?

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Andre Przywara]

On Wed, 30 Jan 2019 18:16:44 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

> On Wed, Jan 30, 2019 at 4:26 PM Andre Przywara
> <andre.przywara@arm.com> wrote:
> >
> > On Wed, 30 Jan 2019 16:08:14 +0530
> > Jagan Teki <jagan@amarulasolutions.com> wrote:
> >  
> > > On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> > > <andre.przywara@arm.com> wrote:  
> > > >
> > > > On Tue, 29 Jan 2019 23:56:44 +0530
> > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > >
> > > > Hi,
> > > >  
> > > > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > > > <andre.przywara@foss.arm.com> wrote:  
> > > > > >
> > > > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > >  
> > > > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > > > <andre.przywara@arm.com> wrote:  
> > > > > > > >
> > > > > > > > Some Allwinner clock devices have parent clocks and
> > > > > > > > reset gates itself, which need to be activated for them
> > > > > > > > to work.
> > > > > > > >
> > > > > > > > Add some code to just assert all resets and enable all
> > > > > > > > clocks given. This should enable the A80 MMC config
> > > > > > > > clock, which requires both to be activated. The full
> > > > > > > > CCU devices typically don't require resets, and have
> > > > > > > > just fixed clocks as their parents. Since we treat both
> > > > > > > > as optional and enabling fixed clocks is a NOP, this
> > > > > > > > works for all cases, without the need to differentiate
> > > > > > > > between those clock types.
> > > > > > > >
> > > > > > > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > > > > > > ---
> > > > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > > > >  1 file changed, 12 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c index
> > > > > > > > 62ce2994e4..6d4aeb5315 100644 ---
> > > > > > > > a/drivers/clk/sunxi/clk_sunxi.c +++
> > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@
> > > > > > > >  #include <clk-uclass.h>
> > > > > > > >  #include <dm.h>
> > > > > > > >  #include <errno.h>
> > > > > > > > +#include <reset.h>
> > > > > > > >  #include <asm/io.h>
> > > > > > > >  #include <asm/arch/ccu.h>
> > > > > > > >  #include <linux/log2.h>
> > > > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > > > > > >  int sunxi_clk_probe(struct udevice *dev)
> > > > > > > >  {
> > > > > > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > > > > > +       struct clk_bulk clk_bulk;
> > > > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > > > +       int ret;
> > > > > > > >
> > > > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > > > >         if (!priv->base)
> > > > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice
> > > > > > > > *dev) if (!priv->desc)
> > > > > > > >                 return -EINVAL;
> > > > > > > >
> > > > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > > > +       if (!ret)
> > > > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > > > +
> > > > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > > > +       if (!ret)
> > > > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > > > +  
> > > > > > >
> > > > > > > Can't we do this locally to clk_a80 probe?  
> > > > > >
> > > > > > That's the point: there is no such thing. For all SoCs we
> > > > > > use the shared sunxi_clk_probe() function. Doing this only
> > > > > > for the A80 would mean to split this up, which is
> > > > > > duplicating a lot of code for very little effect. The code
> > > > > > here just enables every clock and reset given, which is
> > > > > > generic and should always be the right thing.  
> > > > >
> > > > > But enable and dessert of clock and reset is job respective IP
> > > > > driver isn't it?  
> > > >
> > > > Which IP driver are you thinking about? This is "the IP driver"
> > > > for those clock, isn't it?  
> > >
> > > IP can be any peripheral like USB, MMC, UART and it those drivers
> > > job to get and enable the clock isn't it?  
> >
> > Yes, using the DM_CLK framework. This is what we do: the A80 MMC DT
> > node refers to the MMC config clock (instead of the generic CCU),
> > and the MMC driver doesn't care about any requirement this clock has
> > *itself*.
> > This is the responsibility of the *A80 MMC config clock driver*,
> > which we introduce in patch 3/9. So in *this* driver's probe
> > function you would need to enable the parent clocks, which is
> > exactly what we do. Just by re-using the existing sunxi_clk_probe()
> > function. 
> > > I assume this code would do the same thing what these peripheral
> > > driver do?  
> >
> > It does, it's just one layer in between.
> > -----------------------
> > A64 MMC driver   A64 CCU driver           fixed clock driver
> >                  sunxi_clk_probe()
> >                      clk_enable()    ->   (NULL)  
> 
> Ahh.. It didn't effect other clk drivers except A80?

It affects every CCU device, but most (all?) of them just don't
specify any resets in the DT and the only clocks most of them have
there are fixed clocks.
And even if they would, enabling clocks and de-asserting resets sounds
like a reasonable thing to do anyway.
So the reset_get_bulk() call will fail (which we don't care about), and
the clk_get_bulk() call will return the two fixed clocks, for which
enable calls are a NOP.
So it works.

Cheers,
Andre.


> 
> > clk_enable()  -> sunxi_clk_enable()
> > -----------------------
> > A80 MMC driver   A80 MMC cfg clk driver   A80 CCU driver     fixed
> > clk sunxi_clk_probe()
> >                                              clk_enable() -> (NULL)
> >                  sunxi_clk_probe()
> >                      clk_enable()    ->   sunxi_clk_enable()
> > clk_enable()  -> sunxi_clk_enable()
> > -----------------------  
> 
> So these bulk enable /deasserts in sunxi_clk_probe will call
> respective ops for A80 only and for other the behavior is as before.
> it it?

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Jagan Teki]

On Wed, Jan 30, 2019 at 7:13 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Wed, 30 Jan 2019 18:16:44 +0530
> Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > On Wed, Jan 30, 2019 at 4:26 PM Andre Przywara
> > <andre.przywara@arm.com> wrote:
> > >
> > > On Wed, 30 Jan 2019 16:08:14 +0530
> > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >
> > > > On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> > > > <andre.przywara@arm.com> wrote:
> > > > >
> > > > > On Tue, 29 Jan 2019 23:56:44 +0530
> > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > >
> > > > > Hi,
> > > > >
> > > > > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > > > > <andre.przywara@foss.arm.com> wrote:
> > > > > > >
> > > > > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > >
> > > > > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > > > > <andre.przywara@arm.com> wrote:
> > > > > > > > >
> > > > > > > > > Some Allwinner clock devices have parent clocks and
> > > > > > > > > reset gates itself, which need to be activated for them
> > > > > > > > > to work.
> > > > > > > > >
> > > > > > > > > Add some code to just assert all resets and enable all
> > > > > > > > > clocks given. This should enable the A80 MMC config
> > > > > > > > > clock, which requires both to be activated. The full
> > > > > > > > > CCU devices typically don't require resets, and have
> > > > > > > > > just fixed clocks as their parents. Since we treat both
> > > > > > > > > as optional and enabling fixed clocks is a NOP, this
> > > > > > > > > works for all cases, without the need to differentiate
> > > > > > > > > between those clock types.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > > > > > > > ---
> > > > > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > > > > >  1 file changed, 12 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c index
> > > > > > > > > 62ce2994e4..6d4aeb5315 100644 ---
> > > > > > > > > a/drivers/clk/sunxi/clk_sunxi.c +++
> > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@
> > > > > > > > >  #include <clk-uclass.h>
> > > > > > > > >  #include <dm.h>
> > > > > > > > >  #include <errno.h>
> > > > > > > > > +#include <reset.h>
> > > > > > > > >  #include <asm/io.h>
> > > > > > > > >  #include <asm/arch/ccu.h>
> > > > > > > > >  #include <linux/log2.h>
> > > > > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > > > > > > >  int sunxi_clk_probe(struct udevice *dev)
> > > > > > > > >  {
> > > > > > > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > > > > > > +       struct clk_bulk clk_bulk;
> > > > > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > > > > +       int ret;
> > > > > > > > >
> > > > > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > > > > >         if (!priv->base)
> > > > > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice
> > > > > > > > > *dev) if (!priv->desc)
> > > > > > > > >                 return -EINVAL;
> > > > > > > > >
> > > > > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > > > > +       if (!ret)
> > > > > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > > > > +
> > > > > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > > > > +       if (!ret)
> > > > > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > > > > +
> > > > > > > >
> > > > > > > > Can't we do this locally to clk_a80 probe?
> > > > > > >
> > > > > > > That's the point: there is no such thing. For all SoCs we
> > > > > > > use the shared sunxi_clk_probe() function. Doing this only
> > > > > > > for the A80 would mean to split this up, which is
> > > > > > > duplicating a lot of code for very little effect. The code
> > > > > > > here just enables every clock and reset given, which is
> > > > > > > generic and should always be the right thing.
> > > > > >
> > > > > > But enable and dessert of clock and reset is job respective IP
> > > > > > driver isn't it?
> > > > >
> > > > > Which IP driver are you thinking about? This is "the IP driver"
> > > > > for those clock, isn't it?
> > > >
> > > > IP can be any peripheral like USB, MMC, UART and it those drivers
> > > > job to get and enable the clock isn't it?
> > >
> > > Yes, using the DM_CLK framework. This is what we do: the A80 MMC DT
> > > node refers to the MMC config clock (instead of the generic CCU),
> > > and the MMC driver doesn't care about any requirement this clock has
> > > *itself*.
> > > This is the responsibility of the *A80 MMC config clock driver*,
> > > which we introduce in patch 3/9. So in *this* driver's probe
> > > function you would need to enable the parent clocks, which is
> > > exactly what we do. Just by re-using the existing sunxi_clk_probe()
> > > function.
> > > > I assume this code would do the same thing what these peripheral
> > > > driver do?
> > >
> > > It does, it's just one layer in between.
> > > -----------------------
> > > A64 MMC driver   A64 CCU driver           fixed clock driver
> > >                  sunxi_clk_probe()
> > >                      clk_enable()    ->   (NULL)
> >
> > Ahh.. It didn't effect other clk drivers except A80?
>
> It affects every CCU device, but most (all?) of them just don't
> specify any resets in the DT and the only clocks most of them have
> there are fixed clocks.
> And even if they would, enabling clocks and de-asserting resets sounds
> like a reasonable thing to do anyway.
> So the reset_get_bulk() call will fail (which we don't care about), and
> the clk_get_bulk() call will return the two fixed clocks, for which
> enable calls are a NOP.
> So it works.

This certainly not so understand to be part of common probe, instead I
would prefer to be part of a80 [1] as of now till CLK framework become
more mature. Let me know, we can push all these to send PR to Tom.

[1] https://paste.ubuntu.com/p/KRgx8kFQjD/



>
> Cheers,
> Andre.
>
>
> >
> > > clk_enable()  -> sunxi_clk_enable()
> > > -----------------------
> > > A80 MMC driver   A80 MMC cfg clk driver   A80 CCU driver     fixed
> > > clk sunxi_clk_probe()
> > >                                              clk_enable() -> (NULL)
> > >                  sunxi_clk_probe()
> > >                      clk_enable()    ->   sunxi_clk_enable()
> > > clk_enable()  -> sunxi_clk_enable()
> > > -----------------------
> >
> > So these bulk enable /deasserts in sunxi_clk_probe will call
> > respective ops for A80 only and for other the behavior is as before.
> > it it?
>


-- 
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Andre Przywara]

On Wed, 30 Jan 2019 19:49:23 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

> On Wed, Jan 30, 2019 at 7:13 PM Andre Przywara
> <andre.przywara@arm.com> wrote:
> >
> > On Wed, 30 Jan 2019 18:16:44 +0530
> > Jagan Teki <jagan@amarulasolutions.com> wrote:
> >  
> > > On Wed, Jan 30, 2019 at 4:26 PM Andre Przywara
> > > <andre.przywara@arm.com> wrote:  
> > > >
> > > > On Wed, 30 Jan 2019 16:08:14 +0530
> > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > >  
> > > > > On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> > > > > <andre.przywara@arm.com> wrote:  
> > > > > >
> > > > > > On Tue, 29 Jan 2019 23:56:44 +0530
> > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > >
> > > > > > Hi,
> > > > > >  
> > > > > > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > > > > > <andre.przywara@foss.arm.com> wrote:  
> > > > > > > >
> > > > > > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > > >  
> > > > > > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > > > > > <andre.przywara@arm.com> wrote:  
> > > > > > > > > >
> > > > > > > > > > Some Allwinner clock devices have parent clocks and
> > > > > > > > > > reset gates itself, which need to be activated for
> > > > > > > > > > them to work.
> > > > > > > > > >
> > > > > > > > > > Add some code to just assert all resets and enable
> > > > > > > > > > all clocks given. This should enable the A80 MMC
> > > > > > > > > > config clock, which requires both to be activated.
> > > > > > > > > > The full CCU devices typically don't require
> > > > > > > > > > resets, and have just fixed clocks as their
> > > > > > > > > > parents. Since we treat both as optional and
> > > > > > > > > > enabling fixed clocks is a NOP, this works for all
> > > > > > > > > > cases, without the need to differentiate between
> > > > > > > > > > those clock types.
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Andre Przywara
> > > > > > > > > > <andre.przywara@arm.com> ---
> > > > > > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > > > > > >  1 file changed, 12 insertions(+)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c index
> > > > > > > > > > 62ce2994e4..6d4aeb5315 100644 ---
> > > > > > > > > > a/drivers/clk/sunxi/clk_sunxi.c +++
> > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@
> > > > > > > > > >  #include <clk-uclass.h>
> > > > > > > > > >  #include <dm.h>
> > > > > > > > > >  #include <errno.h>
> > > > > > > > > > +#include <reset.h>
> > > > > > > > > >  #include <asm/io.h>
> > > > > > > > > >  #include <asm/arch/ccu.h>
> > > > > > > > > >  #include <linux/log2.h>
> > > > > > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > > > > > > > >  int sunxi_clk_probe(struct udevice *dev)
> > > > > > > > > >  {
> > > > > > > > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > > > > > > > +       struct clk_bulk clk_bulk;
> > > > > > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > > > > > +       int ret;
> > > > > > > > > >
> > > > > > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > > > > > >         if (!priv->base)
> > > > > > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct
> > > > > > > > > > udevice *dev) if (!priv->desc)
> > > > > > > > > >                 return -EINVAL;
> > > > > > > > > >
> > > > > > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > > > > > +       if (!ret)
> > > > > > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > > > > > +
> > > > > > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > > > > > +       if (!ret)
> > > > > > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > > > > > +  
> > > > > > > > >
> > > > > > > > > Can't we do this locally to clk_a80 probe?  
> > > > > > > >
> > > > > > > > That's the point: there is no such thing. For all SoCs
> > > > > > > > we use the shared sunxi_clk_probe() function. Doing
> > > > > > > > this only for the A80 would mean to split this up,
> > > > > > > > which is duplicating a lot of code for very little
> > > > > > > > effect. The code here just enables every clock and
> > > > > > > > reset given, which is generic and should always be the
> > > > > > > > right thing.  
> > > > > > >
> > > > > > > But enable and dessert of clock and reset is job
> > > > > > > respective IP driver isn't it?  
> > > > > >
> > > > > > Which IP driver are you thinking about? This is "the IP
> > > > > > driver" for those clock, isn't it?  
> > > > >
> > > > > IP can be any peripheral like USB, MMC, UART and it those
> > > > > drivers job to get and enable the clock isn't it?  
> > > >
> > > > Yes, using the DM_CLK framework. This is what we do: the A80
> > > > MMC DT node refers to the MMC config clock (instead of the
> > > > generic CCU), and the MMC driver doesn't care about any
> > > > requirement this clock has *itself*.
> > > > This is the responsibility of the *A80 MMC config clock driver*,
> > > > which we introduce in patch 3/9. So in *this* driver's probe
> > > > function you would need to enable the parent clocks, which is
> > > > exactly what we do. Just by re-using the existing
> > > > sunxi_clk_probe() function.  
> > > > > I assume this code would do the same thing what these
> > > > > peripheral driver do?  
> > > >
> > > > It does, it's just one layer in between.
> > > > -----------------------
> > > > A64 MMC driver   A64 CCU driver           fixed clock driver
> > > >                  sunxi_clk_probe()
> > > >                      clk_enable()    ->   (NULL)  
> > >
> > > Ahh.. It didn't effect other clk drivers except A80?  
> >
> > It affects every CCU device, but most (all?) of them just don't
> > specify any resets in the DT and the only clocks most of them have
> > there are fixed clocks.
> > And even if they would, enabling clocks and de-asserting resets
> > sounds like a reasonable thing to do anyway.
> > So the reset_get_bulk() call will fail (which we don't care about),
> > and the clk_get_bulk() call will return the two fixed clocks, for
> > which enable calls are a NOP.
> > So it works.  
> 
> This certainly not so understand to be part of common probe, instead I
> would prefer to be part of a80 [1] as of now till CLK framework become
> more mature. Let me know, we can push all these to send PR to Tom.

So you now have this *generic* code exposed to the A80 CCU as well
(which is very similar to all the other CCUs), not only to the A80 MMC
config clock. Sounds like combining the worst parts together: Having an
extra probe routine (which is still generic(!) and duplicates code), but
also exposing it to the CCU which doesn't need it.

So what is your actual problem with this patch here (v4 1/9)?
Are you afraid that it "hurts" the other CCUs?

Cheers,
Andre.

> [1] https://paste.ubuntu.com/p/KRgx8kFQjD/

> > Cheers,
> > Andre.
> >
> >  
> > >  
> > > > clk_enable()  -> sunxi_clk_enable()
> > > > -----------------------
> > > > A80 MMC driver   A80 MMC cfg clk driver   A80 CCU driver
> > > > fixed clk sunxi_clk_probe()
> > > >                                              clk_enable() ->
> > > > (NULL) sunxi_clk_probe()
> > > >                      clk_enable()    ->   sunxi_clk_enable()
> > > > clk_enable()  -> sunxi_clk_enable()
> > > > -----------------------  
> > >
> > > So these bulk enable /deasserts in sunxi_clk_probe will call
> > > respective ops for A80 only and for other the behavior is as
> > > before. it it?  
> >  
> 
> 

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Jagan Teki]

On Wed, Jan 30, 2019 at 8:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Wed, 30 Jan 2019 19:49:23 +0530
> Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > On Wed, Jan 30, 2019 at 7:13 PM Andre Przywara
> > <andre.przywara@arm.com> wrote:
> > >
> > > On Wed, 30 Jan 2019 18:16:44 +0530
> > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >
> > > > On Wed, Jan 30, 2019 at 4:26 PM Andre Przywara
> > > > <andre.przywara@arm.com> wrote:
> > > > >
> > > > > On Wed, 30 Jan 2019 16:08:14 +0530
> > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > >
> > > > > > On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> > > > > > <andre.przywara@arm.com> wrote:
> > > > > > >
> > > > > > > On Tue, 29 Jan 2019 23:56:44 +0530
> > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > >
> > > > > > > Hi,
> > > > > > >
> > > > > > > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > > > > > > <andre.przywara@foss.arm.com> wrote:
> > > > > > > > >
> > > > > > > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > > > >
> > > > > > > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > > > > > > <andre.przywara@arm.com> wrote:
> > > > > > > > > > >
> > > > > > > > > > > Some Allwinner clock devices have parent clocks and
> > > > > > > > > > > reset gates itself, which need to be activated for
> > > > > > > > > > > them to work.
> > > > > > > > > > >
> > > > > > > > > > > Add some code to just assert all resets and enable
> > > > > > > > > > > all clocks given. This should enable the A80 MMC
> > > > > > > > > > > config clock, which requires both to be activated.
> > > > > > > > > > > The full CCU devices typically don't require
> > > > > > > > > > > resets, and have just fixed clocks as their
> > > > > > > > > > > parents. Since we treat both as optional and
> > > > > > > > > > > enabling fixed clocks is a NOP, this works for all
> > > > > > > > > > > cases, without the need to differentiate between
> > > > > > > > > > > those clock types.
> > > > > > > > > > >
> > > > > > > > > > > Signed-off-by: Andre Przywara
> > > > > > > > > > > <andre.przywara@arm.com> ---
> > > > > > > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > > > > > > >  1 file changed, 12 insertions(+)
> > > > > > > > > > >
> > > > > > > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c index
> > > > > > > > > > > 62ce2994e4..6d4aeb5315 100644 ---
> > > > > > > > > > > a/drivers/clk/sunxi/clk_sunxi.c +++
> > > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@
> > > > > > > > > > >  #include <clk-uclass.h>
> > > > > > > > > > >  #include <dm.h>
> > > > > > > > > > >  #include <errno.h>
> > > > > > > > > > > +#include <reset.h>
> > > > > > > > > > >  #include <asm/io.h>
> > > > > > > > > > >  #include <asm/arch/ccu.h>
> > > > > > > > > > >  #include <linux/log2.h>
> > > > > > > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = {
> > > > > > > > > > >  int sunxi_clk_probe(struct udevice *dev)
> > > > > > > > > > >  {
> > > > > > > > > > >         struct ccu_priv *priv = dev_get_priv(dev);
> > > > > > > > > > > +       struct clk_bulk clk_bulk;
> > > > > > > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > > > > > > +       int ret;
> > > > > > > > > > >
> > > > > > > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > > > > > > >         if (!priv->base)
> > > > > > > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct
> > > > > > > > > > > udevice *dev) if (!priv->desc)
> > > > > > > > > > >                 return -EINVAL;
> > > > > > > > > > >
> > > > > > > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > > > > > > +       if (!ret)
> > > > > > > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > > > > > > +
> > > > > > > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > > > > > > +       if (!ret)
> > > > > > > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > > > > > > +
> > > > > > > > > >
> > > > > > > > > > Can't we do this locally to clk_a80 probe?
> > > > > > > > >
> > > > > > > > > That's the point: there is no such thing. For all SoCs
> > > > > > > > > we use the shared sunxi_clk_probe() function. Doing
> > > > > > > > > this only for the A80 would mean to split this up,
> > > > > > > > > which is duplicating a lot of code for very little
> > > > > > > > > effect. The code here just enables every clock and
> > > > > > > > > reset given, which is generic and should always be the
> > > > > > > > > right thing.
> > > > > > > >
> > > > > > > > But enable and dessert of clock and reset is job
> > > > > > > > respective IP driver isn't it?
> > > > > > >
> > > > > > > Which IP driver are you thinking about? This is "the IP
> > > > > > > driver" for those clock, isn't it?
> > > > > >
> > > > > > IP can be any peripheral like USB, MMC, UART and it those
> > > > > > drivers job to get and enable the clock isn't it?
> > > > >
> > > > > Yes, using the DM_CLK framework. This is what we do: the A80
> > > > > MMC DT node refers to the MMC config clock (instead of the
> > > > > generic CCU), and the MMC driver doesn't care about any
> > > > > requirement this clock has *itself*.
> > > > > This is the responsibility of the *A80 MMC config clock driver*,
> > > > > which we introduce in patch 3/9. So in *this* driver's probe
> > > > > function you would need to enable the parent clocks, which is
> > > > > exactly what we do. Just by re-using the existing
> > > > > sunxi_clk_probe() function.
> > > > > > I assume this code would do the same thing what these
> > > > > > peripheral driver do?
> > > > >
> > > > > It does, it's just one layer in between.
> > > > > -----------------------
> > > > > A64 MMC driver   A64 CCU driver           fixed clock driver
> > > > >                  sunxi_clk_probe()
> > > > >                      clk_enable()    ->   (NULL)
> > > >
> > > > Ahh.. It didn't effect other clk drivers except A80?
> > >
> > > It affects every CCU device, but most (all?) of them just don't
> > > specify any resets in the DT and the only clocks most of them have
> > > there are fixed clocks.
> > > And even if they would, enabling clocks and de-asserting resets
> > > sounds like a reasonable thing to do anyway.
> > > So the reset_get_bulk() call will fail (which we don't care about),
> > > and the clk_get_bulk() call will return the two fixed clocks, for
> > > which enable calls are a NOP.
> > > So it works.
> >
> > This certainly not so understand to be part of common probe, instead I
> > would prefer to be part of a80 [1] as of now till CLK framework become
> > more mature. Let me know, we can push all these to send PR to Tom.
>
> So you now have this *generic* code exposed to the A80 CCU as well
> (which is very similar to all the other CCUs), not only to the A80 MMC
> config clock. Sounds like combining the worst parts together: Having an
> extra probe routine (which is still generic(!) and duplicates code), but
> also exposing it to the CCU which doesn't need it.

Yes, I know but we have to wait some time till CLK become more mature. isn't it?
>
> So what is your actual problem with this patch here (v4 1/9)?
> Are you afraid that it "hurts" the other CCUs?

Yes.

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Andre Przywara]

On Wed, 30 Jan 2019 20:17:56 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

> On Wed, Jan 30, 2019 at 8:02 PM Andre Przywara
> <andre.przywara@arm.com> wrote:
> >
> > On Wed, 30 Jan 2019 19:49:23 +0530
> > Jagan Teki <jagan@amarulasolutions.com> wrote:
> >  
> > > On Wed, Jan 30, 2019 at 7:13 PM Andre Przywara
> > > <andre.przywara@arm.com> wrote:  
> > > >
> > > > On Wed, 30 Jan 2019 18:16:44 +0530
> > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > >  
> > > > > On Wed, Jan 30, 2019 at 4:26 PM Andre Przywara
> > > > > <andre.przywara@arm.com> wrote:  
> > > > > >
> > > > > > On Wed, 30 Jan 2019 16:08:14 +0530
> > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > >  
> > > > > > > On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> > > > > > > <andre.przywara@arm.com> wrote:  
> > > > > > > >
> > > > > > > > On Tue, 29 Jan 2019 23:56:44 +0530
> > > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > > >
> > > > > > > > Hi,
> > > > > > > >  
> > > > > > > > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > > > > > > > <andre.przywara@foss.arm.com> wrote:  
> > > > > > > > > >
> > > > > > > > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > > > > >  
> > > > > > > > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > > > > > > > <andre.przywara@arm.com> wrote:  
> > > > > > > > > > > >
> > > > > > > > > > > > Some Allwinner clock devices have parent clocks
> > > > > > > > > > > > and reset gates itself, which need to be
> > > > > > > > > > > > activated for them to work.
> > > > > > > > > > > >
> > > > > > > > > > > > Add some code to just assert all resets and
> > > > > > > > > > > > enable all clocks given. This should enable the
> > > > > > > > > > > > A80 MMC config clock, which requires both to be
> > > > > > > > > > > > activated. The full CCU devices typically don't
> > > > > > > > > > > > require resets, and have just fixed clocks as
> > > > > > > > > > > > their parents. Since we treat both as optional
> > > > > > > > > > > > and enabling fixed clocks is a NOP, this works
> > > > > > > > > > > > for all cases, without the need to
> > > > > > > > > > > > differentiate between those clock types.
> > > > > > > > > > > >
> > > > > > > > > > > > Signed-off-by: Andre Przywara
> > > > > > > > > > > > <andre.przywara@arm.com> ---
> > > > > > > > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > > > > > > > >  1 file changed, 12 insertions(+)
> > > > > > > > > > > >
> > > > > > > > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c index
> > > > > > > > > > > > 62ce2994e4..6d4aeb5315 100644 ---
> > > > > > > > > > > > a/drivers/clk/sunxi/clk_sunxi.c +++
> > > > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@
> > > > > > > > > > > >  #include <clk-uclass.h>
> > > > > > > > > > > >  #include <dm.h>
> > > > > > > > > > > >  #include <errno.h>
> > > > > > > > > > > > +#include <reset.h>
> > > > > > > > > > > >  #include <asm/io.h>
> > > > > > > > > > > >  #include <asm/arch/ccu.h>
> > > > > > > > > > > >  #include <linux/log2.h>
> > > > > > > > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops
> > > > > > > > > > > > = { int sunxi_clk_probe(struct udevice *dev)
> > > > > > > > > > > >  {
> > > > > > > > > > > >         struct ccu_priv *priv =
> > > > > > > > > > > > dev_get_priv(dev);
> > > > > > > > > > > > +       struct clk_bulk clk_bulk;
> > > > > > > > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > > > > > > > +       int ret;
> > > > > > > > > > > >
> > > > > > > > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > > > > > > > >         if (!priv->base)
> > > > > > > > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct
> > > > > > > > > > > > udevice *dev) if (!priv->desc)
> > > > > > > > > > > >                 return -EINVAL;
> > > > > > > > > > > >
> > > > > > > > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > > > > > > > +       if (!ret)
> > > > > > > > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > > > > > > > +
> > > > > > > > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > > > > > > > +       if (!ret)
> > > > > > > > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > > > > > > > +  
> > > > > > > > > > >
> > > > > > > > > > > Can't we do this locally to clk_a80 probe?  
> > > > > > > > > >
> > > > > > > > > > That's the point: there is no such thing. For all
> > > > > > > > > > SoCs we use the shared sunxi_clk_probe() function.
> > > > > > > > > > Doing this only for the A80 would mean to split
> > > > > > > > > > this up, which is duplicating a lot of code for
> > > > > > > > > > very little effect. The code here just enables
> > > > > > > > > > every clock and reset given, which is generic and
> > > > > > > > > > should always be the right thing.  
> > > > > > > > >
> > > > > > > > > But enable and dessert of clock and reset is job
> > > > > > > > > respective IP driver isn't it?  
> > > > > > > >
> > > > > > > > Which IP driver are you thinking about? This is "the IP
> > > > > > > > driver" for those clock, isn't it?  
> > > > > > >
> > > > > > > IP can be any peripheral like USB, MMC, UART and it those
> > > > > > > drivers job to get and enable the clock isn't it?  
> > > > > >
> > > > > > Yes, using the DM_CLK framework. This is what we do: the A80
> > > > > > MMC DT node refers to the MMC config clock (instead of the
> > > > > > generic CCU), and the MMC driver doesn't care about any
> > > > > > requirement this clock has *itself*.
> > > > > > This is the responsibility of the *A80 MMC config clock
> > > > > > driver*, which we introduce in patch 3/9. So in *this*
> > > > > > driver's probe function you would need to enable the parent
> > > > > > clocks, which is exactly what we do. Just by re-using the
> > > > > > existing sunxi_clk_probe() function.  
> > > > > > > I assume this code would do the same thing what these
> > > > > > > peripheral driver do?  
> > > > > >
> > > > > > It does, it's just one layer in between.
> > > > > > -----------------------
> > > > > > A64 MMC driver   A64 CCU driver           fixed clock driver
> > > > > >                  sunxi_clk_probe()
> > > > > >                      clk_enable()    ->   (NULL)  
> > > > >
> > > > > Ahh.. It didn't effect other clk drivers except A80?  
> > > >
> > > > It affects every CCU device, but most (all?) of them just don't
> > > > specify any resets in the DT and the only clocks most of them
> > > > have there are fixed clocks.
> > > > And even if they would, enabling clocks and de-asserting resets
> > > > sounds like a reasonable thing to do anyway.
> > > > So the reset_get_bulk() call will fail (which we don't care
> > > > about), and the clk_get_bulk() call will return the two fixed
> > > > clocks, for which enable calls are a NOP.
> > > > So it works.  
> > >
> > > This certainly not so understand to be part of common probe,
> > > instead I would prefer to be part of a80 [1] as of now till CLK
> > > framework become more mature. Let me know, we can push all these
> > > to send PR to Tom.  
> >
> > So you now have this *generic* code exposed to the A80 CCU as well
> > (which is very similar to all the other CCUs), not only to the A80
> > MMC config clock. Sounds like combining the worst parts together:
> > Having an extra probe routine (which is still generic(!) and
> > duplicates code), but also exposing it to the CCU which doesn't
> > need it.  
> 
> Yes, I know but we have to wait some time till CLK become more
> mature. isn't it?

I don't understand how this would matter. Actually it's a good argument
for merging a simple solution first, then refining it later, if
needed.

> > So what is your actual problem with this patch here (v4 1/9)?
> > Are you afraid that it "hurts" the other CCUs?  
>
> Yes.

I don't see how, and even if, we will know very soon and can still fix
it. If we have the code in for every SoC, we will spot issues easier.
So let's go with a simple and generic solution first.

Cheers,
Andre.

[U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices

[Jagan Teki]

On Wed, Jan 30, 2019 at 9:43 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Wed, 30 Jan 2019 20:17:56 +0530
> Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > On Wed, Jan 30, 2019 at 8:02 PM Andre Przywara
> > <andre.przywara@arm.com> wrote:
> > >
> > > On Wed, 30 Jan 2019 19:49:23 +0530
> > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >
> > > > On Wed, Jan 30, 2019 at 7:13 PM Andre Przywara
> > > > <andre.przywara@arm.com> wrote:
> > > > >
> > > > > On Wed, 30 Jan 2019 18:16:44 +0530
> > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > >
> > > > > > On Wed, Jan 30, 2019 at 4:26 PM Andre Przywara
> > > > > > <andre.przywara@arm.com> wrote:
> > > > > > >
> > > > > > > On Wed, 30 Jan 2019 16:08:14 +0530
> > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > >
> > > > > > > > On Wed, Jan 30, 2019 at 4:04 PM Andre Przywara
> > > > > > > > <andre.przywara@arm.com> wrote:
> > > > > > > > >
> > > > > > > > > On Tue, 29 Jan 2019 23:56:44 +0530
> > > > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > > > >
> > > > > > > > > Hi,
> > > > > > > > >
> > > > > > > > > > On Tue, Jan 29, 2019 at 11:47 PM Andre Przywara
> > > > > > > > > > <andre.przywara@foss.arm.com> wrote:
> > > > > > > > > > >
> > > > > > > > > > > On Tue, 29 Jan 2019 23:40:26 +0530
> > > > > > > > > > > Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > > > > > > > > >
> > > > > > > > > > > > On Tue, Jan 29, 2019 at 9:25 PM Andre Przywara
> > > > > > > > > > > > <andre.przywara@arm.com> wrote:
> > > > > > > > > > > > >
> > > > > > > > > > > > > Some Allwinner clock devices have parent clocks
> > > > > > > > > > > > > and reset gates itself, which need to be
> > > > > > > > > > > > > activated for them to work.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Add some code to just assert all resets and
> > > > > > > > > > > > > enable all clocks given. This should enable the
> > > > > > > > > > > > > A80 MMC config clock, which requires both to be
> > > > > > > > > > > > > activated. The full CCU devices typically don't
> > > > > > > > > > > > > require resets, and have just fixed clocks as
> > > > > > > > > > > > > their parents. Since we treat both as optional
> > > > > > > > > > > > > and enabling fixed clocks is a NOP, this works
> > > > > > > > > > > > > for all cases, without the need to
> > > > > > > > > > > > > differentiate between those clock types.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Signed-off-by: Andre Przywara
> > > > > > > > > > > > > <andre.przywara@arm.com> ---
> > > > > > > > > > > > >  drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++
> > > > > > > > > > > > >  1 file changed, 12 insertions(+)
> > > > > > > > > > > > >
> > > > > > > > > > > > > diff --git a/drivers/clk/sunxi/clk_sunxi.c
> > > > > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c index
> > > > > > > > > > > > > 62ce2994e4..6d4aeb5315 100644 ---
> > > > > > > > > > > > > a/drivers/clk/sunxi/clk_sunxi.c +++
> > > > > > > > > > > > > b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@
> > > > > > > > > > > > >  #include <clk-uclass.h>
> > > > > > > > > > > > >  #include <dm.h>
> > > > > > > > > > > > >  #include <errno.h>
> > > > > > > > > > > > > +#include <reset.h>
> > > > > > > > > > > > >  #include <asm/io.h>
> > > > > > > > > > > > >  #include <asm/arch/ccu.h>
> > > > > > > > > > > > >  #include <linux/log2.h>
> > > > > > > > > > > > > @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops
> > > > > > > > > > > > > = { int sunxi_clk_probe(struct udevice *dev)
> > > > > > > > > > > > >  {
> > > > > > > > > > > > >         struct ccu_priv *priv =
> > > > > > > > > > > > > dev_get_priv(dev);
> > > > > > > > > > > > > +       struct clk_bulk clk_bulk;
> > > > > > > > > > > > > +       struct reset_ctl_bulk rst_bulk;
> > > > > > > > > > > > > +       int ret;
> > > > > > > > > > > > >
> > > > > > > > > > > > >         priv->base = dev_read_addr_ptr(dev);
> > > > > > > > > > > > >         if (!priv->base)
> > > > > > > > > > > > > @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct
> > > > > > > > > > > > > udevice *dev) if (!priv->desc)
> > > > > > > > > > > > >                 return -EINVAL;
> > > > > > > > > > > > >
> > > > > > > > > > > > > +       ret = clk_get_bulk(dev, &clk_bulk);
> > > > > > > > > > > > > +       if (!ret)
> > > > > > > > > > > > > +               clk_enable_bulk(&clk_bulk);
> > > > > > > > > > > > > +
> > > > > > > > > > > > > +       ret = reset_get_bulk(dev, &rst_bulk);
> > > > > > > > > > > > > +       if (!ret)
> > > > > > > > > > > > > +               reset_deassert_bulk(&rst_bulk);
> > > > > > > > > > > > > +
> > > > > > > > > > > >
> > > > > > > > > > > > Can't we do this locally to clk_a80 probe?
> > > > > > > > > > >
> > > > > > > > > > > That's the point: there is no such thing. For all
> > > > > > > > > > > SoCs we use the shared sunxi_clk_probe() function.
> > > > > > > > > > > Doing this only for the A80 would mean to split
> > > > > > > > > > > this up, which is duplicating a lot of code for
> > > > > > > > > > > very little effect. The code here just enables
> > > > > > > > > > > every clock and reset given, which is generic and
> > > > > > > > > > > should always be the right thing.
> > > > > > > > > >
> > > > > > > > > > But enable and dessert of clock and reset is job
> > > > > > > > > > respective IP driver isn't it?
> > > > > > > > >
> > > > > > > > > Which IP driver are you thinking about? This is "the IP
> > > > > > > > > driver" for those clock, isn't it?
> > > > > > > >
> > > > > > > > IP can be any peripheral like USB, MMC, UART and it those
> > > > > > > > drivers job to get and enable the clock isn't it?
> > > > > > >
> > > > > > > Yes, using the DM_CLK framework. This is what we do: the A80
> > > > > > > MMC DT node refers to the MMC config clock (instead of the
> > > > > > > generic CCU), and the MMC driver doesn't care about any
> > > > > > > requirement this clock has *itself*.
> > > > > > > This is the responsibility of the *A80 MMC config clock
> > > > > > > driver*, which we introduce in patch 3/9. So in *this*
> > > > > > > driver's probe function you would need to enable the parent
> > > > > > > clocks, which is exactly what we do. Just by re-using the
> > > > > > > existing sunxi_clk_probe() function.
> > > > > > > > I assume this code would do the same thing what these
> > > > > > > > peripheral driver do?
> > > > > > >
> > > > > > > It does, it's just one layer in between.
> > > > > > > -----------------------
> > > > > > > A64 MMC driver   A64 CCU driver           fixed clock driver
> > > > > > >                  sunxi_clk_probe()
> > > > > > >                      clk_enable()    ->   (NULL)
> > > > > >
> > > > > > Ahh.. It didn't effect other clk drivers except A80?
> > > > >
> > > > > It affects every CCU device, but most (all?) of them just don't
> > > > > specify any resets in the DT and the only clocks most of them
> > > > > have there are fixed clocks.
> > > > > And even if they would, enabling clocks and de-asserting resets
> > > > > sounds like a reasonable thing to do anyway.
> > > > > So the reset_get_bulk() call will fail (which we don't care
> > > > > about), and the clk_get_bulk() call will return the two fixed
> > > > > clocks, for which enable calls are a NOP.
> > > > > So it works.
> > > >
> > > > This certainly not so understand to be part of common probe,
> > > > instead I would prefer to be part of a80 [1] as of now till CLK
> > > > framework become more mature. Let me know, we can push all these
> > > > to send PR to Tom.
> > >
> > > So you now have this *generic* code exposed to the A80 CCU as well
> > > (which is very similar to all the other CCUs), not only to the A80
> > > MMC config clock. Sounds like combining the worst parts together:
> > > Having an extra probe routine (which is still generic(!) and
> > > duplicates code), but also exposing it to the CCU which doesn't
> > > need it.
> >
> > Yes, I know but we have to wait some time till CLK become more
> > mature. isn't it?
>
> I don't understand how this would matter. Actually it's a good argument
> for merging a simple solution first, then refining it later, if
> needed.
>
> > > So what is your actual problem with this patch here (v4 1/9)?
> > > Are you afraid that it "hurts" the other CCUs?
> >
> > Yes.
>
> I don't see how, and even if, we will know very soon and can still fix
> it. If we have the code in for every SoC, we will spot issues easier.
> So let's go with a simple and generic solution first.

Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 2/9] sunxi: clk: add MMC gates/resets

[Andre Przywara]

Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a10.c  | 4 ++++
 drivers/clk/sunxi/clk_a10s.c | 3 +++
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 8 ++++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a80.c  | 4 ++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 6 ++++++
 drivers/clk/sunxi/clk_h6.c   | 6 ++++++
 drivers/clk/sunxi/clk_r40.c  | 8 ++++++++
 drivers/clk/sunxi/clk_v3s.c  | 6 ++++++
 11 files changed, 63 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index b00f51af8b..2aa41efe17 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = {
 	[CLK_AHB_OHCI0]		= GATE(0x060, BIT(2)),
 	[CLK_AHB_EHCI1]		= GATE(0x060, BIT(3)),
 	[CLK_AHB_OHCI1]		= GATE(0x060, BIT(4)),
+	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB_MMC3]		= GATE(0x060, BIT(11)),
 
 	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
 	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index aa904ce067..87b74e52dc 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = {
 	[CLK_AHB_OTG]		= GATE(0x060, BIT(0)),
 	[CLK_AHB_EHCI]		= GATE(0x060, BIT(1)),
 	[CLK_AHB_OHCI]		= GATE(0x060, BIT(2)),
+	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
 
 	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
 	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 854259bf81..1ef2359286 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 
 static struct ccu_clk_gate a23_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),
@@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_OHCI]		= RESET(0x2c0, BIT(29)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index a38d76cb7c..5bd8b7dccc 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 static struct ccu_clk_gate a31_gates[] = {
+	[CLK_AHB1_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB1_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB1_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB1_MMC3]		= GATE(0x060, BIT(11)),
 	[CLK_AHB1_OTG]		= GATE(0x060, BIT(24)),
 	[CLK_AHB1_EHCI0]	= GATE(0x060, BIT(26)),
 	[CLK_AHB1_EHCI1]	= GATE(0x060, BIT(27)),
@@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 
+	[RST_AHB1_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_AHB1_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_AHB1_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_AHB1_MMC3]		= RESET(0x2c0, BIT(11)),
 	[RST_AHB1_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_AHB1_EHCI0]	= RESET(0x2c0, BIT(26)),
 	[RST_AHB1_EHCI1]	= RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index a2ba6eefc5..910275fbce 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static const struct ccu_clk_gate a64_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
@@ -38,6 +41,9 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
 	[RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index d6dd6a1fa1..d4bfb0a98b 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -13,6 +13,8 @@
 #include <dt-bindings/reset/sun9i-a80-ccu.h>
 
 static const struct ccu_clk_gate a80_gates[] = {
+	[CLK_BUS_MMC]		= GATE(0x580, BIT(8)),
+
 	[CLK_BUS_UART0]		= GATE(0x594, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x594, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x594, BIT(18)),
@@ -22,6 +24,8 @@ static const struct ccu_clk_gate a80_gates[] = {
 };
 
 static const struct ccu_reset a80_resets[] = {
+	[RST_BUS_MMC]		= RESET(0x5a0, BIT(8)),
+
 	[RST_BUS_UART0]		= RESET(0x5b4, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x5b4, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x5b4, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 1ef6ac5b25..b5a555da36 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
 
 static struct ccu_clk_gate a83t_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
@@ -36,6 +39,9 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f82949b3b6..416aec2b89 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-h3-ccu.h>
 
 static struct ccu_clk_gate h3_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
@@ -44,6 +47,9 @@ static struct ccu_reset h3_resets[] = {
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 	[RST_USB_PHY3]		= RESET(0x0cc, BIT(3)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(23)),
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(25)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 0da3a40e3d..902612da91 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun50i-h6-ccu.h>
 
 static struct ccu_clk_gate h6_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
 	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
 	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
 	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
@@ -20,6 +23,9 @@ static struct ccu_clk_gate h6_gates[] = {
 };
 
 static struct ccu_reset h6_resets[] = {
+	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
 	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index fd7aae97ea..b9457e1971 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
 
 static struct ccu_clk_gate r40_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(25)),
 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
@@ -43,6 +47,10 @@ static struct ccu_reset r40_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(25)),
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 25ad87500e..c8a9027889 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
 
 static struct ccu_clk_gate v3s_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
@@ -25,6 +28,9 @@ static struct ccu_clk_gate v3s_gates[] = {
 static struct ccu_reset v3s_resets[] = {
 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
 
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
-- 
2.17.1

[U-Boot] [PATCH v4 2/9] sunxi: clk: add MMC gates/resets

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:26 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> Add the MMC clock gates and reset bits for all the Allwinner SoCs.
> This allows them to be used by the MMC driver.
>
> We don't advertise the mod clock yet, as this is still handled by the
> MMC driver.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> [jagan: add V3S gates/resets]

add nit V3S, A80

> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 3/9] sunxi: clk: A80: add MMC clock support

[Andre Przywara]

The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.

Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a80.c | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index d4bfb0a98b..aec1d80c46 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -34,19 +34,45 @@ static const struct ccu_reset a80_resets[] = {
 	[RST_BUS_UART5]		= RESET(0x5b4, BIT(21)),
 };
 
+static const struct ccu_clk_gate a80_mmc_gates[] = {
+	[0]			= GATE(0x0, BIT(16)),
+	[1]			= GATE(0x4, BIT(16)),
+	[2]			= GATE(0x8, BIT(16)),
+	[3]			= GATE(0xc, BIT(16)),
+};
+
+static const struct ccu_reset a80_mmc_resets[] = {
+	[0]			= GATE(0x0, BIT(18)),
+	[1]			= GATE(0x4, BIT(18)),
+	[2]			= GATE(0x8, BIT(18)),
+	[3]			= GATE(0xc, BIT(18)),
+};
+
 static const struct ccu_desc a80_ccu_desc = {
 	.gates = a80_gates,
 	.resets = a80_resets,
 };
 
+static const struct ccu_desc a80_mmc_clk_desc = {
+	.gates = a80_mmc_gates,
+	.resets = a80_mmc_resets,
+};
+
 static int a80_clk_bind(struct udevice *dev)
 {
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets));
+	ulong count = ARRAY_SIZE(a80_resets);
+
+	if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
+		count = ARRAY_SIZE(a80_mmc_resets);
+
+	return sunxi_reset_bind(dev, count);
 }
 
 static const struct udevice_id a80_ccu_ids[] = {
 	{ .compatible = "allwinner,sun9i-a80-ccu",
 	  .data = (ulong)&a80_ccu_desc },
+	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
+	  .data = (ulong)&a80_mmc_clk_desc },
 	{ }
 };
 
-- 
2.17.1

[U-Boot] [PATCH v4 3/9] sunxi: clk: A80: add MMC clock support

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:26 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The A80 handles resets and clock gates for the MMC devices differently,
> outside of the CCU IP block. Consequently we have a separate clock
> device with a separate binding for that.
>
> Implement that with the respective clock gates and resets to allow the
> A80 taking part in the DM_MMC game.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 3/9] sunxi: clk: A80: add MMC clock support

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:26 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The A80 handles resets and clock gates for the MMC devices differently,
> outside of the CCU IP block. Consequently we have a separate clock
> device with a separate binding for that.
>
> Implement that with the respective clock gates and resets to allow the
> A80 taking part in the DM_MMC game.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Fixed commit message, and Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 4/9] mmc: sunxi: Add remaining compatible strings

[Andre Przywara]

From: Jagan Teki <jagan@amarulasolutions.com>

Add MMC compatible strings for A83T, A64, H5.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/mmc/sunxi_mmc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 302332bf97..1259e627cc 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -693,6 +693,18 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	  .compatible = "allwinner,sun7i-a20-mmc",
 	  .data = (ulong)&sun4i_a10_variant,
 	},
+	{
+	  .compatible = "allwinner,sun8i-a83t-emmc",
+	  .data = (ulong)&sun4i_a10_variant,
+	},
+	{
+	  .compatible = "allwinner,sun50i-a64-mmc",
+	  .data = (ulong)&sun4i_a10_variant,
+	},
+	{
+	  .compatible = "allwinner,sun50i-a64-emmc",
+	  .data = (ulong)&sun4i_a10_variant,
+	},
 	{ /* sentinel */ }
 };
 
-- 
2.17.1

[U-Boot] [PATCH v4 4/9] mmc: sunxi: Add remaining compatible strings

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:27 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Add MMC compatible strings for A83T, A64, H5.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 5/9] mmc: sunxi: Add DM_MMC support for H6

[Andre Przywara]

From: Jagan Teki <jagan@amarulasolutions.com>

Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
Connect that with the respective compatible string.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/mmc/sunxi_mmc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 1259e627cc..1e13a0665d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = {
 	.mclk_offset = 0x88,
 };
 
+static const struct sunxi_mmc_variant sun50i_h6_variant = {
+	.mclk_offset = 0x830,
+};
+
 static const struct udevice_id sunxi_mmc_ids[] = {
 	{
 	  .compatible = "allwinner,sun4i-a10-mmc",
@@ -705,6 +709,14 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	  .compatible = "allwinner,sun50i-a64-emmc",
 	  .data = (ulong)&sun4i_a10_variant,
 	},
+	{
+	  .compatible = "allwinner,sun50i-h6-mmc",
+	  .data = (ulong)&sun50i_h6_variant,
+	},
+	{
+	  .compatible = "allwinner,sun50i-h6-emmc",
+	  .data = (ulong)&sun50i_h6_variant,
+	},
 	{ /* sentinel */ }
 };
 
-- 
2.17.1

[U-Boot] [PATCH v4 5/9] mmc: sunxi: Add DM_MMC support for H6

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:26 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
> Connect that with the respective compatible string.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---

Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 6/9] mmc: sunxi: Add DM clk and reset support

[Andre Przywara]

Now that we have the gate clocks and the reset gates in our new
Allwinner clock driver, let's make use of them in the MMC driver, when
DM_MMC is defined.
We treat the reset device as optional now, as the older SoCs don't
implement it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/mmc/sunxi_mmc.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 1e13a0665d..62b658c435 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -12,6 +12,8 @@
 #include <errno.h>
 #include <malloc.h>
 #include <mmc.h>
+#include <clk.h>
+#include <reset.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
@@ -21,7 +23,6 @@
 
 #ifdef CONFIG_DM_MMC
 struct sunxi_mmc_variant {
-	u16 gate_offset;
 	u16 mclk_offset;
 };
 #endif
@@ -607,9 +608,11 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 	struct sunxi_mmc_priv *priv = dev_get_priv(dev);
+	struct reset_ctl_bulk reset_bulk;
+	struct clk gate_clk;
 	struct mmc_config *cfg = &plat->cfg;
 	struct ofnode_phandle_args args;
-	u32 *gate_reg, *ccu_reg;
+	u32 *ccu_reg;
 	int bus_width, ret;
 
 	cfg->name = dev->name;
@@ -641,8 +644,14 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
 	priv->mclkreg = (void *)ccu_reg +
 			(priv->variant->mclk_offset + (priv->mmc_no * 4));
-	gate_reg = (void *)ccu_reg + priv->variant->gate_offset;
-	setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
+
+	ret = clk_get_by_name(dev, "ahb", &gate_clk);
+	if (!ret)
+		clk_enable(&gate_clk);
+
+	ret = reset_get_bulk(dev, &reset_bulk);
+	if (!ret)
+		reset_deassert_bulk(&reset_bulk);
 
 	ret = mmc_set_mod_clk(priv, 24000000);
 	if (ret)
@@ -676,7 +685,6 @@ static int sunxi_mmc_bind(struct udevice *dev)
 }
 
 static const struct sunxi_mmc_variant sun4i_a10_variant = {
-	.gate_offset = 0x60,
 	.mclk_offset = 0x88,
 };
 
-- 
2.17.1

[U-Boot] [PATCH v4 6/9] mmc: sunxi: Add DM clk and reset support

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:28 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> Now that we have the gate clocks and the reset gates in our new
> Allwinner clock driver, let's make use of them in the MMC driver, when
> DM_MMC is defined.
> We treat the reset device as optional now, as the older SoCs don't
> implement it.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---

Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 7/9] sunxi: board: do MMC pinmux setup for DM_MMC builds

[Andre Przywara]

Enabling DM_MMC skips the call to mmc_pinmux_setup() in board.c, as this
is supposed to be handled by the MMC driver, using DT information.

However we don't have a pinctrl driver yet, but would still like to keep
the working pinmux setup for our MMC devices. So bring this particular
call back to the DM_MMC code flow.

When booting from either SD card or eMMC, the SPL does the setup for us,
but when booting from SPI or USB we must not skip this part.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 board/sunxi/board.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index ad14837291..98bc3cd0c1 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -208,6 +208,10 @@ enum env_location env_get_location(enum env_operation op, int prio)
 }
 #endif
 
+#ifdef CONFIG_DM_MMC
+static void mmc_pinmux_setup(int sdc);
+#endif
+
 /* add board specific code here */
 int board_init(void)
 {
@@ -269,6 +273,17 @@ int board_init(void)
 	i2c_init_board();
 #endif
 
+#ifdef CONFIG_DM_MMC
+	/*
+	 * Temporary workaround for enabling MMC clocks until a sunxi DM
+	 * pinctrl driver lands.
+	 */
+	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+#endif
+#endif	/* CONFIG_DM_MMC */
+
 	/* Uses dm gpio code so do this here and not in i2c_init_board() */
 	return soft_i2c_board_init();
 }
-- 
2.17.1

[U-Boot] [PATCH v4 7/9] sunxi: board: do MMC pinmux setup for DM_MMC builds

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:27 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> Enabling DM_MMC skips the call to mmc_pinmux_setup() in board.c, as this
> is supposed to be handled by the MMC driver, using DT information.
>
> However we don't have a pinctrl driver yet, but would still like to keep
> the working pinmux setup for our MMC devices. So bring this particular
> call back to the DM_MMC code flow.
>
> When booting from either SD card or eMMC, the SPL does the setup for us,
> but when booting from SPI or USB we must not skip this part.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---

Add fix details on commit message and Applied to u-boot-sunxi/master

[U-Boot] [PATCH v4 8/9] arm: sunxi: Enable DM_MMC

[Andre Przywara]

From: Jagan Teki <jagan@amarulasolutions.com>

Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.

Also removed DM_MMC enablement in few parts of sunxi
configurations.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/Kconfig                      | 1 +
 arch/arm/mach-sunxi/Kconfig           | 1 -
 configs/Linksprite_pcDuino3_defconfig | 1 -
 3 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cefa8f40d0..f0edb10003 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -851,6 +851,7 @@ config ARCH_SUNXI
 	select DM_ETH
 	select DM_GPIO
 	select DM_KEYBOARD
+	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_USB if DISTRO_DEFAULTS
 	select OF_BOARD_SETUP
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3c54f5106d..74e234cded 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -154,7 +154,6 @@ config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
-	select DM_MMC if MMC
 	select DM_SCSI if SCSI
 	select PHY_SUN4I_USB
 	select DRAM_SUN4I
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 9156f132d1..18f658e96b 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -14,7 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 CONFIG_SCSI_AHCI=y
-CONFIG_DM_MMC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
-- 
2.17.1

[U-Boot] [PATCH v4 9/9] arm: dts: sunxi: Enumerate MMC2 as MMC1

[Andre Przywara]

From: Jagan Teki <jagan@amarulasolutions.com>

Environment and fastboot MMC devices are configured based number
of mmc slots defined on particular board in sunxi platform.

If number of slots are not more than 1, it assigns 0 which usually mmc
device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always
be an mmc device.

If number of slots are more than 1, it assigns 1 which assumes 0 is mmc
device and 1 is emmc device. But with DM_MMC there is chance of detecting
emmc as device 2 since mmc1 is SDIO as per devicetree definition.

So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2
as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.

Some platforms like A20 has mmc0...mmc3, but there is no usecases now for
enabling all mmc controllers in any of A20 board dts files.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 8a9f2a6417..fdd4c80aa4 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -1,6 +1,10 @@
 #include <config.h>
 
 / {
+	aliases {
+		mmc1 = &mmc2;
+	};
+
 	binman {
 		filename = "u-boot-sunxi-with-spl.bin";
 		pad-byte = <0xff>;
-- 
2.17.1

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Jagan Teki]

On Tue, Jan 29, 2019 at 9:24 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> This series gathers all remaining patches we need to enable DM_MMC for
> Allwinner boards. It relies on the clock gates framework already merged,
> and adds the respective gates and resets for each SoC.
> It then teaches the sunxi MMC driver to use the clock framework for
> those reset and gates clocks. The "mod clock", responsible for setting
> the actual interface speed, is still handled in the MMC driver, as the
> DM_CLK part of that is not ready yet (and is not trivial).
> This allows to turn on DM_MMC, and gets rid of the doomsday warning
> message every Allwinner board was blessed with for a while.
>
> This series is available at:
> https://github.com/apritzel/u-boot/commits/sunxi-dm-gates
>
> ---------------------------
>
> Jagan, can you please have a look whether this is fine? If you are not
> sure about patch 7, you can leave this one out for now.
> If you are good with it, can you merge it to sunxi/master and send the
> PR, so that it still goes into the release?
> We can then fix all the remaining issues until the release.
>
> Cheers,
> Andre.
>
> Changes in v4:
> - Add proper A80 support (special MMC config clock)
> - Add V3s support (gates and resets)
> - Fix pinmux problem when not booting via SD or eMMC
> - smaller fixes per ML discussion
> Changes for v3:
> - Handle clock via CLK framework.
> Changes for v2:
> - update the 'reset enablement' logic to do
>   required SoC's
>
> Andre Przywara (5):
>   sunxi: clk: enable clk and reset for CCU devices
>   sunxi: clk: add MMC gates/resets
>   sunxi: clk: A80: add MMC clock support
>   mmc: sunxi: Add DM clk and reset support
>   sunxi: board: do MMC pinmux setup for DM_MMC builds

Does this fix any issue? not sure why is this part of DM_MMC? in fact
I didn't see any issues.

>
> Jagan Teki (4):
>   mmc: sunxi: Add remaining compatible strings
>   mmc: sunxi: Add DM_MMC support for H6
>   arm: sunxi: Enable DM_MMC
>   arm: dts: sunxi: Enumerate MMC2 as MMC1

I have next version change for this? will replace.

patch [1] should be also be part of the DM_MMC w/o this SD is unable
to detect in sopine boards.

[1] https://patchwork.ozlabs.org/patch/1027858/

Pritt, can you test the FEL that you mentioned on IRC?

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Andre Przywara]

On Tue, 29 Jan 2019 23:12:17 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

Hi,

> On Tue, Jan 29, 2019 at 9:24 PM Andre Przywara
> <andre.przywara@arm.com> wrote:
> >
> > This series gathers all remaining patches we need to enable DM_MMC
> > for Allwinner boards. It relies on the clock gates framework
> > already merged, and adds the respective gates and resets for each
> > SoC. It then teaches the sunxi MMC driver to use the clock
> > framework for those reset and gates clocks. The "mod clock",
> > responsible for setting the actual interface speed, is still
> > handled in the MMC driver, as the DM_CLK part of that is not ready
> > yet (and is not trivial). This allows to turn on DM_MMC, and gets
> > rid of the doomsday warning message every Allwinner board was
> > blessed with for a while.
> >
> > This series is available at:
> > https://github.com/apritzel/u-boot/commits/sunxi-dm-gates
> >
> > ---------------------------
> >
> > Jagan, can you please have a look whether this is fine? If you are
> > not sure about patch 7, you can leave this one out for now.
> > If you are good with it, can you merge it to sunxi/master and send
> > the PR, so that it still goes into the release?
> > We can then fix all the remaining issues until the release.
> >
> > Cheers,
> > Andre.
> >
> > Changes in v4:
> > - Add proper A80 support (special MMC config clock)
> > - Add V3s support (gates and resets)
> > - Fix pinmux problem when not booting via SD or eMMC
> > - smaller fixes per ML discussion
> > Changes for v3:
> > - Handle clock via CLK framework.
> > Changes for v2:
> > - update the 'reset enablement' logic to do
> >   required SoC's
> >
> > Andre Przywara (5):
> >   sunxi: clk: enable clk and reset for CCU devices
> >   sunxi: clk: add MMC gates/resets
> >   sunxi: clk: A80: add MMC clock support
> >   mmc: sunxi: Add DM clk and reset support
> >   sunxi: board: do MMC pinmux setup for DM_MMC builds  
> 
> Does this fix any issue? not sure why is this part of DM_MMC? in fact
> I didn't see any issues.

This fixes boot via FEL or SPI flash, where the SPL won't setup the
pinmux for us. I should have mentioned that explicitly in the commit
message, sorry.

> >
> > Jagan Teki (4):
> >   mmc: sunxi: Add remaining compatible strings
> >   mmc: sunxi: Add DM_MMC support for H6
> >   arm: sunxi: Enable DM_MMC
> >   arm: dts: sunxi: Enumerate MMC2 as MMC1  
> 
> I have next version change for this? will replace.
> 
> patch [1] should be also be part of the DM_MMC w/o this SD is unable
> to detect in sopine boards.

I know, if you are OK with it, can you please add it to the series, at
best with your Reviewed-by? Otherwise we can still take it later as a
fix.

Thanks,
Andre

> [1] https://patchwork.ozlabs.org/patch/1027858/
> 
> Pritt, can you test the FEL that you mentioned on IRC?

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Jagan Teki]

On Tue, Jan 29, 2019 at 11:20 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Tue, 29 Jan 2019 23:12:17 +0530
> Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Hi,
>
> > On Tue, Jan 29, 2019 at 9:24 PM Andre Przywara
> > <andre.przywara@arm.com> wrote:
> > >
> > > This series gathers all remaining patches we need to enable DM_MMC
> > > for Allwinner boards. It relies on the clock gates framework
> > > already merged, and adds the respective gates and resets for each
> > > SoC. It then teaches the sunxi MMC driver to use the clock
> > > framework for those reset and gates clocks. The "mod clock",
> > > responsible for setting the actual interface speed, is still
> > > handled in the MMC driver, as the DM_CLK part of that is not ready
> > > yet (and is not trivial). This allows to turn on DM_MMC, and gets
> > > rid of the doomsday warning message every Allwinner board was
> > > blessed with for a while.
> > >
> > > This series is available at:
> > > https://github.com/apritzel/u-boot/commits/sunxi-dm-gates
> > >
> > > ---------------------------
> > >
> > > Jagan, can you please have a look whether this is fine? If you are
> > > not sure about patch 7, you can leave this one out for now.
> > > If you are good with it, can you merge it to sunxi/master and send
> > > the PR, so that it still goes into the release?
> > > We can then fix all the remaining issues until the release.
> > >
> > > Cheers,
> > > Andre.
> > >
> > > Changes in v4:
> > > - Add proper A80 support (special MMC config clock)
> > > - Add V3s support (gates and resets)
> > > - Fix pinmux problem when not booting via SD or eMMC
> > > - smaller fixes per ML discussion
> > > Changes for v3:
> > > - Handle clock via CLK framework.
> > > Changes for v2:
> > > - update the 'reset enablement' logic to do
> > >   required SoC's
> > >
> > > Andre Przywara (5):
> > >   sunxi: clk: enable clk and reset for CCU devices
> > >   sunxi: clk: add MMC gates/resets
> > >   sunxi: clk: A80: add MMC clock support
> > >   mmc: sunxi: Add DM clk and reset support
> > >   sunxi: board: do MMC pinmux setup for DM_MMC builds
> >
> > Does this fix any issue? not sure why is this part of DM_MMC? in fact
> > I didn't see any issues.
>
> This fixes boot via FEL or SPI flash, where the SPL won't setup the
> pinmux for us. I should have mentioned that explicitly in the commit
> message, sorry.

np, may be i will add while applying. and is this FEL issue that Pritt
pointed out?

>
> > >
> > > Jagan Teki (4):
> > >   mmc: sunxi: Add remaining compatible strings
> > >   mmc: sunxi: Add DM_MMC support for H6
> > >   arm: sunxi: Enable DM_MMC
> > >   arm: dts: sunxi: Enumerate MMC2 as MMC1
> >
> > I have next version change for this? will replace.
> >
> > patch [1] should be also be part of the DM_MMC w/o this SD is unable
> > to detect in sopine boards.
>
> I know, if you are OK with it, can you please add it to the series, at
> best with your Reviewed-by? Otherwise we can still take it later as a
> fix.

Will take this, anyway.

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Tomas Novotny]

Hi Andre,

On Tue, 29 Jan 2019 15:54:07 +0000, Andre Przywara <andre.przywara@arm.com>
wrote:
> This series gathers all remaining patches we need to enable DM_MMC for
> Allwinner boards. It relies on the clock gates framework already merged,
> and adds the respective gates and resets for each SoC.
> It then teaches the sunxi MMC driver to use the clock framework for
> those reset and gates clocks. The "mod clock", responsible for setting
> the actual interface speed, is still handled in the MMC driver, as the
> DM_CLK part of that is not ready yet (and is not trivial).
> This allows to turn on DM_MMC, and gets rid of the doomsday warning
> message every Allwinner board was blessed with for a while.
> 
> This series is available at:
> https://github.com/apritzel/u-boot/commits/sunxi-dm-gates

I've briefly tested that branch on A83t mainlined tablet (TBS A711). I was
able to boot from SD card and eMMC.

Just noticed that message:
MMC:   Device 'mmc at 1c11000': seq 1 is in use by 'mmc at 1c10000'
mmc at 1c0f000: 0, mmc at 1c10000: 2, mmc at 1c11000: 1
I guess that this is the mmc1/2 renaming stuff?

With 2019.01 I got:
MMC:   SUNXI SD/MMC: 0, SUNXI SD/MMC: 1

Tomas

> ---------------------------
> 
> Jagan, can you please have a look whether this is fine? If you are not
> sure about patch 7, you can leave this one out for now.
> If you are good with it, can you merge it to sunxi/master and send the
> PR, so that it still goes into the release?
> We can then fix all the remaining issues until the release.
> 
> Cheers,
> Andre.
> 
> Changes in v4:
> - Add proper A80 support (special MMC config clock)
> - Add V3s support (gates and resets)
> - Fix pinmux problem when not booting via SD or eMMC
> - smaller fixes per ML discussion
> Changes for v3:
> - Handle clock via CLK framework.
> Changes for v2:
> - update the 'reset enablement' logic to do
>   required SoC's
> 
> Andre Przywara (5):
>   sunxi: clk: enable clk and reset for CCU devices
>   sunxi: clk: add MMC gates/resets
>   sunxi: clk: A80: add MMC clock support
>   mmc: sunxi: Add DM clk and reset support
>   sunxi: board: do MMC pinmux setup for DM_MMC builds
> 
> Jagan Teki (4):
>   mmc: sunxi: Add remaining compatible strings
>   mmc: sunxi: Add DM_MMC support for H6
>   arm: sunxi: Enable DM_MMC
>   arm: dts: sunxi: Enumerate MMC2 as MMC1
> 
>  arch/arm/Kconfig                      |  1 +
>  arch/arm/dts/sunxi-u-boot.dtsi        |  4 +++
>  arch/arm/mach-sunxi/Kconfig           |  1 -
>  board/sunxi/board.c                   | 15 ++++++++++
>  configs/Linksprite_pcDuino3_defconfig |  1 -
>  drivers/clk/sunxi/clk_a10.c           |  4 +++
>  drivers/clk/sunxi/clk_a10s.c          |  3 ++
>  drivers/clk/sunxi/clk_a23.c           |  6 ++++
>  drivers/clk/sunxi/clk_a31.c           |  8 +++++
>  drivers/clk/sunxi/clk_a64.c           |  6 ++++
>  drivers/clk/sunxi/clk_a80.c           | 32 +++++++++++++++++++-
>  drivers/clk/sunxi/clk_a83t.c          |  6 ++++
>  drivers/clk/sunxi/clk_h3.c            |  6 ++++
>  drivers/clk/sunxi/clk_h6.c            |  6 ++++
>  drivers/clk/sunxi/clk_r40.c           |  8 +++++
>  drivers/clk/sunxi/clk_sunxi.c         | 12 ++++++++
>  drivers/clk/sunxi/clk_v3s.c           |  6 ++++
>  drivers/mmc/sunxi_mmc.c               | 42 +++++++++++++++++++++++----
>  18 files changed, 159 insertions(+), 8 deletions(-)
> 

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Andre Przywara]

On Wed, 30 Jan 2019 11:16:07 +0100
Tomas Novotny <tomas@novotny.cz> wrote:

Hi,

> On Tue, 29 Jan 2019 15:54:07 +0000, Andre Przywara
> <andre.przywara@arm.com> wrote:
> > This series gathers all remaining patches we need to enable DM_MMC
> > for Allwinner boards. It relies on the clock gates framework
> > already merged, and adds the respective gates and resets for each
> > SoC. It then teaches the sunxi MMC driver to use the clock
> > framework for those reset and gates clocks. The "mod clock",
> > responsible for setting the actual interface speed, is still
> > handled in the MMC driver, as the DM_CLK part of that is not ready
> > yet (and is not trivial). This allows to turn on DM_MMC, and gets
> > rid of the doomsday warning message every Allwinner board was
> > blessed with for a while.
> > 
> > This series is available at:
> > https://github.com/apritzel/u-boot/commits/sunxi-dm-gates  
> 
> I've briefly tested that branch on A83t mainlined tablet (TBS A711).
> I was able to boot from SD card and eMMC.
> 
> Just noticed that message:
> MMC:   Device 'mmc at 1c11000': seq 1 is in use by 'mmc at 1c10000'
> mmc at 1c0f000: 0, mmc at 1c10000: 2, mmc at 1c11000: 1
> I guess that this is the mmc1/2 renaming stuff?

I think so. So is this just a warning, and it continues anyway and
works?

TBH, I don't like this patch 9/9 very much, I actually believe relying
on this numbering scheme in /aliases is something odd and fragile.
Especially since Linux (and other OSes) seem to get away without it.

For MMC, can't we just enumerate them dynamically? AFAIU the MMC driver
would not probe a block device successfully on an SDIO device, would it?

But for the sake of having something working, I am fine with the patch,
at least on a for-now basis.

Cheers,
Andre.
 
> With 2019.01 I got:
> MMC:   SUNXI SD/MMC: 0, SUNXI SD/MMC: 1
> 
> Tomas
> 
> > ---------------------------
> > 
> > Jagan, can you please have a look whether this is fine? If you are
> > not sure about patch 7, you can leave this one out for now.
> > If you are good with it, can you merge it to sunxi/master and send
> > the PR, so that it still goes into the release?
> > We can then fix all the remaining issues until the release.
> > 
> > Cheers,
> > Andre.
> > 
> > Changes in v4:
> > - Add proper A80 support (special MMC config clock)
> > - Add V3s support (gates and resets)
> > - Fix pinmux problem when not booting via SD or eMMC
> > - smaller fixes per ML discussion
> > Changes for v3:
> > - Handle clock via CLK framework.
> > Changes for v2:
> > - update the 'reset enablement' logic to do
> >   required SoC's
> > 
> > Andre Przywara (5):
> >   sunxi: clk: enable clk and reset for CCU devices
> >   sunxi: clk: add MMC gates/resets
> >   sunxi: clk: A80: add MMC clock support
> >   mmc: sunxi: Add DM clk and reset support
> >   sunxi: board: do MMC pinmux setup for DM_MMC builds
> > 
> > Jagan Teki (4):
> >   mmc: sunxi: Add remaining compatible strings
> >   mmc: sunxi: Add DM_MMC support for H6
> >   arm: sunxi: Enable DM_MMC
> >   arm: dts: sunxi: Enumerate MMC2 as MMC1
> > 
> >  arch/arm/Kconfig                      |  1 +
> >  arch/arm/dts/sunxi-u-boot.dtsi        |  4 +++
> >  arch/arm/mach-sunxi/Kconfig           |  1 -
> >  board/sunxi/board.c                   | 15 ++++++++++
> >  configs/Linksprite_pcDuino3_defconfig |  1 -
> >  drivers/clk/sunxi/clk_a10.c           |  4 +++
> >  drivers/clk/sunxi/clk_a10s.c          |  3 ++
> >  drivers/clk/sunxi/clk_a23.c           |  6 ++++
> >  drivers/clk/sunxi/clk_a31.c           |  8 +++++
> >  drivers/clk/sunxi/clk_a64.c           |  6 ++++
> >  drivers/clk/sunxi/clk_a80.c           | 32 +++++++++++++++++++-
> >  drivers/clk/sunxi/clk_a83t.c          |  6 ++++
> >  drivers/clk/sunxi/clk_h3.c            |  6 ++++
> >  drivers/clk/sunxi/clk_h6.c            |  6 ++++
> >  drivers/clk/sunxi/clk_r40.c           |  8 +++++
> >  drivers/clk/sunxi/clk_sunxi.c         | 12 ++++++++
> >  drivers/clk/sunxi/clk_v3s.c           |  6 ++++
> >  drivers/mmc/sunxi_mmc.c               | 42
> > +++++++++++++++++++++++---- 18 files changed, 159 insertions(+), 8
> > deletions(-) 
> 
> 

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Jagan Teki]

On Wed, Jan 30, 2019 at 5:17 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Wed, 30 Jan 2019 11:16:07 +0100
> Tomas Novotny <tomas@novotny.cz> wrote:
>
> Hi,
>
> > On Tue, 29 Jan 2019 15:54:07 +0000, Andre Przywara
> > <andre.przywara@arm.com> wrote:
> > > This series gathers all remaining patches we need to enable DM_MMC
> > > for Allwinner boards. It relies on the clock gates framework
> > > already merged, and adds the respective gates and resets for each
> > > SoC. It then teaches the sunxi MMC driver to use the clock
> > > framework for those reset and gates clocks. The "mod clock",
> > > responsible for setting the actual interface speed, is still
> > > handled in the MMC driver, as the DM_CLK part of that is not ready
> > > yet (and is not trivial). This allows to turn on DM_MMC, and gets
> > > rid of the doomsday warning message every Allwinner board was
> > > blessed with for a while.
> > >
> > > This series is available at:
> > > https://github.com/apritzel/u-boot/commits/sunxi-dm-gates
> >
> > I've briefly tested that branch on A83t mainlined tablet (TBS A711).
> > I was able to boot from SD card and eMMC.
> >
> > Just noticed that message:
> > MMC:   Device 'mmc at 1c11000': seq 1 is in use by 'mmc at 1c10000'
> > mmc at 1c0f000: 0, mmc at 1c10000: 2, mmc at 1c11000: 1
> > I guess that this is the mmc1/2 renaming stuff?
>
> I think so. So is this just a warning, and it continues anyway and
> works?
>
> TBH, I don't like this patch 9/9 very much, I actually believe relying
> on this numbering scheme in /aliases is something odd and fragile.
> Especially since Linux (and other OSes) seem to get away without it.
>
> For MMC, can't we just enumerate them dynamically? AFAIU the MMC driver
> would not probe a block device successfully on an SDIO device, would it?
>
> But for the sake of having something working, I am fine with the patch,
> at least on a for-now basis.

It's not a simple think that 9/9 fix is for,It's something big like
w/o that we can't get the default env and fastboot devices because we
always assign mmc1 for these purposes and indeed mmc1 is SDIO for DT
enumeration.

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Andre Przywara]

On Wed, 30 Jan 2019 18:20:31 +0530
Jagan Teki <jagan@amarulasolutions.com> wrote:

> On Wed, Jan 30, 2019 at 5:17 PM Andre Przywara
> <andre.przywara@arm.com> wrote:
> >
> > On Wed, 30 Jan 2019 11:16:07 +0100
> > Tomas Novotny <tomas@novotny.cz> wrote:
> >
> > Hi,
> >  
> > > On Tue, 29 Jan 2019 15:54:07 +0000, Andre Przywara
> > > <andre.przywara@arm.com> wrote:  
> > > > This series gathers all remaining patches we need to enable
> > > > DM_MMC for Allwinner boards. It relies on the clock gates
> > > > framework already merged, and adds the respective gates and
> > > > resets for each SoC. It then teaches the sunxi MMC driver to
> > > > use the clock framework for those reset and gates clocks. The
> > > > "mod clock", responsible for setting the actual interface
> > > > speed, is still handled in the MMC driver, as the DM_CLK part
> > > > of that is not ready yet (and is not trivial). This allows to
> > > > turn on DM_MMC, and gets rid of the doomsday warning message
> > > > every Allwinner board was blessed with for a while.
> > > >
> > > > This series is available at:
> > > > https://github.com/apritzel/u-boot/commits/sunxi-dm-gates  
> > >
> > > I've briefly tested that branch on A83t mainlined tablet (TBS
> > > A711). I was able to boot from SD card and eMMC.
> > >
> > > Just noticed that message:
> > > MMC:   Device 'mmc at 1c11000': seq 1 is in use by 'mmc at 1c10000'
> > > mmc at 1c0f000: 0, mmc at 1c10000: 2, mmc at 1c11000: 1
> > > I guess that this is the mmc1/2 renaming stuff?  
> >
> > I think so. So is this just a warning, and it continues anyway and
> > works?
> >
> > TBH, I don't like this patch 9/9 very much, I actually believe
> > relying on this numbering scheme in /aliases is something odd and
> > fragile. Especially since Linux (and other OSes) seem to get away
> > without it.
> >
> > For MMC, can't we just enumerate them dynamically? AFAIU the MMC
> > driver would not probe a block device successfully on an SDIO
> > device, would it?
> >
> > But for the sake of having something working, I am fine with the
> > patch, at least on a for-now basis.  
> 
> It's not a simple think that 9/9 fix is for,It's something big like
> w/o that we can't get the default env and fastboot devices because we
> always assign mmc1 for these purposes and indeed mmc1 is SDIO for DT
> enumeration.

Yeah, but why is it enumerating mmc1 in the first place? It doesn't
seem to be usable? The MMC layer should know that there is no block
device behind this SDIO thing, so it shouldn't even bother with
creating a device for it. Certainly Linux works this way.

I understand that it fixes the issue, but it's some sort of hack,
especially as it's applied to all DTs.

Cheers,
Andre.

[U-Boot] [PATCH v4 0/9] mmc: sunxi: Enable DM_MMC

[Tomas Novotny]

Hi,

On Wed, 30 Jan 2019 11:46:55 +0000, Andre Przywara <andre.przywara@arm.com>
wrote:
> On Wed, 30 Jan 2019 11:16:07 +0100
> Tomas Novotny <tomas@novotny.cz> wrote:
> 
> Hi,
> 
> > On Tue, 29 Jan 2019 15:54:07 +0000, Andre Przywara
> > <andre.przywara@arm.com> wrote:  
> > > This series gathers all remaining patches we need to enable DM_MMC
> > > for Allwinner boards. It relies on the clock gates framework
> > > already merged, and adds the respective gates and resets for each
> > > SoC. It then teaches the sunxi MMC driver to use the clock
> > > framework for those reset and gates clocks. The "mod clock",
> > > responsible for setting the actual interface speed, is still
> > > handled in the MMC driver, as the DM_CLK part of that is not ready
> > > yet (and is not trivial). This allows to turn on DM_MMC, and gets
> > > rid of the doomsday warning message every Allwinner board was
> > > blessed with for a while.
> > > 
> > > This series is available at:
> > > https://github.com/apritzel/u-boot/commits/sunxi-dm-gates    
> > 
> > I've briefly tested that branch on A83t mainlined tablet (TBS A711).
> > I was able to boot from SD card and eMMC.
> > 
> > Just noticed that message:
> > MMC:   Device 'mmc at 1c11000': seq 1 is in use by 'mmc at 1c10000'
> > mmc at 1c0f000: 0, mmc at 1c10000: 2, mmc at 1c11000: 1
> > I guess that this is the mmc1/2 renaming stuff?  
> 
> I think so. So is this just a warning, and it continues anyway and
> works?

yes. Just a warning and it successfully boots then.

Tomas

> TBH, I don't like this patch 9/9 very much, I actually believe relying
> on this numbering scheme in /aliases is something odd and fragile.
> Especially since Linux (and other OSes) seem to get away without it.
> 
> For MMC, can't we just enumerate them dynamically? AFAIU the MMC driver
> would not probe a block device successfully on an SDIO device, would it?
> 
> But for the sake of having something working, I am fine with the patch,
> at least on a for-now basis.
> 
> Cheers,
> Andre.
>  
> > With 2019.01 I got:
> > MMC:   SUNXI SD/MMC: 0, SUNXI SD/MMC: 1
> > 
> > Tomas
> >   
> > > ---------------------------
> > > 
> > > Jagan, can you please have a look whether this is fine? If you are
> > > not sure about patch 7, you can leave this one out for now.
> > > If you are good with it, can you merge it to sunxi/master and send
> > > the PR, so that it still goes into the release?
> > > We can then fix all the remaining issues until the release.
> > > 
> > > Cheers,
> > > Andre.
> > > 
> > > Changes in v4:
> > > - Add proper A80 support (special MMC config clock)
> > > - Add V3s support (gates and resets)
> > > - Fix pinmux problem when not booting via SD or eMMC
> > > - smaller fixes per ML discussion
> > > Changes for v3:
> > > - Handle clock via CLK framework.
> > > Changes for v2:
> > > - update the 'reset enablement' logic to do
> > >   required SoC's
> > > 
> > > Andre Przywara (5):
> > >   sunxi: clk: enable clk and reset for CCU devices
> > >   sunxi: clk: add MMC gates/resets
> > >   sunxi: clk: A80: add MMC clock support
> > >   mmc: sunxi: Add DM clk and reset support
> > >   sunxi: board: do MMC pinmux setup for DM_MMC builds
> > > 
> > > Jagan Teki (4):
> > >   mmc: sunxi: Add remaining compatible strings
> > >   mmc: sunxi: Add DM_MMC support for H6
> > >   arm: sunxi: Enable DM_MMC
> > >   arm: dts: sunxi: Enumerate MMC2 as MMC1
> > > 
> > >  arch/arm/Kconfig                      |  1 +
> > >  arch/arm/dts/sunxi-u-boot.dtsi        |  4 +++
> > >  arch/arm/mach-sunxi/Kconfig           |  1 -
> > >  board/sunxi/board.c                   | 15 ++++++++++
> > >  configs/Linksprite_pcDuino3_defconfig |  1 -
> > >  drivers/clk/sunxi/clk_a10.c           |  4 +++
> > >  drivers/clk/sunxi/clk_a10s.c          |  3 ++
> > >  drivers/clk/sunxi/clk_a23.c           |  6 ++++
> > >  drivers/clk/sunxi/clk_a31.c           |  8 +++++
> > >  drivers/clk/sunxi/clk_a64.c           |  6 ++++
> > >  drivers/clk/sunxi/clk_a80.c           | 32 +++++++++++++++++++-
> > >  drivers/clk/sunxi/clk_a83t.c          |  6 ++++
> > >  drivers/clk/sunxi/clk_h3.c            |  6 ++++
> > >  drivers/clk/sunxi/clk_h6.c            |  6 ++++
> > >  drivers/clk/sunxi/clk_r40.c           |  8 +++++
> > >  drivers/clk/sunxi/clk_sunxi.c         | 12 ++++++++
> > >  drivers/clk/sunxi/clk_v3s.c           |  6 ++++
> > >  drivers/mmc/sunxi_mmc.c               | 42
> > > +++++++++++++++++++++++---- 18 files changed, 159 insertions(+), 8
> > > deletions(-)   
> > 
> >   
>